Prime University 2A/1, Darus Salam Road, Mirpur-1, Dhaka-1216, Bangladesh Faculty of Engineering Department of Electrical and Electronic

Engineering Course Conducted by: Shuvodip Das Digital Electronics EEE 357 Lecture 02 Logic Gates Introduction Boolean functions may be practically implemented by using electronic gates. The following points are important to understand.
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Electronic gates require a power supply. Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and 5V representing logic 0 and logic 1 respectively. The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5V representing logic 0 and logic 1 respectively. In general, there is only one output to a logic gate except in some special cases. There is always a time delay between an input being applied and the output responding.

Truth Tables Truth tables are used to help show the function of a logic gate. If you are unsure about truth tables and need guidence on how go about drawning them for individual gates or logic circuits then use the truth table section link. Logic gates Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth tables.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.

Table 1: Logic gate symbols

Table 2 is a summary truth table of the input/output combinations for the NOT gate together with all possible input/output combinations for the other gate functions. Also note that a truth table with 'n' inputs has 2n rows. You can compare the outputs of different gates. Table 2: Logic gates representation using the Truth table

Universal Gates: A universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the other way around!! Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the other way around!! NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion. NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation. EXNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion. The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT can be generated. NAND Gate is a Universal Gate: To prove that any Boolean function can be implemented using only NAND gates, we will show that the AND, OR, and NOT operations can be performed using only these gates.

Implementing an Inverter Using only NAND Gate The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate). 1. All NAND input pins connect to the input signal A gives an output A.

2. One NAND input pin is connected to the input signal A while all other input pins are connected to logic 1. The output will be A.

Implementing AND Using only NAND Gates An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND gate with its output complemented by a NAND gate inverter).

Implementing OR Using only NAND Gates An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters).

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions. NOR Gate is a Universal Gate: To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND, OR, and NOT operations can be performed using only these gates. Implementing an Inverter Using only NOR Gate The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate). 1. All NOR input pins connect to the input signal A gives an output A.

2. One NOR input pin is connected to the input signal A while all other input pins are connected to logic 0. The output will be A.

Implementing OR Using only NOR Gates An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter)

Implementing AND Using only NOR Gates An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR gate with all its inputs complemented by NOR gate inverters)

Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions. Diode Logic Gates: In diode logic, electrically operated switches are implemented by diodes: when forward biased, a diode switch is closed; when backward biased, the switch is open. There are two kinds of diode logic gates OR and AND. It is not possible to construct NOT diode gate. The explanations below are true for positive logic (high voltage represents logical 1 and low voltage represents logical 0).

In a diode OR gate, the output voltage is high if only one input voltage is high. The output voltage is low if all the input voltages are low. OR logic gates are implemented by parallel connected normally open switches. So, in diode OR logic gates, the input voltage sources are connected to diode anodes. Diode cathodes are joined to the output (node 1 in the figure), which is connected through the pull-down resistor R1 to ground. Input logical one. If the voltage of a particular input voltage source is high (input logical 1), the according diode is forward biased and this diode switch is closed. The input source passes current through the diode and creates high voltage drop across the resistor R1 (output logical 1). The rest of diodes connected to low input voltage (input logical 0s) are backward biased and their input sources (grounds) are disconnected from the output.
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Input logical zeros. If all the input voltages are low (input logical 0), the voltage drops across the diodes are zero. These diode switches are open and the input sources (grounds) are disconnected from the output. No current flows through the resistor. The output voltage is low (output logical 0) and the output resistance is R1. If two diode OR logic gates are cascaded, they behave as current-sourcing logic gates: if the first gate produces high output voltage, the second gate consumes current from the first one. If the first gate produces low output voltage, the second gate does not inject current into the output of the first one. A diode OR gate does not use its own power supply. The input sources with high voltage (logical 1) supply the load through the forward-biased diodes. AND logic gate: AND logic gates are implemented by series connected normally open switches. So, diode AND logic gates should be implemented by series connected diode switches (like an NMOS AND gate that is implemented by series connected transistor switches). However, in contrast to transistors, diodes are two-terminal switching elements, in which the input and output are not separated but they are the same. As a result, series connected diode switches cannot be driven by grounded input voltage sources. To solve this problem, diode AND gates are constructed in the same manner as OR diode gates - by parallel connected diode switches.[nb 1] However, to obtain AND instead OR function according to De Morgan's laws, the input and output logical variables are inverted: Y = NOT ((NOT (X1) OR NOT (X2)) = NOT (NOT (X1 AND X2)) = X1 AND X2, where X1 and X2 are the two input logical variables; Y is the output variable. Therefore, the diode AND logic gate is a modified diode OR logic gate: the diode AND gate is actually a diode OR gate with inverted inputs and output. Implementation

In a diode AND gate, the output voltage is high if all the input voltages are high. The output voltage is low if only one input voltage is low. To realize the basic idea, the diodes are reverse connected and forward biased by an additional voltage source +V (a power supply) through the pull-up resistor R1. The input voltage sources are connected in
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opposite direction to the supplying voltage source (traveling along the loop +V - R1 - D - Vin). To invert the output voltage and to get a grounded output, the complementary voltage drop (+V - VR1) between the output and ground is taken as an output instead the floating voltage drop VR1 across the resistor. Input logical ones. When all the input voltages are high, they "neutralize" the biasing supply voltage +V. The voltage drops across the diodes are zero and these diode switches are open. The output voltage is high (output logical 1) since no current flows through the resistor and there is no voltage drop across it. The output resistance is R1. Hence, the behavior of the diode switches is reversed whereas in diode OR logic gates diodes act as normally open switches, in diode AND logic gates diodes act as normally closed switches. Input logical zero. If the voltage of some input voltage source is low (input logical 0), the power supply passes current through the resistor, diode and the input source. The diode is forward biased (the diode switch is closed) and the output voltage drop across the diode is low (output logical 0). The output resistance is low and is determined by the input source. The rest of diodes connected to high input voltages (input logical 1s) are backward biased and their input sources are disconnected from the output Node 1. If two diode AND logic gates are cascaded, they behave as current-sinking logic gates: if the first gate produces high output voltage, the second gate does not consume current from the first one; if the first gate produces low output voltage, the second gate injects current into the output of the first one. A diode AND gate uses its own power supply to drive the load through the pull-up resistor. Transistor Logic Gates: Transistor AND Gate:

The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to ground may be less than a volt and can be used as a logic 0 in the TTL logic family.

Transistor OR Gate: The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to ground may be less than a volt and can be used as a logic 0 in the TTL logic family.

Transistor NAND Gate:

The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to ground may be less than a volt and can be used as a logic 0 in the TTL logic family. Transistor NOR Gate: The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to ground may be less than a volt and can be used as a logic 0 in the TTL logic family.

Transistor NOR Gate:

The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to ground may be less than a volt and can be used as a logic 0 in the TTL logic family. CMOS Logic Gates
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CMOS (complementary metal-oxide-semiconductor) technology is used predominantly to create digital circuitry. The fundamental building blocks of CMOS circuits are P-type and N-type MOSFET transistors. A P-type MOSFET can be modeled as a switch that is closed when the input voltage is low (0 V) and open when the input voltage is high (5 V). A N-type MOSFET can be modeled as a switch that is closed when the input voltage is high (5 V) and open when the input voltage is low (0 V). The basic idea for CMOS technology is to combine P-type and N-type MOSFETs such that there is never a conducting path from the supply voltage (5 V) to ground. As a consequence, CMOS circuits consume very little energy.

Figure 3.1: P-type and N-type MOSFETS.

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CMOS Inverter
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The circuit below is the simplest CMOS logic gate. When a low voltage (0 V) is applied at the input, the top transitor (P-type) is conducting (switch closed) while the bottom transitor behaves like an open circuit. Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the input, the bottom transitor (N-type) is conducting (switch closed) while the top transitor behaves like an open circuit. Hence, the ouput voltage is low (0 V). The function of this gate can be summarized by the following table: Input Output High Low Low High

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The output is the opposite of the input - this gate inverts the input. Notice that always one of the transistor will be an open circuit and no current flows from the supply voltage to ground. Figure 3.2: Inverter Circuit and Standard Symbol

NAND Gate
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The circuit below has two inputs and one output. Whenever at least one of the inputs is low, the corresponding P-type transistor will be conducting while the N-type transistor will be closed. Consequently, the ouput voltage will be high. Conversely, if both inputs are high, then both P-type transistors at the top will be open circuits and both N-type transistors will be conducting. Hence, the output voltage is low. The function of this gate can be summarized by the following table:

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V1

V2

Output

Low Low High Low High High High Low High High High Low

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If logical 1's are associated with high voltages then the function of this gate is called NAND for negated AND. Again, there is never a conducting path from the supply voltage to ground. Figure 3.3: NAND Circuit and Standard Symbol

NOR Gate
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The circuit below has two inputs and one output. Whenever at least one of the inputs is high, the corresponding N-type transistor will be closed while the P-type transistor will be open. Consequently, the ouput voltage will be low. Conversely, if both inputs are low, then both P-type transistors at the top will be closed circuits and the N-type transistors will be open. Hence, the output voltage is high. The function of this gate can be summarized by the following table:

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V1

V2

Output

Low Low High Low High Low High Low Low High High Low

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If logical 1's are associated with high voltages then the function of this gate is called NOR for negated OR. Again, there is never a conducting path from the supply voltage to ground. Figure 3.4: NOR Circuit and Standard Symbol

Logic Family: A "logic family" may also refer to a set of techniques used to implement logic within VLSI integrated circuits such as central processors, memories, or other complex functions. Some such logic families use static techniques to minimize design complexity. Other such logic families, such as domino logic, use clocked dynamic techniques to minimize size, power consumption, and delay. Classification of Logic Family: The list of packaged building-block logic families can be divided into categories, listed here in rough chronological order of introduction along with their usual abbreviations:
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Resistortransistor logic (RTL) o Direct-coupled transistor logic (DCTL)

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o Resistorcapacitortransistor logic (RCTL) Diodetransistor logic (DTL) o Complemented transistor diode logic (CTDL) o High-threshold logic (HTL) Emitter-coupled logic (ECL) o Positive emitter-coupled logic (PECL) o Low-voltage positive emitter-coupled logic (LVPECL) Gunning transceiver logic (GTL) Transistortransistor logic (TTL) P-type metaloxidesemiconductor logic (PMOS) N-type metaloxidesemiconductor logic (NMOS) o Depletion-load NMOS logic Complementary metaloxidesemiconductor logic (CMOS) Bipolar complementary metaloxidesemiconductor logic (BiCMOS) Integrated injection logic (I2L)

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