2011 MSc Project Brief

Name Supervisor Co-supervisor

.

Swami Elampooranan K T Dr. Peter Wilson

ID no

23482478

Email

sekt1g10@ecs.soton.ac.uk

2nd Examiner

AL-HASHIMI, Bashir

Project title

RC Based PLL design for Sigma Delta Converter

Description of project
(briefly introduce the subject of the project, describe your main aims and the experiments, procedures, design stages you expect to carry out)

A PLL (Phase locked loop) is to be designed and implemented which generate a configurable clock range of 10Mhz to 50Mhz for a sigma delta ADC. The design is implemented in IBM process IBM 8RF with a supply voltage of 1.2V. The noise floor of the oscillator is expected to be at least -80db at operation range. The PLL reference of 10MHz or 20Mhz is expected which leaves the PLL loopbandwith within possible range of on chip RC values. The PLL will be designed for fosc of 100Mhz and final output stage will consist of a frequency divider to provide the exact clock required. The basic blocks of the PLL are PFD, Charge Pump, Loop Filter, VCO and Frequency divider in a feedback. PFD This is will be implemented using a resettable D-flip-flop type circuitry. As we deploy a ring oscillator as VCO this type of PFD is chosen to ensure wide range of functionality as EXOR or any other type will provide only phase error and not frequency error. The initial frequency of the ring oscillator varies in wide ranges. Charge Pump This will be implemented for using the current sink and current source. The signals from the PFD consist of a UP and Down which provides positive and negative error signals. A opamp can be used to convert it to a single end output but charge pump model is better suited for this type of application. Loop Filter Onchip resister and capacitor. A high tolerance resister and capacitor are deployed to ensure accuracy. VCO Ring oscillator with current starving technique with a Pmos and Nmos transistor in cascade with inverters. The ring oscillator designed will be a 5 stage single ended ring oscillator which will ensure smooth functionality with these operating frequencies. Frequency Divider A programmable frequency divider with a divideby 64 steps will be designed to enable it to configure for the range. Final stage will consist of a fixed frequency divider to enable it reduce the VCO output to required frequency range. All the blocks will be evaluated in cadence for its functionality and then layout are implemented in cadence. The final deliverable will be to produce a design which is fully functional and meets the specification after the parasitic extraction.

Does your project involve laboratory work?

NO

Does your project involve human subjects?

NO

Work Plan and Milestones

Week #
week beginning : 1 13/6 2 20/6 3 27/6 4 4/7 5 11/7 6 18/7 7 25/7 8 1/8 9 8/8 10 15/8 11 22/8 12 29/8 13 5/9 14 12/9 15 19/9

Activities and milestones Backround Research PFD schematics Charge pump schemactics Frequency Divider VCO schematics Layout for blocks Post layout changes Writing-up Milestone demonstrate to sup/examiner Milestone dissertation draft complete Final corrections Milestone Hand-in

* *

When you have completed this brief you should discuss it with your supervisor. You should then electronically submit as a PDF document via the project homepage