MULTI LEVEL METALLIZATION

S.SANGAMESHWAR RAO
ENGINEERING PHYSICS IIT DELHI

INDO-GERMAN WINTER ACADEMY 2005 JAMSHEDPUR, INDIA

OVERVIEW
Metallization Importance of Multilevel metallization
RC Time Delay

Interconnection materials
Metals Junction spiking, Stress migration, Electromigration Properties of Al, Cu, W etc Dielectrics Diffusion Barriers and Adhesion Promoters

Metallization processing
PVD, CVD, Electroplating Damascene Process Chemical Mechanical Polishing

Conclusion References
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Metallization
Metallization is the process that makes accessible the IC to the outside world through conducting pads. Doped silicon conduct electricity but have large resistance and lack interconnecting facility Thin conductive metal films (Al, Cu, Au, Ag etc) are used as interconnects between Si and external leads
Global Interconnects First Level Dielectric Local Interconnects

Ref: Modified Picture from SILICON VLSI TECHNOLOGY By Plummer et al

Why interconnect structures are important?

Rough Estimation of Interconnect RC Time Delay
C

As technology progresses, Ls decreases

delay increases

RC

R
W Ls

To decrease RC delay -, , L should take low values

L

Fig: Interconnection delay and device delay

Dielectric

Metal

Global Interconnect
R=L WH C = HL Ls RC = L2 WLs
Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 4 87-151

Needs of new technology

Lower resistivity metal for interconnect wiring Lower dielectric constant material for the interlayer dielectric Smaller wire lengths-Multilevel Metallization

Multi level metallization

Three dimensional network of interconnections is given the name multilevel interconnections Metal interconnections
span several planes isolated by the insulating dielectric layers interconnected by the wiring in the third dimension through the holes in the dielectric planes Fig: Two level Metallization

Vias Global Interconnects Second level dielectric First Level Dielectric Local Interconnects

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Ref: Modified Picture from SILICON VLSI TECHNOLOGY By Plummer et al

Uses -Multi level metallization

Reduced interconnection lengths-enhanced performance due to reduced RC

Densification-higher package densities

Design flexibility

Interconnection materials
Metals
Metal Issues
Junction spiking Electromigration Stress migration

Important metals
Aluminum Copper Tungsten Silver, Gold

Dielectrics Diffusion barriers and Adhesion promoters

Metals Requirements
Low resistivity Easy to deposit Easy to etch and planarize High melting point
High electromigration resistance

Mechanical stability, adherence to interlayer dielectrics and other materials on chip

Substrate matched coefficient of thermal expansion Low stress, high stress migration resistance

Metals Requirements.contd
Controlled microstructure
Preferably uniform large grains and smooth surfaces

Oxidation/corrosion resistance
Low chemical reactivity Ideally passivates itself

Compatible with surrounding materials and their processing Bondable to wirings in package Environmentally safe material during processing and actual use, and recyclable Reliable Low cost
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Metals
Property\Metal Resistivity Youngs modulus(x10-11 dyn cm-2) Thermal conductivity(Wcm-1) Coeff. of thermal expansion CTE x 106(0C-1) M.P (0C) Specific heat capacity(Jkg-1K-1) Corrosion in air Adhesion to SiO2 Delay Thermal stress per degree for films on Si(x107 dyn cm-2 0C-1) Cu 1.67 12.98 3.98 17 1085 38 Poor Poor 2.3 2.5 Ag 1.59 8.27 4.25 19.1 962 234 Poor Poor 2.2 1.9 Au 2.35 7.85 3.15 14.2 1064 132 Excellent Poor 3.2 1.2 Al 2.66 7.06 2.358 23.5 660 917 Good Good 3.7 2.1 W 5.65 41.1 1.74 4.5 3387 138 Good Poor 7.8 0.8

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Aluminum
Early ICs used pure Al as the interconnect material Low resistivity Strong adhesion with Si Corrosion resistant

Problems with pure Al Junction spiking Electromigration Stress migration Later ICs used Al alloyed with Cu
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Junction spiking
Consider Al-Si contact
Solubility of Si in Al is 0. 5 wt% at 4500C Si will dissolve into the Al during annealing (at 4500C)

Solution
Add Si to the Al
Al spikes

Introduce a barrier metal layer between the Al and the Si substrate. (TiN)

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Stress migration
Due to difference between coefficient of thermal expansion for Al and Si Al 23 x 10-6 0C-1 and Si 2.6 x 10-6 0C-1 High compressive stresses in Al at high temperatures Movement of Al occurs along grain boundaries Whole grains of Al pushed upward forming hillocks Under tensile stress voids are formed
Al hillock
Compressive stress (due to thermal expansion difference between film and substrate)

Grain Boundary

Al SiO2 Si substrate
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Stress migrationcontd
Consequences Electrical shorts between interconnect levels Rough surface topography making lithography and etch difficult

Solution
Addition of elements that have limited solubility Ex:- Cu atoms segregate and precipitate preferentially along the grain boundaries suppressing hillock formation

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Electromigration
Transport of mass in metals under the influence of high current Occurs by transfer of momentum from electrons to the positive metal ions High current densities in the smaller devices are responsible for electron migration Grain boundary diffusion is the primary vehicle of mass transport Metal in some regions pile up and voids form in other regions
Void Hillock formation Al film SiO2
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Electron Flow

Solutions - Electromigration

Alloying with copper (Al with 0.5%Cu) Multilayer structure

Shunt layer provides alternative path for current flow If shunt layer has high melting point and strong mechanical properties, they can be more rigid and act as barrier to hillock and void formation

Oxide
Current Flow

Al Ti Void
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Tungsten
Good corrosion resistance Electromigration and stress migration stability Excellent deposition methods Sometimes used for filling of vias called plugs High resistivity Poor adhesion (Adhesion promoter required-Ti/TiN)

Gold
Low resistivity

Very inert; adheres poorly Very costly

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Copper
Benefits
Higher conductivity More electromigration resistance Higher ultimate tensile strength Higher melting point, low CTE Higher thermal conductivity, high specific heat, lesser Joule heating

Draw backs
Lack of feasible dry etching method Lack of self passivating oxide similar to Al2O3 on Al Poor adhesion to dielectric materials such as SiO2 and low-k polymers

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Silicides
Silicon forms stable metallic compound (MSix) with metal, called silicide Low resistivity and high thermal stability of metal silicides make them suitable for VLSI applications Silicides be used as local interconnects and adhesion promoters

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Diffusion barriers and adhesion promoters

Objective: To find adhesion promoter and diffusion barrier Adhesion Cu has poor adhesion properties Need a adhesive material where chemical bonding across interface provides stability Silicides such as TiSi2 can be used as adhesion promoter but doesnt have good barrier properties TiSi2 with another barrier layer on top of it can be used
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Diffusion barriers and adhesion promotersContd

Barrier
To stop reaction between metals (W, Al etc) and Si or between two layers Passive barrier (TiN) Stuffed barrier (Ti-W alloy) Sacrificial barrier
TiN has contact resistance higher barrier than TiSi2 Bilayer structure of TiSi2 /TiN is used as adhesion promoter and diffusion barrier
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Fig: Adhesion and barrier layers

Dielectrics
Dielectric Requirements Small dielectric constant High breakdown voltage Good adhesion High temperature stability Low stress Some dielectrics Conventional SiO2-high dielectric constant-high RC delay New materials Fluorine doped SiO2 ~3 Polymers ~1.9-2.9 Aerogels ~1.01-2.0
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Multilevel Metallization Processing

Metal deposition
PVD
Evaporation
Resistance heated Evaporation Inductively heated evaporation Electron beam Evaporation

Sputtering
DC, RF sputtering Magnetron sputtering

CVD Electroplating

Via and trench formation Chemical mechanical Planarization

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Fig: Two level Metallization

Vias Global Interconnects Second level dielectric First Level Dielectric Local Interconnects

Fig: SEM Image showing trenches and vias

Ref: SILICON VLSI TECHNOLOGY By Plummer et al 25

Physical Vapor Deposition

1. Evaporation 2. Sputtering
Resistance heated evaporation

Evaporation

E-Beam Evaporation

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Ref: Prof.S.Kal, IIT Kharagpur

Sputter Deposition
Simple DC sputtering is used for elemental metal deposition For deposition of insulating materials such as SiO2, Si3N4, an RF plasma is used Application of magnetic field increases ion bombardment rate Magnetic sputtering

Earlier generation ICs- Evaporation Present technique Sputtering- Better step coverage
Ref: Prof.S.Kal, IIT Kharagpur
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Step Coverage
Conformal step coverage refers to uniform thickness on both horizontal and vertical surfaces In evaporation, the deposition species travel essentially in straight lines because of very low pressure Step coverage is very poor

Solution:
1) Rotate the wafer

2) Sputtering on heated substances to cause reflow

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Ref: Prof.S.Kal, IIT Karagpur

Bias sputtering
If substrate and deposited films are conductive, it is possible to adjust the bias on the substrate with respect to the plasma Placing a negative bias on the substrate, the ion bombardment of the substrate is increased Since the sputter etched film may redeposit on the wafer if sputtered at low bias, a net improvement in the step coverage may be achieved

29 Ref: Prof.S.Kal, IIT Kharagpur

Chemical Vapor deposition

Gases are introduced into the substrate that react and form the desired film on the surface of the substrate Can coat large number of wafers at same time Better conformal step coverage than PVD over a wide range of topographic profiles

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Silicide Deposition
Direct deposition and selective etching
Sputtering from a composite target Co-sputtering from two targets Co-evaporation of metal and Si CVD

Self-aligned silicide process

31 Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151

Common deposition techniques

Metal Al Process Magnetron Sputter deposition Magnetron Sputter deposition (standard, ionized, or collimated) Low Pressure CVD Sputter and surface reaction Reactive Sputter Deposition CVD Cu Electroplating
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Ti and Ti-W W TiSi2 TiN

Aluminum
CVD not good for alloys
Unwanted reactions between the precursors for the various metals

DC magnetron sputtering is used

High deposition rates

Heat the wafers to 150-3500C-To improve step coverage Further high temperatures 450-5500C For filling deep contacts and vias
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Etching of the metal or dielectric films

Metallization + Lithography+ Etching = Desired pattern Dry etching- also called reactive ion etching Chlorine and chlorine containing gases are used to etch Al Lack of volatile copper species- Dry etching not possible for Cu Wet etching in chemicals - Not good option as it is isotropic

Solution Damascene Process

Etching

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Copper
Step coverage poor with PVD methods Electroplating
Cu2+ + 2eCu Thin seed layer (Cu) is required for electrical contact for electroplating Seed layer by sputtering or CVD

Excellent filling of vias with electroplating

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Damascene Technology
Via and trench formation Adhesion and Barrier Layer deposition Chemical Mechanical Planarization Second Level Dielectric Deposition Via and trench formation

Dry etching is not required

36 Ref: Multilevel interconnections for ULSI era, S.P.Murarka, MSE, R(19), 87-151

Damascene Technology
Trench first approach Via first approach

Major Drawback of Trench first approach: After trench formation, photoresist completely pools down into the trench Forming fine vias in thick photoresists becomes problem Via first approach is most preferred
Ref: www.icknowledge.com/threshold_simonton/techtrends01.pdf

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Chemical Mechanical Polishing

To achieve planar surface over the entire chip and wafer Referred to as global planarity Dielectrics, poly silicon or oxide and various metal films can be polished

Components Mechanism
Combination of chemical and mechanical effects Abrasive particles in slurry grind against material and loosens it Chemicals in slurry etch and dissolve the material Chemicals help in damage free sample Surface to be polished (Wafer) Slurry abrasive + chemical component Polishing pad
Fig: Schematic set-up for CMP

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Ref: http://www.agc.co.jp/english/products/semiconductor/cmp.html

Early 2 level structure

After CMP

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Alternatives for future interconnections

Optical Interconnections Higher bandwidth, higher density Elimination of cross-talk High TC superconductors Zero resistance below TC High current densities can be carried

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Conclusion
Interconnect parameter now dominate nearly all aspects of IC performance such as delay, power dissipation, and electromigration Multi level metallization reduces the RC delay Different physical properties of the materials and deposition techniques have to be considered Sometimes multilayer structures may have to be used (adhesion & barrier layers etc) Al as the interconnect material has limitations, Cu is being used now But even Cu has some limitations. New technologies like damascene, CMP have been developed to overcome the limitations of etching etc
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References
1. Multilevel interconnections for ULSI era, S.P.Murarka, Materials Science and Engineering, R(19), 87-151 2. 3. 4. 5. SILICON VLSI TECHNOLOGY By Plummer et al VLSI Metallization, Prof.S.kal, IIT Kaharagpur Microchip Fabrication, Peter van Zant, Mc Graw hill Fundamentals of Semiconductor Processing Technologies, Badih-el Kareh, Kluwer Academic Publishers 6. 7. 8. Semiconductor Devices Physics and Technology, S.M.Sze, Wiley http://www.agc.co.jp/english/products/semiconductor/cmp.html www.icknowledge.com/threshold_simonton/techtrends01.pdf
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