NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO

NT 511740C5J Data Sheet

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO

TABLE OF CONTENTS
1. Description.............................................................................................3 2. Features.................................................................................................3 3. Product Family........................................................................................3 4. Pin Configuration....................................................................................4 5. Block Diagram........................................................................................5 6. Electrical Characteristics.......................................................................6 7. DC Characteristics.................................................................................7 8. AC Characteristics.................................................................................8~11 9. DRAM AC Timing Waveforms..............................................................12~18

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO

1. DESCRIPTION
The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. The NT511740C5J achieves high integration , high-speed operation , and lowpower consumption due to quadruple polysilicon double metal CMOS. The NT511740C5J is available in a 26/24-pin plastic SOJ.

2. FEATURES l l l l l l l l l 4,194,304-word x 4-bit configuration Single 5V power supply,+/-10% tolerance Input :TTL compatible , low input capacitance Output :TTL compatible , 3-state Refresh :2048 cycles/32 ms Fast page mode with EDO, read modify write capability /CAS before /RAS refresh, hidden refresh, /RAS-only refresh capability Multi-bit test mode capability Package options: 26/24-Pin 300 mil plastic SOJ
3. PRO D UCT FAM ILY Access Tim e (M ax.) Fam ily NT511740C5J-50 NT511740C5J-60 NT511740C5J-70 t RA C tA A 50ns 25ns 60 ns 30 ns 70 ns 35 ns t CA C 13ns 15 ns 20 ns t O EA 13ns 15 ns 20 ns (M in.) 84ns 104 ns 124 ns Operation(M ax.) Standby(M ax.) 660m W 605m W 5.5 m W 550 m W C ycle Time Power Dissipation

(SOJ26/24-P300)

(Product:NT511740C5J-XX) XX indicates speed rank.

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO

4. PIN CONFIGURATION (TOPVIEW)

Vcc DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21
Vss

DQ4 DQ3 CAS OE A9

A10 A0 A1 A2 A3 Vcc

8 9 10 11 12 13

19 18 17 16 15 14

A8 A7 A6 A5 A4 Vss

26/24-Pin Plastic SOJ

Pin Name
A0-A10 RAS CAS DQ1-DQ4 OE WE Vcc Vss NC

Function
Adress input Row Adress Strobe Column Adress Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5v) Ground(0V) No Connection

Note:The same power supply voltage must be provided to every Vcc pin , and the same GND voltage level must be provided to every Vss pin.

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NANYA TECHNOLOGY CORP

NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 5. BLOCK DIAGRAM
RAS CAS
Timing Generator

Timing Generator

11

Column Address Buffer

11

Column Decoders

Write Clock Generator

WE OE
4

A0-A10

Internal Address Counter

Output Buffers
4

Refresh Control Clock

Sense Amplifiers

I/O Selector

4 4

DQ1-DQ4

Input Buffers

11

Row Address Buffer

11

Row Decoders

Word Drivers

Memory Cells

VCC On Chip VBB Generator On Chip IVCC Generator VSS

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Cuttent Po/WEr Dissipation Operation Temperature Storage Temperature Recommended Operating Conditions Parameter Po/WEr Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -0.3 Typ. 5.0 0 Symbol VIN,VOUT VCC IOS PD* Topr Tstg *:Ta = 25
o

Rating -0.3 to VCC+0.3 -0.5 to 7 50 1 0 to 70 -55 to 150 C (Ta=0 C to70 Max. 5.5 0 VCC+0.3 0.8
o o

Unit V V mA W o C
o

C) Unit V V V V

Capacitance (Vcc = 5V+/-10%,Ta=25 Symbol Typ. CIN1 CIN2 CI/O o

Parameter Input Capacitance (A0-A10)

C , f=1 MHZ) Max. Unit 5 7 7 pF pF pF

Input Capacitance (/RAS,/CAS,/WE,/OE) Output Capacitance (DQ1-DQ4)

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
7. DC Characteristics (Vcc=5V+/-10% ,Ta=0 Parameter Output High Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (/RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (/CAS before /RAS Refresh) Average Power Supply Current (Fast Page Mode) NotesG Symbol V OH V OL IL1 IL0 Condition
IOH =-5.0 mA IOL =4.2 mA 0V<=VI<=6.5V; All other pins not under test = 0V DQ disable 0V<=Vo<=5.5V /RAS,CAC cycling,
o

C to 70

C)

NT511740C NT511740C NT511740C 5J-50 5J-60 5J-70

Min. Max. Min. Max. Min. Max. 2.4 0 -10 -10 Vcc 0.4 10 10 2.4 0 -10 -10 Vcc 0.4 10 10 2.4 0 -10 -10 Vcc 0.4 10 10

Unit Note V V A A

Icc1 Icc2

tRC = Min. /RAS , /CAS=VIH /RAS, /CAS

120 2 1

110 2 1

100 2 1

mA

1,2

mA

>=Vcc-0.2V /RAS cycling,

Icc3

/CAS

= VIH,

120

110

110

mA

1,2

tRC=Min.

Icc5

/RAS= VIH, /CAS= VIL, DQ = enable /RAS cycling,

mA

Icc6

/CAS before /RAS

110

100

90

mA

1,2

/RAS=VIL,

Icc7

/CAS cycling tpc=Min.

110

100

90

mA

1,3

1. ICC Max. is specified as Icc for output open condition. 2. Address can be changed once or less while /RAS=VIL. 3. Address can be changed once or less while /CAS=VIH.

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 8. AC Characteristics (1/3)
(Vcc=5V ,Ta=0 oC to 70 oC ) Note:1,2,3,12,13 10% NT511740C5J- NT511740C5J- NT511740C5J50 60 70 Unit Note Symbol Min. Max. Min. Max. Min. Max. tRC tRWC tHPC tPRWC tRAC tCAC tAA tCPA t/OEA tCLZ tDOH tCEZ tREZ t/OEZ t/WEZ tT tREF tRP t/RAS t/RASP 84 110 20 58 0 5 0 0 0 0 1 30 50 50 50 13 25 30 13 13 13 13 13 50 32 10,000 100,000 104 135 25 68 0 5 0 0 0 0 1 40 60 60 60 15 30 35 15 15 15 15 15 50 32 10,000 124 160 30 78 0 5 0 0 0 0 1 50 70 70 20 35 40 20 20 20 20 20 50 32 10,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 7,8 7,8 7 7 3 4,5,6 4,5 4,6 4 4 4

Parameter

Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time form /RAS Access Time form /CAS Access Time form Column Address Access Time form /CAS Precharge Access Time form /OE Output Low Impedance Time from /CAS Data Output Hold After /CAS Low /CAS to Data Output Buffer Turn-off Delay Time /RAS to Data Output Buffer Turn-off Time /OE to Data Output Buffer Turn-off /WE to Data Output Buffer Turn-off Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode with EDO) Delay Delay Time Delay

100,000 70

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO AC Characteristics (2/3)
NT10511740C5J50 NT511740C5J60 Min. 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30 0 0 0 0 Max. 10,000 45 30 NT511740C5J70 Unit Min. /RAS Hold Time /RAS Hold Time referenced to /OE /CAS Precharge Time (Fast Page Mode with EDO) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge Time /OE Hold Time from /CAS (DQ Disable) /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS Write Command Set-up Time Max. 10,000 37 25 Min. 13 13 13 13 45 5 40 5 14 12 0 13 0 13 35 0 0 0 0 Max. 10,000 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 10 5 6 Note

Parameter

Symbol

tRSH tROH tCP t/CAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS

7 7 7 7 35 5 30 5 11 9 0 7 0 7 25 0 0 0 0

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO AC Characteristics (3/3)
(Vcc=5V +/-10% ,Ta=0 oC to 70 oC) Note 1,2,3,12,13
Unit Min. Max. Min. 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 10 10 Max. Min. 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 10 10 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 11 11 Note

NT511740C5J- NT511740C5J- NT511740A5J50 60 70

Parameter
Write Command Hold Time Write Command Pulse Width /WE Pulse Width (DQ Disable) /OE Command Hold Time /OE Precharge Time /OE Command Hold Time Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /OE to Data-in Delay Time /CAS to /WE Delay Time Column Address to /WE Delay Time /RAS to /WE Delay Time /CAS Precharge /WE Delay Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode)

Symbol tWCH tWP tWPE t/OEH t/OEP tOCH tRWL tCWL tDS tDH t/OED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH
7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10 10 10

10

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO Notes: 1. A start-up delay of 200 s is required after po/WEr-up,follo/WEd by a minimum of eight initialization cycles (/RAS-only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT=2 ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured bet/WEen VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only . If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only . If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), t/WEZ (Max.) and t/OEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition . 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data tWCS sheet as electrical characteristics only . If tWCS (Min.), the cycle is an early write cycle and the tCWD data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD (Min.) , (Min.) , tAWD (Min.) and tCPWD (Min.), the cycle is a read modify write cycle tAWD tCPWD tRWD tRWD and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge in an /OE control write cycle or a read modify write cycle . 12. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not used and each DQ pin now accesses 8-bit locations .Since all 4 DQ pins are used, a total of 32 data bits can be written in parallel into the memory array. In a read cycle, if 8 data bits are equal the DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a /RAS-only refresh cycle or a /CAS before /RAS refresh cycle. 13. In a test mode read cycle , the value of access time parameters is delayed for 5 ns for the specified value . These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

11

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO 9.DRAM AC Timing Waveforms

Read Cycle R A S VIH

VIL
tCSH tCRP tRCD tRAD tRAL tASR tRAH tASC tCAH tRAS

tRC tRP tCRP

C A S VIH
VIL

tRSH tCAS

Address VIL

VIH

Row
tRCS

Column
tRCH tRRH tAA tROH tREZ

W E VIL

VIH

OE

VIH VIL
tCAC tRAC

tOEA

tCEZ tOEZ tCLZ

D Q VIH
VIL

Open

Valid Data-out

"H" or "L" Write Cycle(Early Write) R A S VIH

VIL
tCSH tCRP tRCD tRAD tRAL tASR tRAH tASC tCAH tRAS

tRC tRP tCRP

C A S VIH
VIL

tRSH tCAS

Address VIL

VIH

Row
tWCS

Column
tCWL tWCH tWP

W E VIL

VIH

tRWL

OE

VIH VIL
tDS tDH Valid data-in

D Q VIH
VIL

Open

"H" or "L"

12

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
Read Modify Write Cycle R A S VIH
VIL
tCRP tRCD tCAS tRAS tCRP tCSH tRSH

tRWC

tRP

C A S VIH
VIL
tASR tRAH

tASC

Address

VIH VIL

tCAH

Row
tRAD

Column
tCWD tRWD tCWL tRWL tWP tAWD tRCS tOEA tOED tCAC tRAC tOEZ tCLZ Valid Data-out tDS tDH Valid Data-in tOEH

W E VIL

VIH

tAA

OE

VIH VIL

DQ

VIH VIL

"H" or "L"

13

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
Fast Page Mode Read Cycle (Part-1)
tRASP tRP tRHCP tHPC tCRP

R A S VIH
VIL
tRCD tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tASC tCAS tCP tCAS tCP

C A S VIH
VIL

tCAS

tCAH

Address

VIH VIL

Row
tRCS

Column

Column

Column
tRRH tCHO tOCH

WE

VIH VIL
tRAC tAA tAA tOEA tCAC tCLZ Valid Data-out tCPA tCAC tDOH

tOEP

tOEP

OE

VIH VIL

tAA tOEA tOEZ

Valid Data-out

tOEA tCAC tOEZ

Valid Data-out

tREZ
Valid Data-out

DQ

VIH VIL

"H" or "L"

Fast Page Mode Read Cycle(Part-2)

tRASP tRP tRHCP tCRP tHPC tCRP

R A S VIH
VIL
tRCD tCAS tRAD tCSH tASR tRAH tASC tCAH tASC tCAH tCP tCAS tCP

CAS

VIH VIL

tCAS

tASC

tCAH

Address

VIH VIL

Row
tRCS

Column

Column
tRCS tRCH

Column

WE

VIH VIL
tRAC tAA

tWPE

tAA tAA tCPA

OE

VIH VIL

tOEA tCAC tCAC tCLZ tWEZ Valid Data-out tCAC Valid Data-out tDOH tCEZ Valid Data-out

D Q VIH
VIL

"H" or "L"

14

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
Fast page Mode Write Cycle(Early Write)
tRASP tRP

RAS

VIH VIL
tHPC tCRP tHPC tCP tCAS tCAS tRSH tCAH tASC tCAH tASC tCAH tRCD tRAD tCSH tASR tRAH tASC tCAS tCP

C A S VIH
VIL

Address

VIH VIL

Row

Column

Column

Column

W E VIL

VIH

tWCS

tWCH

tWCS

tWCH

tWCS

tWCH

OE

VIH VIL
tDS tDH Valid Data-in tDS tDH tDS tDH

D Q VIH
VIL

Valid Data-in

Valid Data-in

"H" or "L"

Fast Page Mode Read Modify Write Cycle

tRASP

RAS

VIH VIL
tCRP tRCD tRAD tASR tRAH tASC

tRWD

tCP tCWD tHPRWC tCAH tCWL tASC tCPWD tCPA tCAH tRWL

CAS

VIH VIL

Address VIL

VIH

Row

Column tAWD tRCS

Column tRCS tCWD

W E VIL

VIH
tRAC tAA tDS tWP tAA tOEH tOEA tCAC tOEZ
Valid Data-out

tAWD tDS tWP

OE

VIH VIL

tOEH tOEA tOED

tOED

tDH
Valid Data-in

tCAC

tOEZ
Valid Data-out

tDH
Valid Data-in

D Q VIH
VIL

tCLZ

tCLZ

"H" or "L"

15

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
RAS-only Refresh Cycle RAS
VIH VIL
tCRP tRAS tRC tRP

tRPC

CAS

VIH VIL
tASR tRAH

Address

VIH VIL
tCEZ

Row

DQ

VIH VIL

Open

Note:WE,OE="H" or "L"

"H" or "L"

CAS before RAS Refresh Cycle

tRP

tRC tRAS tRP

RAS

VIH VIL

tRPC tCP tCSR tCHR tRPC

CAS

VIH VIL
tWRP tWRH tWRP

W E VIH
VIL
tCEZ

DQ

VIH VIL

Open

Note:OE,Address="H" or "L"

"H" or "L"

16

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
Hidden Refresh Read Cycle
tRAS tRC tRP tRAS tRC tRP

RAS

VIH VIL
tCRP tRCD tRAD tASR tRAH tASC tCAH tRSH

tCHR

CAS

VIH VIL

Address

VIH VIL

Row tRCS

Column

tRAL

tRRH

W E VIL

VIH

tAA tROH

OE

VIH VIL
tRAC

tOEA tCAC tCLZ

tCEZ tOEZ tREZ

D Q VIH
VIL

Open

Valid Data-out "H" or "L"

Hidden Refresh Write Cycle

tRAS

tRC tRP tRAS

tRC tRP

RAS

VIH VIL
tCRP tRCD tRAD tASR tRAH tRAL tASC tCAH tRSH

tCHR

CAS

VIH VIL

Address

VIH VIL

Row

Column tRWL

W E VIL

VIH

tWCS

tWCH tWP

OE

VIH VIL
tDS tDH

D Q VIH
VIL

Valid Data-in "H" or "L"

17

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NT5117405J 4,194,304-word X 4-bit Dynamic RAM : Fast Page Mode with EDO
Test Mode Initiate Cycle
tRP tRC tRAS

R A S VIH
VIL
tRPC tCP tCSR tCHR

CAS

VIH VIL

tWTS

tWTH

W E VIH
VIL
tOFF

DQ

VIH VIL

Open

Note:OE,Address="H" or "L"

"H" or "L"

18

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