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Ashish Shukla

402 S Cooper, Apt # 211, Arlington, TX-76013 PERSONAL DETAILS OBJECTIVE

Cell: 817-932-0382 ashish.v.shukla@gmail.com

Seek a challenging position in VLSI Circuit/Logic Design/ Validation/Verification, apply my knowledge & skills effectively for the various projects undertaken by the Organization. Summary: Strong knowledge of Digital and Analog CMOS logic/circuit design principles and Layout rules, using Cadence Virtuoso. -- Strong Digital Design knowledge, working knowledge of VHDL/RTL and ASIC Design flow. -- Worked with IBM 90nm CMOS process for design of 22-29 GHz Impulse Generator for UWB applications (Transistor level design). Strong fundamentals of wireless communication principles and knowledge of Matlab. -- Recipient of Deans Masters Fellowship from The University of Texas at Arlington. -- Self motivated and hard-working, with an analytical bent of mind, good interpersonal skills and excellent team player. EDUCATION M.S. Electrical Engineering, University of Texas at Arlington, TX. - Expected Graduation Date: Dec 2009, GPA 3.82/4.0 B.E. Electronics Engineering, K. J. Somaiya College of Engineering (K.J.S.C.E), University of Mumbai, India -Graduation date: June 2006. G.P.A. 3.8/4.0 COURSES Analog CMOS IC Design, Digital VLSI Design, Radio Frequency Circuit Design, Data Communication, Information Theory and Coding, Wireless Communication systems, Mixed Signal IC Design, Radio Frequency IC Design, Advanced Electronics, Digital Sig. Processing, Computer Architecture, Microwave System Design. PROJECTS Design of 22-29 GHz Impulse Generator for UWB (Ultra Wideband) Vehicular RADAR Application in Deep Sub-micron technology (IBM 90nm CMOS process) using Cadence Virtuoso. 14-bit 100 Msps ADC using TSMC - 0.25um CMOS process. Xilinx FPGA Programming - VHDL Code for Digital Door Lock Communication between PC com-port and Micro-controller 89S52 using RS-232 (Interfacing using C and assembly language). PLL design using TSMC 0.25um CMOS process for GSM Application -- Rate versus power control comparison for various control schemes like Water-filling and channel inversion for CDMA2000 and IS-95 Simulation of MIMO system using Matlab for wireless communication. Comparator design for 0.1mV resolution using 0.5um CMOS process. Convolution, FIR & IIR Digital Filter Design, Sample Reconstruction in Matlab CMOS 4-bit Mux design using AMIC 0.5 um CMOS process. SKILL SET: Circuit Simulation tools like Cadence, ADS. PSPICE and HSpice. PERL scripting. Verification Tools: VHDL Model Sim, RTL Precision Synthesis. Analog and Digital signal analysis and simulation - using MATLAB. Worked with Schematic and Layout for various CMOS technologies including IBM 90nm CMOS using Cadence. Knowledge of Wireshark for basic network analysis. Operating Systems: Windows (98, XP, Vista), UNIX/Linux. High Level Languages: C, C++. WORK EXPERIENCE Worked with M/s Siemens India Ltd. (since July 2006) in the Industrial Solutions and Services (I&S) Division till 31 May 2007. Worked on the following Projects: Hardware Design for JSW Bar Mill, which is come up at Bellary, Karnataka. Worked with Siemens PLC (Programmable Logic Controller) software Step-7 and HMI (Human Machine Interface) software WinCC. Involved in automation related projects namely ITC Paper Mill, Tamil Nadu, India for Drive Commissioning. ACHIEVEMENTS: Recipient of Graduate Teaching Assistantship during Spring '08 and Spring, Summer and Fall '09 for Labs in Antenna Design and Circuit Design. Practical knowledge of both systems. Recipient of scholarship for academic excellence every year from M/s NOCIL India Ltd during Undergraduate studies and high school. Topped the Department of Electronics in the topic of Digital Communication in Final year of Under-grad studies. Extra-Curricular Activities: Participated and won prizes in inter-college robotics competition. Won 3rd prize in Technical Paper Presentation for paper on Nano-technology. Secured 98 percentile at all India EMATS test Organizer in college Cultural fest 'Symphony'. REFERENCES: AVAILABLE UPON REQUEST WILLING TO RELOCATE

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