Introduction to Lithography for Nanometer VLSI Manufacturing

Professor Kuen-Yu Tsai Nano-Detection and Fabrication Systems Group Dept. of Electrical Engineering, National Taiwan University 2006/12/21
Acknowledgement: Ken-Hsien Hsieh, Philip CW Ng, Yi-Sheng Su, and Meng-Fu You

Kuen-Yu Tsais Current Research Areas

List of current Projects:
1. 2. 3. 4. 5. 6. Microlithography Equipment R/D
Next Generation Lithography based on e-beams Resolution Enhancement Techniques (RET) Design for Manufacturing (DFM) Advanced Process Control (APC) Fault detection and classification (FDC) Drive/Sensing circuits Analog circuit design automation Virtual Touch Collaboration with Genomics Research Center Academia Sinica

Microlithography Software Microlithography Equipment/Process Control Analog Circuit Design by Control Techniques Sensor/Actuator Array MEMS and Signal Processing Bio/Cell Printing

2006/12/21

Prof. Kuen-Yu Tsai/NTUEE

Contents
Introduction to Microlithography Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC

Design for Manufacturability (DFM)

What is DFM? Circuit Model Related to Process-Induced Non-ideal Patterning

Next Generation Lithgraphy

EUV E-beam direct-write

Conclusions
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 3

Microlithography
A technology used in semiconductor manufacturing
Image a pattern from a photomask onto a silicon wafer coated with a light sensitive material called photoresist. Lithography at the sub-micrometer scale.

Source: Micronic http://www.micronic.se 2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 4

Optical Imaging System

Source: DongbuAnam Semiconductor [1]

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Moores Law
-Number of transistors on a chip doubles every 2 years

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Potential Solutions for Lithography, 2006

NTU NGL Team current research 65
Source: ITRS Lithography 2006

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SOURCE: Scott Hector, SEMATECH

Resolution Improvement by Immersion

HPMIN , DRY = = 1 RESIST 4 sin RESIST
HPMIN ,WET = = 1 RESIST 4 sin RESIST

1 AIR nRESIST 4 sin nRESIST

AIR nRESIST 1 4 nLIQUID sin nRESIST

1 AIR = 4 sin
Lens

1 AIR = nLIQUID 4 sin

Lens Liquid

Photoresist Silicon wafer

Photoresist Silicon wafer

2006/12/21

Prof. Kuen-Yu Tsai/NTUEE

nwater = 1.44

Contents
Introduction to Microlithography Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC

Design for Manufacturability (DFM)

What is DFM? Circuit Model Related to Process-Induced Non-ideal Patterning

Next Generation Lithgraphy

EUV E-beam direct-write

Conclusions
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 9

Resolution Enhancement Technology (RET)

Target No RET With RET

At 90 nm technology, there is no yield without RET.

Source: Mentor Graphics WCR TSMN Boston Tech Symposium Apr. 2005.

RET uses pre-compensation of pattern in order to try to mitigate the effects of the lithographic process. Several available RET techniques:
Phase-shifted mask PSM Optical proximity correction OPC
2006/12/21

Off-axis illumination OAI

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Prof. Kuen-Yu Tsai/NTUEE

The Contributors to Non-Rectangular Wafer Pattern

Line-end shortening Corner-rounding Line-end roughness

Source: A. Balasinski, et al., Impact of sub wavelength CD tolerance on device performance, SPIE, 2002.

Source: A. Balasinski, A methodology to analyze circuit impact of processs related MOSFET geometry, SPIE, 2004.

Lithography process variations: Lens aberration, misalignment, defocus, and overexposure Sub-wavelength non-ideal optical effects due to Diffraction and polarization effect Those effects or variations would result in wafer pattern distortion: Line-end shortening, corner-rounding, and line-edge roughness
Prof. Kuen-Yu Tsai/NTUEE 11

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Optical Proximity Correction (OPC)

Optical proximity correction (OPC) is a photolithography enhancement techniques commonly used to compensate the mask pattern for image errors due to diffraction or process effects[2].

Typical OPC type

Source: Synopsys [6] Source: DongbuAnam Semiconductor [1]

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NTUEE Model-Based OPC Engine

Before OPC: Mask pattern sdasdasdasdasd

No OPC: Contours of desired pattern and wafer pattern

Segment length= 72 nm Iteration number: 10

After NTUEE OPC: Corrected mask 2006/12/21pattern

Prof. Kuen-Yu Tsai/NTUEE

With NTUEE OPC: Contours of 13 desired pattern and wafer pattern

Contents
Introduction to Microlithography Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC

Design for Manufacturability (DFM)

What is DFM? Circuit Model Related to Process-Induced Non-ideal Patterning

Next Generation Lithgraphy

EUV E-beam direct-write

Conclusions
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 14

Design for Manufacturability (DFM)

A design methodology includes a set of techniques to modify the design of ICs in order to improve:
Functional yield, parametric yield, reliability

Techniques includes:
Substituting higher yield cells where permitted by timing, power, and routability. Changing the spacing and width of the interconnect wires, where possible Optimizing the amount of redundancy in internal memories. Substituting fault tolerant (redundant) vias in a design where possible.
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 15

Historical Mode of Operation for Circuit Design and Fabrication

Layout

Physical design
Circuit architecture Device models Design rules

Test data
BIM

PSM

Packaged IC

SOURCE: Scott Hector, SEMATECH

Masks

Design

Organizational, corporate cultural and geographical barriers

2006/12/21 Prof. Kuen-Yu Tsai/NTUEE Wafer fab 16

New Mode of Operation With Design for Manufacturing (DFM) Practices

DFM-aware physical design
Statistical optimization Layout with critical paths DFM score DFM guidelines

SOURCE: Scott Hector, SEMATECH

Masks optimized based on design intent

Design rules

Circuit architecture

40 30 20 10 0

Frequency

Wafer fab

Process variation information Design

IP maturity database Test data

BIM, ACI CD 78 PSM, ACI CD 8 BIM, ACI CD 74

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Device models with process Prof. Kuen-Yu Tsai/NTUEE variation information

Packaged IC 17

Circuit Model Related to Process-Induced Nonideal Patterning

TCAD simulation SPICE modeling

Circuit layout

Lithography process Circuit device Variation-aware

Variation-aware model

Performance

Process modeling

Device modeling

A variation-aware model (e.g. SPICE BSIM4) could be built to predict circuit performance variability based on circuit design and characterized source of manufacturing variation including:
Poor ILS (image log-slope) Defocus Misalignment
2006/12/21

Aberration in the lens Overexposure

Prof. Kuen-Yu Tsai/NTUEE 18

Contents
Introduction to Microlithography Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC

Design for Manufacturability (DFM)

What is DFM? Circuit Model Related to Process-Induced Non-ideal Patterning

Next Generation Lithgraphy

EUV E-beam direct-write

Conclusions
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 19

Potential Solutions for Lithography, 2006

NTU NGL Team current research 65
Source: ITRS Lithography 2006

45

32

22

16

2006/12/21

Prof. Kuen-Yu Tsai/NTUEE

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Some of the NGL Activities at NTU

Prof.\Technology Yung-Yaw Chen

ML2
Yes

EUV

Immersion Imprint

Near-field

Tien-Tung Chung Yes Jia-Han Li Cheewee Liu Kuen-Yu Tsai Fu-Cheng Wang Sen-Yeu Yang Jia-Yush Yen Lon Wang Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

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EUV Lithography
Utilize 13.5-nm wavelength light (extreme ultra-violet). Reflective optics (mirrors with multi-layer coating). One of the most promising technology for 32-nm-and-below mass production. Disadvantages:
High energy loss in reflective optical system due to the nature of EUV light. Extremely high cost in light source and optical components maintenance.
SOURCE: Carl Zeiss

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Massively Parallel Mask-less Lithography (MPML2)

E-beam lithography is capable of sub-20 nm patterning. E-beam direct write technique eliminate the cost of mask fabrication (~2M USD.) and correction (~1 week). Direct write technique is capable of patterning more complex patterns (e.g. Fresnel zone plate). Challenges:
Integrate as many as possible beams into the system. Design an effective writing strategy to maximize system throughput. Electron-resist interaction (proximity effect) correction. Design a data transfer system to process huge data at one time.
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Multiple E-beam Maskless Lithography Research

Several countries have been seriously involved with research in e-beam direct write systems. The main motivation of this research is to develop key technologies for MEMSbased maskless e-beam exposure systems

Not for public disclosure

Schematic of MAPPER system [7] Schematic of MCC, Advantest [8]

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2006/12/21
Schematics of Canons System [9]

Schematic of REBL, KLA [10]

Prof. Kuen-Yu Tsai/NTUEE

MPML2, NTU

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Multiple E-beam ML2 Electron Source

MEMS-based electron emitters: Provide the electron beam current with enough brightness during wafer exposure. Microchannel amplifier array: Provide stable, high-current operation and long-term reliability.

Arradiance Inc.[11]
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 25

Multiple E-beam ML2 Electron Optics

2-D and 3-D electromagnetic lens simulation environment is built up. Control theories can be applied to optimize lens structures and minimize the beam size.

Electrostatic field of einzel lens and electron trajectory are simulated under MATLAB and COMSOL Multiphysics.
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 26

Multiple E-beam Maskless Lithography Research

Electron scattering is the main limitation of EBL resolution. Two types of scattering: Forward scattering: Electrons scatter by resist atoms. Backscattering: Electrons bounce back from substrate.

desired pattern
forward scattering

backscattering
2006/12/21

Trajectories of 200 electrons with energy of 20keV is simulated by MONTE.

Prof. Kuen-Yu Tsai/NTUEE

developed pattern
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Contents
Introduction to Microlithography Resolution Enhancement Technology (RET)
Distortion; NTUEE OPC

Design for Manufacturability (DFM)

What is DFM? Circuit Model Related to Process-Induced Non-ideal Patterning

Next Generation Lithgraphy

EUV E-beam direct-write

Conclusions
2006/12/21 Prof. Kuen-Yu Tsai/NTUEE 28

Conclusions and Suggestions for Students conducting Microlithography-centered Research

Lithography technology is
Very important to keep Moores law valid Highly interdisciplinary Very interesting!!

Be open minded Start from basics, even high school stuff

Really understand simple things Built complex concepts/systems based on simple things

System Engineering concepts can help integration

System theories, control, signal processing, optimization can facilitate Interdisciplinary Research

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Questions and Answers

(5-10min) Any questions about:
Lithography in general MS at NTU PhD/Study abroad at Stanford/USA Work at Intel/USA What my classmates are doing Other?

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References
Keeho Kim, Optical Lithography, DongbuAnam Semiconductor, Nano Team/ R&D. Wikipedia, OPC article, available at http://en.wikipedia.org/wiki/Optical_proximity_correction 3. Rajesh Menon, D. J. D. Carter, Dario Gil, and Henry I. Smith,Zone-Plate-Array Lithography (ZPAL): Simulations for System Design, MIT, NanoStructures Laboratory (NSL) 4. Rajesh Menon, D. J. D. Carter, Dario Gil, and Henry I. Smith, Zone-Plate-Array Lithography (ZPAL): Optical Maskless Lithography for Cost-Effective Patterning, Proc. of SPIE, Emerging Lithographic Technologies IX, Vol. 5751,May 2005 5. ITRS Lithography Roadmap, available at http://public.itrs.net/ 6. Synopsys OPC tool, available at http://www.synopsys.com/products/ntimrg/opc_ds.html 7. SEMATECH Maskless Workshop, Jan. 2005. available at http://www.sematech.org/resources/litho/meetings/emerging/20050117/ 8. A. Yamada, ADVANTEST Technology Developments, Maskless Workshop, January 17-19 2005 9. Phillip Ware, Removing The Mask, oe magazine pp. 26-27, march 2002. 10. Marian Mankos, Harald F. Hess, David L. Adler, and Kirk J. Bertsche, Maskless reflection electron beam projection lithography, US Patent Issued on March 22, 2005 11. 2006/12/21 Arradiance, Inc., available atProf. Kuen-Yu Tsai/NTUEE http://arradiance.com/index.html 31 1. 2.