Vous êtes sur la page 1sur 9

Hardware of the PIC16F84A In order to use the PIC, you must understood how it functions.

The PIC16F84A, uses the RISC(Reduced Instruction Set Computer). With this, the total number of instructions is 35 . Pin Diagram

million. For this reason it is not recommended for temporary data storage. It is used to store data which will not change frequently. Data can be safely stored for 40 years. SFR Registers16 different SFR (Special Function Registers) can be specified by the bank switching technique. The figure below shows the RAM File Registers. The memory capacity is only 160 bytes. The contents of the registers with the left pointing arrow are the same on both banks. The other registers of the SFR are accessible through bank switching, and the gray colored registers are not used (Flash Program Memory)

OSC1/CLKIN : Oscillator crystal input. External clock source input. OSC2/CLKOUT : Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. MCLR(inv) : Master clear(reset)input. Programming voltage input. This pin is an active low reset to the device. RA0 - RA3 : Bi-directional I/O port. RA4/T0CKI : Bi-directional I/O port. Clock input to the TMR0 timer/counter. RB0/INT : Bi-directional I/O port. External interrupt pin. RB1 - RB7 : Bi-directional I/O port. VSS : Ground VDD : Positive supply(+2.0V to +5.5V) .Flash Program Memory Flash memory is used to store the program. One word is 14 bits long and 1024 words (1k words ) can be stored. Even if power is switched off the contents of the flash memory will not be lost. Flash memory can be written to using the writer, but the number of times it be rewritten is limited to 1000 times.

(SFR Registers)

Reset Vector ( 0000h ) When a reset is executed, either by turning power on, by the WDT (Watchdog Timer) or any other factor, the program will start from this address. Peripheral Interrupt Vector ( 0004h ) When there is a time-out interruption from the timer (TMR0) or an outside interrupt, the program will start from this address.

Configuration word ( 2007h ) The basic operation of the PIC is specified at this memory location. The enable bits of the Power-up timer, and the Watch-dog timer as well as the oscillator selection bits are set here. This area is behind the usual program area and can not be accessed by the program. These parameters must be specified using the burner when burning the program into flash memory. RAM(Random Access Memory) File Registers Bank switching is used to access this memory. Each bank has a memory capacity of 80 bytes (00h-4Fh). The PIC16F84A has two banks. This memory is divided into two sections. The first 12 bytes (00h-0Bh) of each bank are called SFR (Special Function Registers) and are used to record the operating states of the PIC, the input/output (I/O) port conditions and other conditions. There are 16 different registers in the SFR (11 in bank 0 and 5 in bank1). The content of each register is managed by the PIC. Although there are a total of 24 file registers, several of them are in both banks. The remaining 68 bytes (0Ch-4Fh), from byte 13 upward, are called GPR (General Purpose Registers) and can be used to temporally store results and conditions while the program is running. The contents of the GPR are the same in both banks, so even with bank switching the total capacity is only 68 bytes. The contents of the GPR are lost when the power is switched off. There is no limit to the number of times data can be rewritten. EEPROM(Electrically Erasable Programmable Read Only Memory) This is nonvolatile memory, the contents is not lost when power is turned off. The memory contents can be rewritten by the program. The total capacity is 64 bytes, and the number of times it can be rewritten to is limited to about one

Each SFR has the following function. INDF : Data memory contents by indirect addressing TMR0 : Timer counter PCL : Low order 8 bits of program counter STATUS : Flag of calculation result FSR : Indirect data memory address pointer PORTA : PORTA DATA I/O PORTB : PORTB DATA I/O EEDATA : Dtata for EEPROM EEADR : Address for EEPROM PCLATH : Write buffer for upper 5 bits of the program counter INTCON : Interruption control OPTIN_REG : Mode set TRISA : Mode set for PORTA TRISB : Mode set for PORTB EECON1 : Control Register for EEPROM EECON2 : Write protection Register for EEPROM Program Counter This counter contains the address of the next instruction ( fetch address) to be read from the program memory (flash memory). It is a 13 bit counter. Generally the count increments each time an instruction is executed, and the

location of the following instruction is shown in the PC. But when a jump is executed the contents of this counter is rewritten to that of the jump address. 8 Level Stack The stack stores the program return address when a jump is executed. For example if the same instructions are to be executed more than once, a subroutine is used. A RETURN instruction signifies the end of the subroutine and the program continues were it left off. A CALL instruction tells the program to jump to a subroutine. When the CALL instruction is encountered, the return address (the address of the instruction immediately after the CALL) is stored at the top of the stack. This operation is sometimes called a PUSH. When the subroutine processing is finished and the RETURN instruction is executed, the address at the top of the stack is put in the PC and the program continues normal execution. This operation is sometimes called a POP. This way multiple subroutines can be called and the processing will return to the part of the program which called the subroutine. Since there are eight stack registers, eight subroutine calls can be made sequentially. After the eighth, a call will roll the contents of the eighth (and last register) back to the top of the stack. When a return is executed, the PC will send the program to the wrong address, and the program will not work properly. For this reason only eight sequential subroutines calls can be made. A return from a subroutine call must be done by the RETURN instruction. Never use the JUMP instruction to return from a subroutine. Instruction Register The instruction at the address specified by the PC is read to this register. This operation is called a FETCH. Instruction Decode & Control The instruction in the Instruction Register is analyzed here, and (according to its contents) the operation is performed. Multiplexer and Arithmetic Logic Unit The calculations are performed by the Multiplexer and Arithmetic Logic Unit (ALU).Without these two it would not be a computer. W Register This is the working register. It is used to temporarily store the contents of the ALU. It is indispensable for calculation operations. The contents of this register can be transferred to the various registers to be utilized by the program. It is also used to control the I/O ports. STATUS Register This Register stores the result of the ALU (Zero, positive or negative), a time-out condition, register bank select etc. FSR Register FSR (File Select Register) is used to specify the address of the RAM file register when using the indirect addressing method. In the direct address method the register address is specified by the program instructions. In this case a 7 bit address, from 0 to 127, can be specified. This range is for one bank. To change the bank, the RP0 bit of the status register must also be specified. Since the FSR is 8 bits, it is possible to specify the address and bank at the same time, saving instruction cycles. In the PIC16F84A memory locations 80 (50h) to 127 (7Fh) are not installed. When using the FSR it is convenient to make the file register data area continuous. Incrementing the FSR simplifies processing during read and write operations. Address Multiplexer Distinguishes between direct and indirect addressing EEDATA This register is used when reading from, or writing data to the EEPROM. EEADR This register specifies the EEPROM address. Since it is composed of eight bits addresses from 0 to 255 can be specified. The PIC16F84A has only 64 bytes of memory installed. The address of EEPROM is started from 2100h. When writing data during program execution it is necessary to sequentially write 55h then AAh to the EECON2 register. Timer The PIC16F84A has only one timer (TMR0, an 8 bit timer). It times out when the count reaches 256 and the TOIF bit of the INCON register of the SFR becomes "1". With a timed out condition it is possible to make an interrupt occur. The interrupt will stop the processing which was in progress at that time. To make the interrupt occur the GIF and the TOIE bits of the INTCON register of the SFR must be set (1) I/O Ports There are 13 I/O pins, with individual direction controls. The mode (input or output) of each pin can be set from within the program. The 13 pins are divided into two groups. The A Port has five pins and the B Port has eight. There is a limitation on control timing, but each of the 13 pins can be individually controlled. Timing Generation This circuit generates the clock pulses which determine the speed of operation. Oscillator operation is determined by external capacitors and a crystal (or ceramic) oscillator. If high stability is desired a crystal or ceramic resonator is used. Generally the circuitry is simpler with the resonator, which incorporates the ceramic and capacitors in one module. An external clock can also be used. The PIC16F84A executes one instruction (one cycle) every four clock pulses, using pipeline architecture. But when a JUMP is executed two cycles are necessary (8 clock pulses). With a 20MHz clock the execution time of an instruction is 200ns. (The pulse period of 20MHz is 50ns (1 / 20MHz = 50ns), so 50ns x 4 cycles = 200ns). 5,000,000 instructions can be executed in one second. (2,000,000 / 4 = 5,000,000)

Initialization circuits The PIC16F84A has various initialization circuits. POW ON Timer : When power is turned on this timer inhibits operation until the voltage is stable. OSC StartTimer : When power is turned on this timer inhibits operation until the clock is stable. POW ON Reset : When power is turned on this timer initializes the inner circuitry of the PIC. Watchdog Timer : This timer watches over the normal operation of the PIC software. It must be regularly cleared by software. When it times out the PIC returns to the point in the program immediately after power on. This timer is used to recover program operation when the software has a defect (or bug). Even if the program is reinitialized the bug is still in the program. PIC16F84A Block Diagram

8 Level Stack

I. SPECIFICATION OF REGISTERS SFR(Special Function Registers) The first 12 bytes at the head of the RAM file register are used for the SFR. This group of registers is very important to the operation of the PIC. Below I

will explain the operation of these registers, which are necessary to the management of the PIC. STATUS Register ( RAM Memory Address 03h,83h )

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

1:16 1:32 1:64 1:128 1:256

1:8 1:16 1:32 1:64 1:128

R =Readable bit ;W =Writable bit ;-n =Value at POR reset; Bit6,7 =Unimplemented bit Bit7: IRP Register Bank Select bit(used for indirect addressing) The IRP bit is not used by the PIC16F84A. IRP should be maintained clear. Bit6,5: RP1,RP0 Register Bank Select bit(used for direct addressing) Only bit RP0 is used by the PIC16F84A. '0' means Bank0, '1' means Bank1. RP1 should be maintained clear. Bit4: TO(inv) Time-out bit 1 = After power-on,CLRWDT instruction,or SLEEP instruction 0 = Watchdog time-out occurred Bit3: PD(inv) Power-down bit 1 = After power-on or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Bit2: Z Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero Bit1: DC Digit carry/borrow(invert) bit (for ADDWF and ADDLW) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Bit0: C Carry/borrow(invert) bit (for ADDWF and ADDLW) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred OPTION_REG Register ( RAM Memory Address 81h )

INTCON Register ( RAM Memory Address 0Bh, 8Bh )

R =Readable bit; W =Writable bit;-n =Value at POR reset Bit7: RBPU(inv) PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) Bit6: INTEDG Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin Bit5: T0CS TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) Bit4: TOSE TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin Bit3: PSA Prescaler Assignment bit 1 = Prescaler assigned to WDT 0 = Prescaler assigned to TMR0 Bit2-0: PS2-0Prescaler Rate Select bits PS2 PS1 PS0 TMR0 WDT 0 0 0 0 0 1 0 1 0 1:2 1:4 1:8 1:1 1:2 1:4

R =Readable bit; W =Writable bit;-n =Value at POR reset Bit7: GIE Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Bit6: EEIE EEPROM Write Complete Interrupt Enable bit 1 = Enables the EEPROM write complete interrupt 0 = Disables the EEPROM write complete interrupt Bit5: T0IE TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt Bit4: INTE RB0/INT Interrupt Enable bit 1= Enables the RB0/INT interrupt = Disables the RB0/INT interrupt Bit3: RBIE RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt Bit2: T0IF TMR0 Overflow Interrupt Flag bit 1 = TMR0 has overflow (must be cleared in software) 0 = TMR0 did not overflow Bit1: INTF RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred (must be cleared in software) 0 = The RB0/INT interrupt did not occurred Bit0: RBIF RB Port Change Interrupt Flag bit 1= When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0= None of the RB7:RB4 pins have changed state

EECON1 Register ( RAM Memory Address 88h )

R =Readable bit W =Writable bit S =Settable bit U =Unimplemented bit -n =Value at POR reset Bit7-5: UnimplementedRead as "0" Bit4: EEIF EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started Bit3: WRERR EEPROM Error Flag bit 1 = A write operation is prematurely terminated 0 = The write operation completed Bit2: WREN EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM Bit1: WR EEPROM Write Control bit 1= Initiates a write cycle (The bit is cleared by hardware once write is complete. the WR bit can only be set(not cleared) in software.) 0= Write cycle to the data EEPROM is complete

Bit0: RD EEPROM Read Control bit 1= Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set(not Cleared) in software) 0= Does not initiate an EEPROM read INDF Register ( RAM Memory Address 00h ) This register is used when reading from, or writing to, memory by the indirect addressing method. When reading a memory location by the direct address method, the memory address is directly designated in the instruction code. movwf 30h is an example of the direct address method In this case, memory address (30h) is specified in the instruction code and becomes 00 0000 1011 0000 in machine code. The red part is the instruction code for movwf, the blue part (one bit) specifies a write to the file register, and the green part is the memory address. In this case, to read or write to a continuous block of memory, an instruction must be written for every memory location. When reading and writing a continuous block of memory, the indirect addressing method is convenient. When reading and writing a memory location by the indirect addressing method, the memory address is set by the FSR register. The memory contents of the register which was specified by the FSR register is read and written through the INDF register. That is, the INDF register is a relay register for the actual memory.By incrementing the contents of FSR the contents of the following memory location can be accessed through the INDF. The memory address can be changed by the calculation even if it doesn't make each instruction. You don't need to set up each memory address by instruction.

1 0 0

0 1 0

High Speed Crystal/Resonator 4MHz to 20MHz Crystal/Resonator Low Power Crystal Less than 4MHz Less than 200KHz

EECON2 Register ( RAM Memory Address 89h )

Writing 55h and then AAh in sequence to the EECON2 enables a data write to the EEPROM register. Data written to the EEPROM doesn't disappear when power is switched off. Therefore, if the wrong data is written, when the power comes on again, it doesn't return to the original. So, this sequence is used to ensure that when the program is running it does not accidentally write the wrong data to the EEPROM.An exsample of the correct writing sequence to the EEPROM is shown below. The red part is the protection sequence.
bsf status,rp0 ;Change to Bank1 bcf intcon,gie ;Disables all interrupts bsf eecon1,wren ;Allows write cycles movlw h'55' ;Set 55h data movwf eecon2 ;Write 55h to EECON2 movlw h'aa' ;Set AAh data movwf eecon2 ;write AAh to EECON2 bsf eecon1,wr ;Initiates a write cycle bsf intcon,gie ;Enables all un-masked interrupts

II. SPECIFICATION OF THE INPUT-OUTPUT PORTS The input/output ports are used for the PIC to do the operation which cooperates with the circuits outside. The PIC16F84A has the 13 input/output pins. Those are classified into five sets and eight sets and five sets are called A port and eight sets are called B port. The A port corresponds to the PORTA register and the B port corresponds to the PORTB register. Each register is composed of 8 bits and the input/output pin corresponds every bit. As for PORTA, 5 bits from bit 0 to bit 4 are used and 3 bits from bit 5 to bit 7 aren't used.As for PORTB, all of the 8 bits correspond to the input/output pins respectively. The mode (the input or the output) of each pin is specified by the TRISA register (for PORTA) and the TRISB register (for PORTB). The setting "0" of TRISx means for the output and "1" means for the input. These mode setting can be set every pin. The control of the A port and the B port is done with the PORTA register and the PORTB register. That is, as for the A port, 5 pins are controlled at the same time and as for the B port, 8 pins are controlled at the same time. The control of the output operation is done by setting the contents to want to output to the W register (8 bits) and writing it in the PORTA register or the PORTB register by the MOVWF instruction. Data setting is done to the bit(s) which was set for the input. However, the actual output is done only by the pin which was set for the output and doesn't have an influence on the pin which was set for the input. The control of the input operation is done by taking in the contents of PORTA or the PORTB register to the W register by the MOVF instruction. In this case, the data of the pin(s) which was set for the output becomes data by the writing operation immediately before reading. This is because the output data latch register keeps an output state. It is necessary to consider to use only the data of the input pins when making software. The A port and the B port rather differently in the circuit and the function. Also, in the A port, the RA4 pin can be used as the clock input of the TMR0. In case of the B port, from RB4 to RB7 have the function to watch over the change of the input signal. Moreover, RB0 has an external interrupt function. These functions confuse you. These functions are a convenient function but are not an indispensable function. Examine when those functions become necessary. Below, I will explain the outline of each port circuit.

Configuration Word ( Program Memory Address 2007h )

R =Readable bit P =Programmable bit -n =Value at POR reset u =Unchanged Bit13-4: CP Code Protection bit 1 = Code protection off 0 = All memory is code protected Code protection is used to prevent the PIC memory contents from being read. It is set to OFF if reading protection is not needed. Bit3: PWRTE(inv) Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled The power up timer maintains the reset condition for about 72 ms after the turning power on. Generally, it is set to enable. Bit2: WDTE Watchdog Timer(WDT) Enable bit 1 = WDT enabled 0 = WDT disabled Bit1-0: FOSC1 FOSC0Oscillator Selection bits FOSC1 FOSC0 1 1 Oscillator mode Resistor/Capacitor Freq Less than 1MHz

Specification of A port ( RA0-RA3 ) The figure on the left shows the circuit block of RA0, RA1, RA2 and RA3 at the A port. The data output circuit is composed of the output data latch register and CMOS drive circuit. The circuit of the CMOS has the function to block an output data to the pin of the input setting as well as the driving function in the output.

The operation of the output circuit The CMOS(Complementary-Metal Oxide Semiconductor) is the circuit which combined the N-channel MOSFET(N-FET) and the P-channel MOSFET(P-FET).

the L level again from the H level. It is same in case of the TRIS latch register, too. First, the contents of the TRISA register are set on the data bus. After that, The control signal of the TRIS latch register (WR TRIS) is changed to the L level from the H level and it makes memorize the contents of the bus to the TRIS latch register. The inverter with the gate is used for the reading of the contents of the TRIS latch register. The contents of the TRIS latch register are set on the data bus when RD TRIS becomes "1".

o The operation of the input/output mode setting circuit The mode of each pin is set with the TRISA register. The set value of the TRISA register is recorded to the TRIS latch register. The inverted output ( ) of the output data latch register and the output (Q) of the TRIS latch register are inputted to P-FET through the OR circuit. The inverted output ( ) of the output data latch register and the inverted output ( ) of the TRIS latch register are inputted to N-FET through the AND circuit. o The operation at the time of the output mode To set the output mode, it makes the bit of the TRISA register which corresponds to the pin "0". Because the output (Q) of the TRIS register is L level, the condition of the inverted output ( ) of the output data latch register is applied just as it is to P-FET. Also, the inverted output ( ) of the TRIS register is H level and the condition of the inverted output ( ) of the output data latch register is applied just as it is to N-FET. When the data to want to output is H level, as for the inverted output ( ) of the output data latch register becomes L level, the P-FET becomes ON, the N-FET become OFF and the output becomes H level. When the data to want to output is L level, it becomes an opposite condition and the output becomes L level.

Taking-in in the condition of the input pin is done by following operation. The gate between the input data latch register and the data bus is opened when the data reading signal(RD PORT) changes into the H level from the L level. Simultaneously with it, the control terminal of the input data latch register(EN) is changed into the L level from the H level, the condition of the port is memorized to the input data latch register and is set on the data bus through the gate. The input data latch register is used because it makes not influence the data of the bus even if the data on the pin changes while data reading.

o The operation at the time of the input mode To set the input mode, it makes the bit of the TRISA register which corresponds to the pin "1". The output (Q) of the TRIS register is H level and the output of the OR circuit is always H level. Therefore, P-FET becomes OFF condition. Also, the inverted output ( ) of the TRIS register is L level and the output of the AND circuit is always L level. Therefore, N-FET becomes OFF condition. So, in this condition, P-FET and N-FET are in the OFF condition. The pin becomes the condition which was separated from the output driver and is operative as the input mode.

Specification of A port ( RA4 ) In the A port, RA4 is the port which has a special function. The figure below shows the circuit block of RA4. The difference with the other port is the FET for the output drive be only N-FET and the Schmitt trigger type is used as the input buffer. This pin can be used for the input of the clock timing pulse of TMR0 in case of the input mode. Because it is using the Schmitt-type input buffer, it can make the judgement of the H level or the L level, when the edge(rising or falling) of the external signal isn't clear. Because there is not P-FET of the output driver, the pull-up(It connects with VDD through the resistor) must put with the circuit outside to input H level. Because this circuit becomes an open drain type in the output mode, it is sometimes convenient for the design of the external circuit.

o The operation of the input circuit The input circuit is always connected with the I/O pin. So, even if it is set to the output mode, the input circuit is working. The input signal is taken into the input data latch register through the TTL buffer o The output and the input timing The transfer of the input data to the output data latch register, the setting data to the TRIS latch register and the output data of the input data latch register is done through the data bus. The data bus has eight lines and the transfer of the data with the pins is done in parallel. Because the data bus is common use, the transfer of the information is controlled by the timing pulse of the control signal to each register. When wanting to output the contents of the PORTA register, first, the data of the PORTA register is set to the data bus. Next, the control signal of the output data latch register(WR PORT) is changed to the L level from the H level and the data of the bus is recorded to the data latch register. The contents of the output data latch register become the condition of the pin just as it is. After that, even if the data on the bus changes, the contents of the output latch register don't change until the control signal changes into

Specification of B port ( RB0-RB3 ) The output circuit composition of the B port is different from the A port. It doesn't use the FET for the output circuit and it is changing the mode with the gate circuit. The characteristic of the B port is to be equipped with the pull up function at the time of the input mode. The pull-up is to hang the input port on the side of the VDD. In this way, when the input is opening, the input port keeps H level. At usual circuit, the resistor is used for the pull-up but the FET is used at this circuit. The FET is not in the true ON condition and is made the weak pull-up condition. When this pull-up function influences circuit operation, it is possible to make not use. RB0 can be used as the input pin of the external interrupt, and is connected with the inner circuit through the Schmitt-type buffer. When the TRIS is "0", it is the output mode. Because there is an inverter in the control input of the output gate, the gate opens when the output of the TRIS latch register is "0" (the L level). The input of the NAND gate for the pull-up is the L level and the output is H level. Therefore, P-FET for the pull-

up becomes OFF condition and pull-up isn't done. When the TRIS is "1", it is the input mode. The output gate is closed and output signal is separated from the I/O pin. As the side of the TRIS latch of the NAND gate for the pull-up is H level, pull-up or not is decided by the setting of the RBUP. RBPU is the bit 7 of the OPTION-REG register and is "Pull-up" in "0" and "Non pull-up" in "1". In case of "0", the gate of P-FET becomes L level and P-FET becomes ON condition. In case of "1", it is opposite. In RBPU, a whole B port pull up condition is set. It isn't possible to do setting every each pin.

Specification of B port ( RB4-RB7 ) RB7 from RB4 has the function to detect the change of the input signal as well as the data input function. This function can be used the interruption processing by the key depression and so on. The change detection is done at the same time in four pins. Because it is, the change only of the specific pin can not be detected. This function works in case of the input mode in the pin. The OLD data latch register and the Exclusive OR(XOR) circuit are used for the change detection in addition to the input data latch register. The input and the output of XOR are as follows. It supposes that the input data changed until the following reading timing. When RD Port becomes H level from the L level, the input data is read to the input data latch register. At this time, the contents of the OLD data latch registe aren't changing yet. Therefore, a different condition is inputted to the two inputs of XOR and H level is output. This H level becomes the trigger of the interruption signal. When RD Port becomes L level from the H level, the input data is read to the OLD data latch registe, the output of both registers becomes the same and the output of XOR becomes L level. When the input data is changed before the signal of RD Port becomes L level from the H level, the input data is read to the OLD data latch registe. On this point, because this change isn't read to the input data latch register yet, the condition of the output of both registers is different, H level is output by XOR and the interruption occurs. The output of XOR continues to the timing of the following RD Port reading pulse. I don't find an influence over the operation that this continues interruption. The interruption may occur once again when the output of XOR is H level even if it processes a interruption softly and it clears RBIF bit. Or, there is possibility to be guarded with the circuit inside.


Specification of the timer (TMR0)

The figure above shows the timer (TMR0) and watchdog timer (WDT) block diagram. Each register under the figure affects the timer setting. The yellow bits are related. The Prescaler, which is at the center of the figure, can be used for either the TMR0 or WDT. The figure above shows the prescaler connected to TMR0. The PSA bit (bit 3) of the OPTION_REG determines to which of the two the prescaler is connected. The prescaler is a programmable counter whose count ratio is determined by OPTION_REG bits PS0, PS1, PS2 (bits 0, 1, &2). TMR0 is a binary 8 bit counter which can count up to 256. When the counter changes from 255(FFh) to 0(00h) an interrupt overflow occurs and T0IF bit (bit 2) of the INTCON register is set (becomes "1"). The hardware is designed such that when both the GIE (bit 7) and TOIE(bit 5) of the INTCON register are Hi ("1") the interruption occurs and the PC goes to address 004h, to start program operation from there. A 256 count of TMR0, is sometimes short. For example, when the internal clock is 20MHz, the counter input frequency is 5MHz.(FOSC/4). The period of this clock pulse is the 200ns (1 / 5Mhz = 0.2sec). So it takes TMR0 51.2sec (0.2sec x 256) to overflow. In order to extend this period the prescaler is used.The prescaler can be used to divide the input by 2, 4, 8, 16, 32, 64, 128, or 256. For example, when the prescaler is set to divide by 2, there is 1 output pulse for every 2 pulses which are input to the prescaler. If set to 256, there will be 1 output pulse for every 256 pulses inputted. So, the overflow time of TMR0 can be made longer by setting the value of the prescaler. In the previous example when the prescaler was set to 256, the overflow time becomes 51.2sec x 256 = 13,107.2sec (about 13 milliseconds).The input to timer (TMR0) can be an external clock or the internal clock. To use the external clock, the T0CS bit (bit 6) of the OPTION_REG register and bit 4 of the TRISA register must be set to "1". This will put RA4/T0CKI pin in input mode (TMR0 CLOCK IN). Also, the rising or falling edge transitions of the clock pulse can be selected by the T0SE bit (bit 5) of the OPTION_REG register. For rising edge clear it "0" and for falling edge set it to "1".At the input to the timer (TMR0) there is a clock synchronizing circuit. When using an external clock, the timing of the rising and falling edges of the clock will not be synchronized with the internal clock. This will upset interrupt timing. This circuit synchronizes the TMR0 input with the internal clock. Synchronization is achieved in a maximum of 2 cycles. The Watch Dog Timer's (WDT) oscillator is independent from the CPU clock. The WDT time-out is about 18 msec. Generally, to prevent a time out condition the WDT must be reset periodically via software using the CLRWDT instruction. If the Timer is not reset before it times out, the CPU will reset forcing it to the address location immediately after power on. The prescaler can be used to extend the time-out period.In this case, the count values are different from TMR0. The prescaler can be set to eight values 1, 2, 4, 8, 16, 32, 64, or 128. When set to 128, the time-out is the about 2 seconds (18msec x 128 = 2,304msec). The function of the watchdog timer (WDT) is to prevent incorrect operation of the software. (Run away: It executes instructions which are not part of the program. / Loop: It executes the same part repeatedly.) The WDT function isn't always necessary. If there is a mistake in the program you can usually recognize there is a malfunction by the way it operates ( it doesn't perform the

way you expect it to). If the WDT resets the PIC you may not be able to understand what caused the program to malfunction. It may be better not to use the watchdog timer. To stop the operation of the watchdog timer, reset the WDTE bit of the configuration word (2007h) of the program memory to "0". Basically I don't use the watchdog timer. In that case, the prescaler can be used for the TMR0. IV. Specification of ICSP The PIC16F84A program is written into flash memory. In order to program the flash memory the following specification is used. The following five pins are used for reading and writing the data. During Programming Pin Name Pin No. Pin Name RB6 RB7 MCLR VDD VSS 12 13 4 14 5 CLOCK DATA VTEST MODE VDD VSS Pin Type I I/O P P P Pin Description Clock input Data input/output Program Mode Select Power Supply Ground Command Mapping
Mapping Command Data The following nine commands to use in Program/Verify mode.

Load Configuration Load Data for Program Memory Read Data from Program Memory Increment Address Begin Programming Load Data for Data Memory Read Data from Data Memory Bulk Erase Program Memory Bulk Erase Data Memory

0, data( 14 ), 0 0, data( 14 ), 0 0, data( 14 ), 0 None None 0, data( 14 ), 0 0, data( 14 ), 0 None None

I = Input, O = Output, P = Power To activate the programming mode, high voltage( VHH = +13V ) must be applied to the MCLR input. Also, +5V is applied to VDD. Programming is done by the following procedure. First +5V must be applied to VDD. o Program/Verify Mode (1) RB6, RB7 and MCLR are made 0V (Low). (2) Raise MCLR pin from 0V(Low) to +13V(VHH). The PIC is now in Program/Verify mode. o Serial Program/Verify Operation Pin RB6 is used as a clock input pin, and the RB7 pin is used for entering command bits and for data input/output during serial operation. Writing or reading of data is done using the above two pins. When using the PIC in Program/Verify mode, the internal clock is not used. Data input/output is controlled by the RB6 clock input. When the PIC is mounted on an application PCB and the clock cannot be disabled, upon the application of power MCLR must be taken to VHH before the PIC begins operation (About 72 milliseconds). Otherwise, if the PIC begins operation the program counter will be incremented and the writing start address will be offset. When using a programmer this problem will not be encountered, since the internal clock generator is not used. Detail specification of Program/Verify mode o About serial method RB6 (Clock input) and RB7 (Data input/output) are used for reading and writing of data to or from the PIC. The data is transmitted or received serially. RB7 data consists of a 6-bit command and 16 data bits. The 16 data bits are made up of one start bit, 8 bits (one byte) of data memory and one stop bit. The remaining 6 bits are ignored. All commands and data words are transmitted least significant bit (LSB) first. Each command and data bit is latched on the falling edge of the RB6 clock pulse. During a read operation the LSB will be transferred to the RB7 pin on the rising edge of the second cycle of the RB6 clock pulse.

Program flow chart Below is a programming flow chart of program memory in Program/Verify mode.

Below is a programming flow chart of configuration data in Program/Verify mode.

Once in configuration memory(PC >= 2000h), the highest bit(14th bit) of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode. Microchip Inc. recommends that VDD be made minimum voltage and then maximum voltage after the above-mentioned processing and then read the data to verify it is correct.

Sound sensors Another name for a sound sensor is a microphone. The diagram shows a cermet microphone: 'Cermet' stands for 'ceramic' and 'metal'. A mixture of these materials is used in making the sound-sensitive part of the microphone. To make them work properly, cermet microphones need a voltage, usually around 1.5 V across them. A suitable circuit for use with a 9 V supply is: The 4.7 and the 1 resistors make a voltage divider which provides 1.6 V across the microphone. Sound waves generate small changes in voltage, usually in the range 10-20 mV. To isolate these small signals from the steady 1.6 V, a capacitor is used.

for adapting this circuit in different signal level, you can use a trimmer before C1 capacitor. Part list : R1= 10Kohm C1= 47uF 25V R2= 1.2Kohm C2= 2.2uF 25V R3= 220Kohm Q1-2= BC550C R4-5= 4.7Kohm D1= LED RED

This sensitive sound operated switch can be used with a dynamic microphone insert as above, or be used with an electret (ECM) microphone. If an ECM is used then R1 (shown dotted) will need to be included. A suitable value would be between 2.2k and 10kohms.The two BC109C transistors form an audio preamp, the gain of which is controlled by the 10k preset. The output is further amplified by a BC182B transistor. To prevent instability the preamp is decoupled with a 100u capacitor and 1k resistor. The audio voltage at the collector of the BC182B is rectified by the two 1N4148 diodes and 4.7u capacitor. This dc voltage will directly drive the BC212B transistor and operate the relay and LED. It should be noted that this circuit does not "latch". The relay and LED operate momentarily in response to audio peaks.The gain of the circuit and sensitivity is controlled by the 10k variable resistor on the emitter of the first (left hand side) transistor. A preset may be used if gain is fixed, a potentiometer should be used to trigger at different sound levels.The relay contacts close and then open (momentary action) in response to audio peaks, these can be used to switch other circuit. The diode across the relay is the usual back emf diode and a 1N4003 or 1N4004 will work well here, preventing damage to the transistor.

This is a simple audio peak indicator circuit diagram. This circuit drive a LED which will active ( LED D1 ON) each time the level of signal reach +4dB level. You can also set the level set point, under or above +4dB (1.25V rms).