Analog VLSI Design

1TT827
Course information Introduction The CMOS process NMOS and PMOS Passives

Lars Vestling
Fasta tillstndets elektronik a Institutionen fr teknikvetenskaper o Uppsala universitet

HT-2009 http://www.teknik.uu.se/fte/courses/acad/
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Syllabus
Analog VLSI Design, 4.5 credits Purpose The aim of this course is to give an introduction to how to design analogous IC-circuits using CAD-tools. Contents Analog MOS-technology. A project work where modern CAD-tools are used in designing an analog circuit on silicon. Other moments in the project work are for example designing of circuits, analog simulation in Spice, circuit layout on silicon, layout verication. Instructions Lectures and laboratory work. Examination Passed laboratory work and project report.
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Course information Introduction The CMOS process NMOS and PMOS Passives

Course literature P.E Allen and D.R Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002.

This course
Content
Computer laborations, preparation for project Project, Operational amplier
Course information Introduction The CMOS process NMOS and PMOS Passives

The Work
Preferably work in pairs, laborations can be reported in pairs. Project report should be written individually, but it is OK to work together.

Grading
Project report sets the grade. Grade 3 for doing the predened project. Higher grades are possible if additional investigations or improvements are done. N.B. this does not automatically give higher grades. It is not possible to x the report afterwards to get higher grades (only if the report is not passed). Reports handed in after the dead-line can not get higher grades than 3.

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What is Analog VLSI Design?

Course information Introduction The CMOS process NMOS and PMOS Passives

Analog IC design is the successful implementation of analog circuits and systems using integrated circuit technology. Unique Features of Analog IC Design
Geometry is an important part of the design Electrical Design Physical Design Test Design Usually implemented in a mixed analog-digital circuit Analog is 20% and digital 80% of the chip area Analog requires 80% of the design time Analog is designed at the circuit level Passes for success: 2-3 for analog, 1 for digital

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The Analog Design Flow

Course information Introduction The CMOS process NMOS and PMOS Passives

Physical Design

Fabrication
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Testing and Product Development

This Course

Electrical Design

Comparison of Analog and Digital Circuits

Analog Circuits
Signals are continuous in amplitude and time
Course information Introduction The CMOS process NMOS and PMOS Passives

Digital Circuits
Signal are discontinuous in amplitude and time Designed at the systems level Component have xed values Standard CAD tools have been extremely successful Timing models only Programmable by software Dynamic range unlimited

Designed at the circuit level Components must have a continuum of values Customized CAD tools are dicult to apply Requires precision modeling

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Performance optimized Dynamic range limited by power supplies and noise

Skills Required for Analog IC Design

In general, analog circuits are more complex than digital.
Course information Introduction The CMOS process NMOS and PMOS Passives

Requires an ability to use multiple concepts simultaneously. Must be able to make appropriate simplications and assumptions. Must have good knowledge of both modeling and technology. Be able to learn from failure. Be able to use simulation correctly.
(Usage of a simulator)x(Common sense)=Constant Simulators are only as good as the models and the knowledge of those models. all models are wrong, some are useful Simulators are only good if you already know the answers.

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Technology
Moores Law Minimum feature size (gate length) decreases by a factor of (1/ 2) every 3 years.
Course information Introduction The CMOS process NMOS and PMOS Passives

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Implications of Technology on IC Design

The good: Smaller geometries Smaller parasitics Higher transconductance Higher bandwidths The bad: Reduced voltages Smaller channel resistances (lower gain) More nonlinearity Deviation from square-law behavior The ugly: Increased substrate noise in mixed signal applications Threshold voltages are not scaling with power supply Reduced dynamic range Suitable models for analog design

Course information Introduction The CMOS process NMOS and PMOS Passives

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The CMOS process ow

Finished Add passivation implant resist mask fordrive-in) Metal nwell:removeremovedo oxide holesmetal Active area: maskimplanter exposed implant Createlayers:depositandetch nitride implantations layer Starting material:applymaskoxideandandlayer boron contacts: deposit(activation 2nd gate: growremoveetchsilicon nitriden+contacts mask p-type metal layer depositmaskthick removed grow eldphosphorussilicon deposit,poly developed depositsilicon polyetch maskand onis and wafer ion activate contact phosphorus implanted Implantthicksilicon maskand resist 1st photoresist phosphorus UV-light oxide contact applygate osilicon metal deposit 1st mask holes photoresist etch via oxide (FOX) mask annealingp+mask

Course information Introduction The CMOS process NMOS and PMOS Passives

ion implantation (phosphorus) UV-light

metal mask

photoresist mask

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photoresist silicon gate poly silicon nitride gate FOX n+ p+ p+ FOX n+ n+ p+ FOX n-well (p-well) n-well PMOS p-substrate NMOS

Passives in the CMOS process

Course information Introduction The CMOS process NMOS and PMOS Passives

Passive components are needed to construct complete circuits. By using existing layers and masks and possibly adding a few extra layers it is possible to construct passive components. Passivs are:
Resistors Capacitors Inductors

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Resistors
All material has a resistivity 2 parameters controls what material that are used to make resistors
Size and accuracy

Course information Introduction The CMOS process NMOS and PMOS Passives

A CMOS-process includes:
Metals (conductor) Insulators (dielectric) Silicon (semiconductor)

Typical resistivities
metal: 0.1 / n/p-plus contacts and polysilicon: 10-100 / n-well: 1000 / low doped poly silicon: 10 k/ (more well dened than n-well, i.e. higher accuracy)

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Resistors, manufacturing
Poly and etch poly Maskresistor pattern metal Deposit silicon oxide silicon layer wafer Starting polygrow eld oxide (FOX) and silicon material: p-type silicon contact Active area: nished holes

Course information Introduction The CMOS process NMOS and PMOS Passives

poly silicon FOX

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p-substrate

Resistors, layout
Mask: POLY METAL1 CONTACT

Course information Introduction The CMOS process NMOS and PMOS Passives

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Capacitors

Course information Introduction The CMOS process NMOS and PMOS Passives

Between each layer of metal, poly silicon or silicon there are naturally capacitors. Dielectrics between dierent metal layers have a thickness of 0.5-1 m, which gives a rather large area for a given capacitance. A t Larger specic capacitance (capacitance per unit area) gives smaller area C=

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Thinning down dielectrics between metal layers will increase specic capacitance (F/cm2 ).

Capacitors, manufacturing
Mask and etch via Sin N Deposit and mask metal Start at oxide layerhole 4 layer n+1 layer) metal (extra 3

Course information Introduction The CMOS process NMOS and PMOS Passives

Critical distance

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metal oxide

Capacitors, layout
Capacitance Mask: CAP dened by VIA and CAP VIA METAL(n+1) METAL(n)

Course information Introduction The CMOS process NMOS and PMOS Passives

C = LW t L

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Summary

Course information Introduction The CMOS process NMOS and PMOS Passives

Analog vs. digital Analog design ow The CMOS process ow

NMOS and PMOS transistors Resistors Capacitors

Layout - top view

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