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2 Hardware and software co-design for a closed-loop servo control system Based on the SoPC technology, a closed-loop servo control system by mixing hardware and software implementation in FPGA chip will be discussed. The circuits requiring fast processing but simple computation are suitable to be implemented by hardware in the FPGA, and the complicated control algorithm with heavy computation can be realized by software in the FPGA [16][17]. The results of the software/hardware codesign increase the programmability and the flexibility of the designed digital system, enhance the system performance by parallel processing, and reduce development time. To exploit the features, a plant with first-order system and a PID controller to form a closed loop control system is taken as a design example and shown in Figure 3.4. The sampling time frequency using in plant system is 500 Hz but in digital controller is 1 kHz. The plant and the PID controller are described as follow:

Implementation can be divided into two methods: (1) Full hardware implementation: the plant and the PID controller are implemented by hardware.

(2) Hardware and software implementation: The plant is implemented by hardware, but the PID controller is implemented by software. Method 1: All hardware realization In this method, the closed-loop control system is implemented by hardware. In Figure 3.5 shows block diagram of PID controller, plant and the overall integrated program, respectively. Firstly, implement coding of the PID controller and the implement coding of the plant. Secondly, connect the PID controller block with the plant block.

(a) Overall control system (b) PID controller (c) Plant

Figure 3.6: VHDL code of overall closed-loop control system Hardware design has two kinds of implementation: The parallel processing and sequential processing using Finite state machine(FSM). But in this case does no require fast operation. So we can use Finite state machine (FSM) to simplify and consume at least chip resources. Figure 3.7 show the circuit design of plant using FSM method and sevenstep machine to carry out the overall computation of plant which mathematical model are shown in (3.1).

Figure 3.8: VHDL code of Plant Figure 3.9 show the circuit design of PID controller using FSM method in 12 steps to execute the PID controller which mathematical model are shown in (3.2), (3.3), (3.4), (3.5).

Figure 3.9: The circuit design of PID controller using Finite State Machine (FSM) In Figure 3.10 shows the VHDL code of PID controller follow the circuit design in Figure 3.9. We execute steps S0 ~ S12 from the codes lines 40 to 72.

End value of output Yn: 16376 for Q15 after 170 ns, maximum value = 20430 (0.4997 and 0.6234 for real value). And at the same time, we use the simulation result in MATLAB to compare with the result in QUARTUS II. The MATLABs simulation results are shown in Figure 3.12 for case 1 and Figure 3.14 for case 2.

Figure 3.13: Simulation result in Quartus II (case 2) End value of output Yn: 16384 for Q15 after 560 ns, maximum value = 28777, minimum value = 6975(0.5, 0.878 and 0.212 for real value)

Method 2: Hardware and software co-design In this section, hardware and software co-design method is presented. The plant is implemented by hardware in FPGA, while the PID controller is implemented by software using Nios II processor. The closed loop control is implemented with interrupt time 1 kHz. And overall structure is shown in Figure 3.15. It can be divided into two parts: Nios system and plant. In Nios system, the controller operation can be done and control signal is transferred to the plant through FPGA Avalon Buss I/O. After the feedback signal and the response results are buffered to the memory, wait until the interrupt active.Then they can be printed on the screen of the PC and can be collected. Then, the response results are plotted by using the MATLAB software. Therefore, under the procedure, the response result is shown in Figure 3.17.

Figure 3.15: Hardware and software co-design of closed-loop servo control system PID controller software is written by C language in Nios II software in Figure 3.16.

Conclusions: Compared with all hardware realization method, the hardware and software co-design implementation in the closed loop control system has the following benefits. 1) The speed processing is faster than the one done by hardware realization. 2) The overshoot is smaller than the one in the hardware realization case. 3) We can observe that the values of the hardware and software co-design method are very similar with the values in MATLAB simulation. However, when we implement hardware/software co-design method (8% LEs resource) the Chip resource is occupied more than using all hardware realization (1% LEs resource). Because the Nios II processor occupy with 3,652/40,877 LEs chip resource.