Proceedings of the 5th European Microwave Integrated Circuits Conference

HVVFET : A New 0.25m Channel Length RF POWER MOSFET with Ultra Low Feedback Capacitance
D. Rice, W. Z. Cai, B. P. Gogoi, M. Watts, P. Le, R. B. Davies, and D. Lutz
HVVi Semiconductors, 10235 South 51st Street, Suite 100, Phoenix, AZ 85044, USA Phone: +1-480-7763800
dave.rice@hvvi.com

TM

Abstract- A novel short channel vertical RF MOSFET (termed HVVFETTM) has been developed for avionics and L-band radar applications. The HVVFET employs a silicided polysilicon spacer that is formed along a vertical dielectric sidewall to serve as the gate. A second silicided poly layer is sandwiched between the gate interconnects and the Si wafer, thereby completely shielding the gate from the drain. Consequently, the HVVFET exhibits superior device characteristics such as a state of the art BVDSSRON-SP combination and very low capacitances, in particular, to the authors knowledge, a record low Cgd. The packaged HVVFET device with a total gate width of 64.5 mm shows a Cgd of 2.67X10-18 and 2.32X10-18 F/um at 25V and 40V respectively. The capacitance values are 1.65X10-18 and 1.3X10-18 F/um for a bare die under the same biases, representing a five-fold improvement over similar devices in the literature. The packaged HVVFET device exhibits superior RF performances in the 1.01.2GHz band, including a 19dB power gain, 0.8W/mm output power at 1dB compression and 45% PAE, and a 20:1 load mismatch survivability.

channel turn-on voltage and consequently a larger subthreshold slope than a typical NMOS. Second, the overlap parasitic capacitance is directly proportional to Lgs(d), ov. As described in [1, 2], the HVVFET addresses the aforementioned issues by adopting a silicided poly spacer as the gate electrode and a p-well that is self-aligned to the sidewall of a dielectric stack, thereby leading to a minimal lateral doping variation in the channel. II. HVVFET ARCHITECTURE One of the most novel aspects of the HVVFET resides in the formation of a sidewall poly spacer to function as the gate. Here, Lpoly is controlled by the thickness of the as-deposited polysilicon layer and a subsequent anisotropic dry etch process. Indeed, an Lpoly as small as 0.3 m is routinely achieved in the wafer fab using 0.5 m photolithography capability. (Theoretically, there is no lower limit on Lpoly. Hence this device architecture can be easily scaled/extended to suit different application space in terms of frequency and supply voltage.) Since extensive thermal cycles are avoided, the lateral overlaps of Lgs, ov and Lgd, ov in HVVFET are comparable to that of a conventional MOSFET. Fig. 1 compares the cross section of a conventional VDMOS and that of an HVVFET, along with a crosssectional image of a fabricated HVVFET. At the bottom of the dielectric stack, there is an undercut profile formed by an isotropic wet etch. As the poly deposition is highly conformal, it is deposited on top of gate oxide above the self-aligned pwell, it also extends laterally into the undercut region to cover a portion of the n-type drain. A shield plate is placed in close physical proximity to the vertical spacer gate, as well as underneath the entire gate interconnect, thus providing a complete shielding of the gate from the drain potential. III EXPERIMENTAL DETAILS The starting material consists of an n-type epi-layer on a heavily arsenic doped Si (100) substrate. The thickness and

I. INTRODUCTION A compact, lightweight and highly reliable power amplifier (PA) lineup is the holy grail for the next generation groundbased and in-flight radars. The RF/microwave power market in the 1.0-1.4 GHz band has 3 major players, all of which are silicon-based. Silicon bipolar transistor suffers from low power gain, typically less than 10dB. Even though silicon LDMOS has a gain of 10-15dB, it generally still requires an additional gain stage. The third competitor, the vertical DMOS transistor, suffers from high Cgd and Cds, since the chips entire back surface is tied to the drain. Further, VDMOS is prone to junction overheating since the thermal path between the heat generating element and back metallization, which serves as a heat sink, is typically greater than 100um. Compared to digital CMOS, RF LDMOS and VDMOS adopt a large gate poly dimension (Lpoly) typically 1 m or wider in the current flow direction to ensure a low gate access resistance. A short channel power transistor can be achieved only by using thermal diffusion for a given Lpoly, following Lg=Lpoly-Lgs,ov-Lgd,ov. The reliance on thermal diffusion to reduce Lg creates two problems. First, the lateral p-channel doping gradient is responsible for a non-uniform

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dopant concentration of the n-epi layer are optimized according to the breakdown and on-resistance specifications. The source and gate electrodes are contacted from the top surface, and the drain from the backside. Detailed process information can be found in [1-2]. A 200 gate oxide is used in our study.

IV. DEVICE CHARACTERISTICS A. Current-Voltage Characteristics As summarized in Table I, HVVFET exhibits an ultra-low Cgd with an excellent BVDSS-RON, SP performance

HVVFET (Shield under gate)

Gate

B. Capacitance-Voltage Characteristics It has been reported that Cgd is a limiting factor for achieving RF gain and low switching loses in LDMOS and a similar trend has been observed for VDMOS using circuit simulation. As displayed in Fig 2, the packaged HVVFET device shows a Cgd of 2.67X10 and 2.32X10 F/ m at 25V and 40V respectively, which is about one third of 8.6 X 10 F/ m for a (bare die) 115V VDMOS reported in [3]. In comparison, a Cgd of 1.5X10 F/ m has been reported on an LDMOS device[7]. As shown in Fig. 2 and Fig. 3, the capacitance displays a good scaling between the 22R1C and 22R2C devices.
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Fig. 1 Schematic cross-sections of HVVFET. The channel resides along the periphery of the hexagons, and the remaining portion of the hexagons becomes source and p-tub, which are shorted to ground potential to minimize gain of the parasitic bipolar transistor. Fig 2. Coss and Cgd versus Vd (with Vg =0) for packaged HVVFETs of
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A device termed 22R1C consists of 22 densely packed hexagons with a total gate periphery of 64.5mm lined up in a single column fashion. The 22R2C consists of two 22R1C devices connected in parallel.

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22R1C and 22R2C. A record low Cgd is found to be 2.67X10 and 2.32X10 F/ m at 25V and 40V, respectively. An even lower Cgd is identified to be 1.65x10 and 1.3x10-18 F/ m for the bare die under the same biases. These values show a five-fold reduction compared to the device reported in [3].
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PORT P=1 Z=50 Ohm

CAP ID=C1 C=0.06988 pF

Fig. 3. Ciss versus Vg (with Vd =0) for packaged HVVFETs of 22R1C and 22R2C. Frequency=1MHz.

Because the gate interconnects are run in parallel with the Si surface, a traditional VDMOS rules out the possibility of the bump process without adding capacitance. HVVFET solves this problem by employing a ubiquitous shield plate which reduces Cgd by orders of magnitude. Since the Si back surface is at the drain potential, an expensive use of shield over the top of the Si surface poses a challenge on Cds. To counter this, a deep trench based dielectric platform (DP) is employed to mitigate the impact. The DP consists of a mix of SiO2, polysilicon and air-gap with an effective dielectric constant of 5.5. The devices presented in this paper all have DP along the periphery of the active region of the die, which reduces the extrinsic components of Cds by approximately 50%. V. PERFORMANCE OF THE PACKAGED PARTS In HVVFET, the source/body terminal is permanently shorted to the shield by a top side metal consisting of 1 m Al and 50 m thick pure gold. A thermal adhesive is applied on top of this thick metal, and the entire Si die is flipped and directly attached to the Cu flange. The flip chip process establishes a solid ground plane. More importantly, the thick metal serves as an effective heat spreader that allows the heat to travel a short distance (~5 m) up through the metal to the Cu flange.

Fig. 5 Schematic diagram for de-embedding the intrinsic die from the package parasitics. The intrinsic device, shown in the middle, is represented by a simple black-box model.

Fig. 4 depicts the die with bond wires. The on-chip metal interconnects and bumps are built around the intrinsic die which is represented by a lumped model. Next, the package related parasitics are placed at the input and output ports, where the lumped model based on EM simulation is used. Fig. 5 shows the final schematic diagram in the simulation. Fig. 6 plots the s-parameters under the quiescent biases of Vdq=40V and Idq=50mA. A flat S versus frequency plot is seen between 960 and 1200MHz, with a peak gain of 17.8dB obtained at 1100MHz. The input return loss (S ) is less than 9dB over the same frequency band.
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Fig. 4 A close-up view of the completed die and wire bonds

Fig. 6 S-parameters for an input/output matched HVVFET device 22R1C under the quiescent biases of Vdq=40V and Idq=50mA. An S11 better than -9dB is seen across a useful frequency band of 240 MHz.

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REFERENCES
[1] B. P. Gogoi, R. B. Davies, J. Crowder, D. Lutz, P. Le, D. Rice, W. Wright, B. Battaglia, S. Tran, A. Elliott, and M. Golio, New Vertical Silicon Microwave Power Transistor Structure and Package With Inherent Thermal Self Protection, IMS, Boston, MA, June 712, 2009. [2] B. Battaglia, W. Wright, R. Neeley, and B. P. Gogoi, High Performance Vertical MOSFET Technology Enables Phased Array Radar Applications, 2008 European Microwave Conference, Amsterdam, Netherlands, Nov. 2008. [3] N. Nenadovi , V. Cuoco, M.P. v.d. Heijden, L.K. Nanver, J.W. Slotboom, S.J.C.H. Theeuwen and H. F. F. Jos, High Performance Silicon On Glass VDMOS Transistor for RF Power Applications, 32th European Solid State Device Research Conf., Firenze, Italy, Sept. 2426, 2002. [4] I. Corts, J. Roig, D. Flores, J. Urresti, S. Hidalgo, and J. Rebollo, A Numerical Study of Field Plate Configurations in RF SOI LDMOS Transistors, Solid State Electronics 50, pp. 155163, 2006. [5] G. Cao, S. K. Manhas, E. M. S. Narayanan, M. M. De Souza, and D. Hinchley, Comparative study of drift region designs in RF LDMOSFETs, IEEE Trans. Electron Devices, 51 (8) pp. 1296 1303, Aug. 2004. [6] V. Khemka, V. Parthasarathy, R. Zhu, A. Bow, and T. Roggenbauer, Floating RESURF (FRESURF) LDMOSFET Devices with Breakthrough BVdss Rdson, Proceedings of 2004 IEEE International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, p 415, 2004. [7] S. Xu, P. Foo, J. Wen, Y. Liu, F. Lin, and C. Ren, RF LDMOS with Extreme Low Parasitic Feedback Capacitance and High Hot Carrier Immunity, IEEE International Electron Devices Meeting, pp. 201204, Washington, DC, Dec. 58, 1999. [8] S. Xu, C. Ren, Y. C. Liang, P.D. Foo, and J. K. O. Sin, Theoretical Analysis and Experimental Characterization of the Dummy Gated VDMOSFET, IEEE Trans. Electron Devices, 48 (9), pp. 21682176, Sept. 2001.

Fig. 7 Small signal power gain as a function of frequency for packaged HVVFET device 22R1C.

Fig. 7 plots the power gain as a function of frequency. The excellent small-signal characteristics leads to superior large signal characteristics including a P1dB of 0.8W/mm at 1.1GHz under pulsed mode of operation and PAE of 45%. VI. CONCLUSIONS
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A novel BV=100V, Ron-SP =1.7m cm RF power MOSFET has been developed with state of the art performance. It shows
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a Cgd|25V of 2.67X10 F/ m and 1.65X10 F/ m for a packaged and a bare die HVVFET device, respectively. This record low feedback capacitance represents a fivefold improvement over similar devices in the literature, and is attributed to the ubiquitous shield plate. A flattop small signal gain S11 is seen across a 200MHz band centered at 1.1 GHz. ACKNOWLEDGEMENT The authors wish to acknowledge the assistance and support of K. Romine and L. J. Reed of HVVi, and L. Golonka, G. Grivna, G. Loechelt and P. Zdebel of ON Semiconductor.

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