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11/16/2006
Boolean methods
Exploit Boolean properties
Dont care conditions
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CS220: Synthesis of Digital System, Fall 06
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CS220: Synthesis of Digital System, Fall 06
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Dont Care
Inputs driven by a de-multiplexer CDCin=x1x2x3x4+x1x2+x1x3+x1x4+x2x3+x2x4+x3x4 Output y1, y2 can be observed only if x1=1 ODCout=[x1; x1; x4; x4] DCext=CDCin+ODCout
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CS220: Synthesis of Digital System, Fall 06
If Network N1 is a single logic function, the above DC condition can be used If N1 has multi-level and we want to simplify a single function, must propagate DCext to that point
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CS220: Synthesis of Digital System, Fall 06
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CS220: Synthesis of Digital System, Fall 06
Example of CDC
CDC of vy includes
x(a+b)+x(a+b)=xa+xb+xab b
* * * * 0 0 1 1 * 1 1 * 0 * * 0
Minimize y
b
0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0
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CS220: Synthesis of Digital System, Fall 06
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Example
SDC=x(a+b)+y(abx+acx)=xa+xb+xab+yabx+yac x+yac+yba+ybc+yx
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CS220: Synthesis of Digital System, Fall 06
b
0 0 0 0
b
* * 0 *
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CS220: Synthesis of Digital System, Fall 06
0 1 1 0
* * 1 *
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Example: f = z = abc
fx(1)=bc(ab)=bc(a+b)=abc ODC=f fx(1) =(abc)(abc)+(abc)(abc)=(a+b+c)(a+b+c)=ab+ac+ab+b+bc +ac+bc+c=b+c
Degree of freedom
Optimization of a local function is subject to many degree of freedom It is to be fully represented by local dont care condition, consisting of
External dont care
Need to be propagated to become local dont care in simplification
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CS220: Synthesis of Digital System, Fall 06
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Data-ready time ti
Input data-ready times denote when inputs are available Computed elsewhere by forward traversal
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CS220: Synthesis of Digital System, Fall 06
Example
dg=3, dh=8, dm=1, dk=10, dt=3 dn=5, dp=2, dq=2, dx=2, dy=3
tg=3+0=3 th=8+3=11 tk=10+3=13 tn=5+10=15 tp=2+max{15,3}=17 tl=3+max{13,17}=20 tm=1+max{3,11,20}=21 tx=2+21=23 tq=2+20=22 ty=3+22=25
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Slack si
Difference between required and actual data-ready times s
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CS220: Synthesis of Digital System, Fall 06
Example
Required data-ready times tx=25 and ty=25
dg=3, dh=8, dm=1, dk=10, dt=3 dn=5, dp=2, dq=2, dx=2, dy=3
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CS220: Synthesis of Digital System, Fall 06
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CS220: Synthesis of Digital System, Fall 06
Example
All gates have unit delay All inputs ready at time 0 Longest topological path : (va,vc,vd,vy,vz)
Path delay: 4 units
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CS220: Synthesis of Digital System, Fall 06
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Sensitizable paths
A path in a logic network is sensitizable if an event can propagate from its tail to its head A critical path is a sensitizable path of maximum weight Only sensitizable paths should be considered Non-sensitizable paths are false and can be discarded
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CS220: Synthesis of Digital System, Fall 06
Sensitizable paths
Paths
Ordered set of vertices
Inputs to a vertex
Direct predecessors
Side-inputs of a vertex
Inputs not on the path
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CS220: Synthesis of Digital System, Fall 06
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Dynamic sensitization
Path P=(vx0,vx1,,vxm) An event propagates along P if
fxi/ xi-1=1 i=1,2,,m
Boolean differences are function of the side-inputs Values on the side-inputs may change with time Boolean difference must be true at the TIME event propagates
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CS220: Synthesis of Digital System, Fall 06
Example
Path: (va,vc,vd,vy,vz)
fy/ d=(de)d(de)d=e0=e1+e0=e
e=1 at time 2
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CS220: Synthesis of Digital System, Fall 06
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