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B GIO DC V O TO B quc phng

HC VIN K THUT QUN S


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hong vn qun



nghin cu thit k
modul m khi dng trong x l mt
thng tin trn cng ngh fpga







LUN VN THC S K THUT




H Ni - 2005
i
Danh mc cc k hiu, cc ch vit tt

T vit tt Ting Anh

Ngha ting Vit
APEX Advanced Programmable logic
matriX
Ma trn logic lp trnh c
ASIC Application Specific Integrated
Circuit
Mch tch hp ng dng chuyn bit
CAD Computer Aided Design Cng c thit k c tr gip bi PC
CBC Cipher Block Chaining Lin kt khi m
CFB Cipher Freed Back Phn hi m
CPLD Complex Programmable Logic
Devices
Thit b lgc lp trnh phc hp
CMOS Complementary MOS Cng ngh MOS ci tin
DSP Digital Signal Processor X l tn hiu s
DES Data Encryption Standard Chun m d liu
ECB Electronic Code Book Sch m in t
EDA Electronic Design Automation H t ng thit k in t
EEPROM Electrically Erasable
Programmable Read-Only-
Memory
B nh ch c lp trnh v xo c
bng in
EPROM Erasable Programmable Read-
Only-Memory
B nh ch c lp trnh v xo c
FPGA Field-Programmable Gate
Array
Ma trn cng lp trnh c theo hng
GOST Chun m d liu X vit
HDL Hardware Description
Language
Ngn ng m t phn cng
IDEA International Data Encryption
Algorithm
Thut ton m ho d liu quc t
IEEE Institute of Electrical and
Electronic Engineers
Hip hi cc K s in v in t

ii
KAT Know Answer Test Php kim tra tnh sn kt qu
LSI Large Scale Integrated Tch hp mt ln
MAX Multiple Array matriX Ma trn chui a phn t
MSI Medium Scale Integrated Tch hp mt trung bnh
OFB Output Freed Back Phn hi u ra
PAL Programmable Array Logic Logic mng lp trnh c
PLA Programmable Logic Array Mng logic lp trnh c
PLD Programmable Logic Device Thit b logic lp trnh c
PROM Programmable Read-Only-
Memory
B nh ch c lp trnh c
RAM Random-Access Memory B nh truy xut ngu nhin
RISC Reduced Instruction Set
Computer
My tnh dng tp lnh rt gn
ROM Read Only Memory B nh ch c
SRAM Static Random-Access
Memory
B nh tnh truy xut ngu nhin cn
gi l RAM tnh
SSI Small Scale Integrated Tch hp mt nh
VHDL VHSIC Hardware Description
Language
Ngn ng m t phn cng ca mch
tch hp tc cao
VHSIC Very High Speed Integrated
Circuits
Mch tch hp tc cao
VKKAT Variable Key Know Answer
Test
Kim tra vi kho bin i
VLSI Very Large Scale Integrated Tch hp mt ln
VPAKT Variable Plaintext Know
Answer Test
Kim tra vi bn r bin i



iii
Mc lc

Danh mc cc k hiu, cc ch vit tt i
Trang
Mc lc
Danh mc cc bng
Danh mc cc hnh v
Li ni u....................................................................................................................... 1
Chng 1: tng quan v h truyn tin mt v c s l thuyt
m khi............................................................................................................................. 3
1.1. Tng quan v h truyn tin mt................................................................. 3
1.1.1. M hnh h thng truyn tin mt .................................................................3
1.1.2. Cc phng php m mt c bn .................................................................5
1.1.3. M hnh h mt ............................................................................................6
1.1.4. Phn loi h m. ...........................................................................................9
1.1.5. nh gi mt ca h thng truyn tin mt............................................10
1.2. C s l thuyt v m khi..........................................................................11
1.2.1. Khi nim v m khi ................................................................................11
1.2.2. Nguyn l thit k m khi........................................................................12
1.2.3. Cc tham s ca m khi ...........................................................................13
1.2.4. Cc cu trc m khi c bn......................................................................14
1.2.5. Cc m lp..................................................................................................17
1.2.6. an ton ca cc h m khi ..................................................................18
1.3. Gii thiu mt s k thut m khi........................................................19
1.3.1. Chun m d liu DES...............................................................................19
1.3.2. Chun m d liu X vit...........................................................................20
1.3.3. Thut ton m ho d liu IDEA...............................................................22
1.3.4. Cc ch hot ng ca m khi. ...........................................................25
1.3.5. Mt s gii php k thut thit k m khi................................................28
1.4. Kt lun chng 1 .............................................................................................30
Chng2: cng ngh fpga v ngn ng m t phn cng vhdl.32
2.1. tng quan v cng ngh FPGA.................................................................... 32

iv
2.1.1. Gii thiu v cng ngh FPGA..................................................................32
2.1.2. Qu trnh thit k c bn trn FPGA .........................................................41
2.1.3. Gii thiu v FPGA ca hng ALTERA: ..................................................46
2.1.4. Cc cng c thit k...................................................................................49
2.1.5. Cc ngn ng m t phn cng..................................................................53
2.2. ngn ng m t phn cng VHDL................................................................ 54
2.2.1. Gii thiu chung v ngn ng VHDL........................................................54
2.2.2. M hnh t chc .........................................................................................57
2.3. kt lun chng 2. ............................................................................................. 58
Chng 3: Phng php thit k modul m khi trn Fpga....... 59
3.1. cu trc ca Modul m khi ..................................................................... 59
3.1.1. Cu trc chung ...........................................................................................59
3.1.2. Mt s yu cu i vi modul m khi......................................................60
3.2. la chn thut ton cho m phng thit k ..................................... 60
3.2.1. La chn thut ton.....................................................................................60
3.2.2. M t thut ton DES. .................................................................................61
3.3. phng php thit k modul des trn fpga........................................ 68
3.3.1. Quy trnh v cng c thit k.....................................................................69
3.3.2. S khi chc nng ca modul m khi DES trn FPGA.......................70
3.3.3. M t hot ng ca cc khi trong modul DES bng VHDL. .................73
3.3.4. Phn cng m phng modul DES .............................................................84
3.3.5. Kim tra s hot ng ca DES trong modul m khi ..............................86
3.4. kt qu thit k modul m khi des ....................................................... 88
3.4.1. Kt qu thit k...........................................................................................88
3.4.2. nh gi kt qu thit k modul m khi ...................................................92
Kt lun.......................................................................................................................... 93
Ti liu tham kho................................................................................................... 95
PH LC 1 ............................................................................................................................I
Ph lc 2: ........................................................................................................................iV



v
Danh mc cc bng

Trang

Bng 2.1: Mt s loi FPGA trn th trng .............................................................47
Bng 2.2: S cng s dng v cc chn I/O ca cc h thit b Altera....................48
Bng 3.1: Cc tham s ca php hon v ban u IP.................................................64
Bng 3.2: Cc tham s ca php hon v FP .............................................................64
Bng 3.3: Cc tham s ca hm m rng E ..............................................................65
Bng 3.4: Tham s ca cc hp S-Box......................................................................66
Bng 3.5: Cc tham s ca php hon v P................................................................66
Bng 3.6: Cc tham s ca php hon v PC-1..........................................................67
Bng 3.7: Cc tham s ca php hon v PC-2..........................................................68
Bng 3.8: M t cc tn hiu vo ra ca modul DES.................................................72
Bng 3.9: Danh sch cc tp tin ca modul DES. .....................................................73
Bng 3.10: Chc nng cc tn hiu vo/ra ca EPC2 LC 20 .....................................90


vi
Danh mc cc hnh v
Trang

Hnh 1.1: M hnh h thng truyn tin........................................................................3
Hnh 1.2: M hnh h thng truyn tin mt.................................................................4
Hnh 1.3: M hnh h mt kho b mt .......................................................................7
Hnh 1.4: M hnh h mt kho cng khai..................................................................8
Hnh 1.5: S cu trc cng-nhn. ........................................................................16
Hnh 1.6: Mt m lp r vng vi hm vng f ............................................................17
Hnh 1.7: M t mt vng ca DES ..........................................................................20
Hnh 1.8: S mt vng lp ca GOST.................................................................21
Hnh 1.9: S cu trc ca IDEA...........................................................................23
Hnh 1.10: Chi tit mi vng n ca IDEA.............................................................24
Hnh 1.11: Php bin i ra ca qu trnh m ho IDEA .........................................24
Hnh 1.12: Cc ch hot ng ca m khi .........................................................27
Hnh 1.13: Cc k thut thit k m khi..................................................................28
Hnh 2.1: Cu trc ca PLA.....................................................................................33
Hnh 2.2: Cu trc ca PAL.....................................................................................33
Hnh 2.3: Cu trc ca CPLD...................................................................................34
Hnh 2.4: M t m hnh ca mt FPGA. ................................................................36
Hnh 2.5: Cu trc Logic Cell trong linh kin FPGA...............................................37
Hnh 2.6: Cu trc ca FPGA. .................................................................................38
Hnh 2.7: Bn loi FPGA in hnh .........................................................................39
Hnh 2.8: Cu trc SRAM FPGA (SRAM Logic Cell) ............................................39
Hnh 2.9: Cu trc ca OTP FPGA (OTP Logic Cell) .............................................40
Hnh 2.10: Qu trnh thit k trn FPGA..................................................................42
Hnh 2.11: Kin trc tng qut ca Altera FPGA MAX 7000..................................47
Hnh 2.12: S khi mt modul m t bng VHDL..............................................55
Hnh 3.1: Cu trc chung ca modul m khi..........................................................59
Hnh 3.2: Lc ca thut ton DES.....................................................................62
Hnh 3.3: Mt vng ca DES ...................................................................................63

vii
Hnh 3.4: Hm F ca thut ton DES........................................................................63
Hnh 3.5: S tnh kho ca thut ton DES. .........................................................68
Hnh 3.6: S khi tng qut ca modul m khi DES trn FPGA.......................70
Hnh 3.7: Qu trnh m ho/gii m DES .................................................................71
Hnh 3.8: M t chc nng modul m ho DES........................................................72
Hnh 3.9: Cu trc I/O ca DES trn cng c Quartus .............................................73
Hnh 3.10: S thc th php hon v IP................................................................75
Hnh 3.11: M t 16 vng lp ca DES.....................................................................76
Hnh 3.12: S thit k ca mt vng lp. .............................................................76
Hnh 3.13: S thc th hp S-BOX.......................................................................79
Hnh 3.14: S khi to kho con. .........................................................................80
Hnh 3.15: M t khi vo/ra d liu ........................................................................83
Hnh 3.16: S lin kt gia cc khi trong Modul DES.......................................83
Hnh 3.17: S khi phn cng ca modul m khi DES......................................85
Hnh 3.18: S ghp ni gia FPGA v cp MV..................................................86
Hnh 3.19: S ghp ni gia FPGA v linh kin cu hnh ...................................86
Hnh 3.20: S khi phn cng modul m khi trn thc t.................................89
Hnh 3.21: Hnh nh modul m khi c thit k m phng.............................91


1
Li ni u

Cuc cch mng v cng ngh thng tin ang tc ng su sc n cc lnh
vc ca i sng x hi, c bit trong lnh vc truyn thng. Mt trong cc th hin
l tc truyn thng ngy cng cao, chuyn ti nhiu loi hnh thng tin khc
nhau. c im ny t ra yu cu cho ngnh mt m l cc thit b x l bo mt
thng tin phi c chuyn dng ho v lm vic c trn cc lung thng tin tc
ln. Vi nhng k thut bo mt truyn thng, i hi trn l rt kh khn, thm
ch khng gii quyt c. Trong khi , cc h thng bo mt tin tc cp quc
gia khng th gii quyt bng con ng nhp ngoi. Do vy, vic nghin cu thit
k thit b bo mt chuyn dng, hot ng vi tc ln l nhu cu cn thit v
cp bch.
Trong k thut mt m, h m khi c nh gi l h mt c nhiu u im,
ph hp cho cc hot ng bo mt tc cao. Tuy nhin, t trc n nay nc
ta, cc thut ton m khi mi ch c thc hin bng phn mm trn my tnh PC
v ch p dng c cho cc h truyn tin c tc khng cao, do vy kh nng ng
dng m khi vo bo mt cho cc lung thng tin tc cao cn gp nhiu kh
khn. Bi ton bo mt lung d liu tc cao ch c th gii quyt c trn c s
cng ho c cc thut ton m khi, theo ngha vic thc hin cc thut ton
m khi c thit k bng phn cng. Do tnh cht phc tp ca cc thut ton m
khi, vic cng ho m khi theo phng php thit k mch in t truyn thng
trong iu kin nn khoa hc v cng ngh Vit Nam cn hn ch l rt kh khn,
trong khi hin nay c nhiu cng ngh hin i x l bi ton ny nh
ASIC, FPGA ...
Nhm gp phn gii quyt vn trn, ti chn ti lun vn tt nghip
Nghin cu thit k modul m khi dng trong x l mt thng tin trn cng
ngh FPGA. Lun vn c nhim v: Tm hiu mt s cc h m khi ang c
dng bo mt ni dung thng tin trong h truyn tin mt t la chn mt h
m khi tiu biu thit k, tch hp modul m khi bng cng ngh FPGA, nm
chc cng ngh thit k, ch to trn FPGA cng nh ngn ng m t phn cng


2
HDL, t i su nghin cu cc gii php, cng c h tr thit k m phng
modul m khi chuyn dng trn cng ngh FPGA.
Ni dung ca lun vn bao gm 3 chng:
Chng 1: Tng quan v h truyn tin mt v c s l thuyt m khi.
Chng 2: Gii thiu v cng ngh FPGA v ngn ng m t phn cng.
Chng 3: Phng php thit k modul m khi trn cng ngh FPGA.
Qua mt thi gian nghin cu, lun vn hon thnh c ni dung t ra.
Nhn dp ny, ti xin by t li cm n chn thnh n thy gio PGS.TS Xun
Tin tn tnh, trc tip hng dn v c nhng kin ht sc qu bu gip ti
trong qu trnh thc hin lun vn. Ti cng xin by t lng bit n n cc thy
gio, c gio khoa V tuyn in t - HVKTQS v nhng kin thc nhn c
trong thi gian hc ti Trng. Ti xin cm n Cc C yu - B Tng tham mu v
cc bn ng nghip gip ti trong qu trnh hc tp v hon thnh lun vn.
D c gng song lun vn khng khi c nhng thiu st, rt mong c s
ng gp ch bo ca cc thy v cc ng nghip lun vn c hon chnh hn.


H Ni, Ngy 16 thng 5 nm 2005




3
Chng 1
tng quan v h truyn tin mt v c s
l thuyt m khi

1.1. Tng quan v h truyn tin mt
1.1.1. M hnh h thng truyn tin mt
Trong cuc sng, con ngi lun c nhu cu trao i thng tin vi nhau c
ngha l c nhu cu truyn tin cho nhau. Hnh 1.1 biu din m hnh ca h thng
truyn tin bao gm: Ngun tin, knh tin v nhn tin.

NGUN TIN KNH TIN NHN TIN

Hnh 1.1: M hnh h thng truyn tin
Trong m hnh ny: Ngun tin l ni sn sinh ra cc tin tc cn truyn i trn
knh tin di dng cc bn tin. Knh tin l mi trng vt l xc nh truyn cc
bn tin di cc dng tn hiu in, quang Nhn tin l c cu khi phc thng tin
ban u t tn hiu ly u ra ca knh tin.
Do x hi ngy cng pht trin, nn nhu cu trao i thng tin cng tng theo
khng ngng. Cc ni dung thng tin c lin quan n li ch, quyn li ca mt s
ngi hay mt giai cp no cn c gi kn, b mt v vy nhu cu bo mt ni
dung thng tin c truyn i hnh thnh v pht trin ngy cng ln.
Song song vi s pht trin mnh m ca khoa hc cng ngh ni chung v
cng ngh thng tin ni ring th bo mt ni dung thng tin ng mt vai tr ht
sc quan trng i vi tt cc cc lnh vc: Chnh tr, qun s, ngoi giao, kinh t,
x hi v i vi an ninh ca mi quc gia trn ton th gii.
Do vy h thng truyn tin mt l h thng m trong ni dung thng tin
phi c bo v v gi b mt khi truyn trn knh tin trc s tn cng, khm ph
bt hp php ca m thm. Hnh 1.2 m t mt cch tng qut v m hnh ca mt


4
h thng truyn tin mt. Trong : M ho l qu trnh bin i cc bn tin r R
thnh cc bn tin m M bng thut ton m ho E v c xem nh mt hm :
M = E(R,K
E
)

M HO KNH TIN NHN TIN GII M
NGUN TIN
KHO MT M
M THM
KHO MT M
NHIU
Hnh 1.2: M hnh h thng truyn tin mt
Gii m l qu trnh bin i ngc ca m ho c ngha l bin i cc bn
tin m M t u ra ca knh tin thnh cc bn tin r R a ti nhn tin v cng
c xem nh mt hm:
R = D(M,K
D
)
Cc kho m K
E
v kho dch K
D
c gi l kho m mt tham gia vo cc
thut ton m ho E v thut ton gii m D.
M thm l cc i tng c kh nng chn bt, thu nhn cc bn tin m M t
knh tin, nhng khng bit kho m K
E
v kho gii m K
D
nhm tm ra bn tin r
R (thng thng m thm s dng kho gii m K
'
D
tm ra bn r R
'
R).
Nhiu l do s tc ng ca mi trng truyn dn.
i khi thng b ng nht hai khi nim h thng truyn tin mt v h mt
khi nh gi mt ca h thng. Theo [1] h mt l mt b 5 (R, M, K, E, D) tho
mn cc iu kin sau:
a. R (khng gian cc bn tin r) l mt tp hp hu hn cc bn r c th c.
b. M (khng gian cc bn tin m) l mt tp hp cc bn tin m c th c.
c. K (khng gian kho) l mt tp hp hu hn cc kho mt m c th c.


5
d. i vi mi kK c mt quy tc m ho e
k
E v mt thut ton gii m
tng ng d
k
D, m mi e
k
: R M v d
k
: M R l nhng hm c tho mn
d

k
(e
k
(x)) = x vi mi bn tin r x R.
iu kin (d) l quan trng nht c ngha l nu c mt bn tin r x c m
ho bng thut ton E v bn tin m nhn c sau c gii m bng thut ton
gii m D th phi thu c bn tin r x ban u.
1.1.2. Cc phng php m mt c bn
C hai phng php m mt c bn l: Chuyn v (Transportation) v thay th
(Substitution).
1.1.2.1. Phng php chuyn v
Chuyn v l s thay i cc v tr cc thnh phn ca bn tin r theo mt quy
c no . S thay i v tr ny ph thuc vo mt kho xc nh dng cho c m
ho v gii m.
Nhn thy rng h m chuyn v khng c cc php ton i s no c thc
hin khi m ho, gii m v di ca bn tin m bng vi di ca bn tin r,
nn m thm c th d dng khm ph tm ra bn tin r ban u nh vic tm cc
hon v c ngha t bn tin m. Cc thnh phn ca bn tin b xo trn thay i trt
t lm bin i v hnh thc nhng v cht th vn tn ti tn sut xut hin ca
cc phn t r trong bn m vn gi nguyn. Phng php ny c mt rt hn
ch.
1.1.2.2. Phng php thay th
Thay th l s thay th cc phn t ca bn tin r bng cc phn t ca bn tin
m tng ng theo mt quy c xc nh no nhn c bn tin m mong
mun. Trong phng php thay th c nhiu dng khc nhau: thay th n biu
(Monoalphabetic), thay th a biu (Polyalphabetic) v thay th ngu nhin
(Random substitution). in hnh cho phng php thay th n biu l phng
php Julius Caesar vi m hnh thay th tng ch ci trong bn r bng mt ch ci
khc tng ng to thnh bn m. Trong phng php ny cc ch ci r t A
n Z nm trn hai vng trn ng tm, bc lch gia hai vng trn chnh l bc


6
thay th. Phng php ny ch lm thay i b mt ca bn r bng vic dch
chuyn tn xut, rt d dng khm ph. Vi phng php thay th a biu, vic
khm ph tr nn kh khn hn, c trng cho phng php ny l phng php s
dng bng Vigenre. Cui cng l phng php thay th ngu nhin. Vic thay th
cng ngu nhin th mt cng cao, song vic phc hi li bn r li cng phc
tp. thc hin qu trnh m ho v gii m cn phi c kho m.
1.1.3. M hnh h mt
Cc h mt hin nay c chia thnh hai loi: h mt kha b mt v h mt
kha cng khai. Trong h mt kha b mt, nhng ngi s dng hp php (ngi
gi v ngi nhn) phi chia s mt kha b mt chung v kha khng c bit
i vi thm m i phng. Trong h mt kha cng khai, ngi s dng hp php
ch cn cc thng tin trung thc cng khai no . Trong lun vn ch cp n
vic ng dng cc h mt kho b mt.
1.1.3.1. H mt i xng (H mt kho b mt)
Theo [2] m hnh h mt ca Shannon c th hin trong hnh 1.3. Trong m
hnh ny, kha b mt Z c phn phi ti ngi gi v ngi nhn theo mt knh
an ton. Kha ny sau c s dng m ha bn r X thnh bn m Y bi
ngi gi v c dng gii m bn m Y thnh bn r X bi ngi nhn. Bn
m c truyn trn knh khng an ton v gi thit rng thm m i phng lun
c th truy nhp nhn c cc bn m. Tt nhin thm m khng th truy nhp
c ti kha b mt. H mt kha b mt nh th c gi l h mt i xng
phn bit vi h mt kha cng khai khng i xng trong cc kha khc nhau
c s dng bi ngi m v ngi dch. Ch rng X, Y, v Z trong m hnh ny
l cc bin ngu nhin. Trong m hnh ny, cng lun gi thit bn r X v kha Z
l c lp thng k.
Cc h mt kha b mt thng c chia thnh cc h m khi v h m
dng. i vi m khi bn r c dng cc khi "ln" (chng hn 64-bit) v dy cc
khi u c m bi cng mt hm m ha, tc l b m ha l mt hm khng
nh. Trong m dng, bn r thng l dy cc khi "nh" (thng l 1-bit) v c
bin i bi mt b m ha c nh.


7
Cc h m khi c u im l chng c th c chun ha mt cch d dng,
bi v cc n v x l thng tin hin nay thng c dng block nh bytes hoc
words. Ngoi ra trong k thut ng b, vic mt mt block m cng khng nh
hng ti chnh xc ca vic gii m ca cc khi tip sau, cng l mt u
im khc ca m khi.
Nhc im ln nht ca m khi l php m ha khng che du c cc
mu d liu: cc khi m ging nhau s suy ra cc khi r cng ging nhau. Tuy
nhin nhc im ny c th c khc phc bng cch a vo mt lng nh c
nh trong qu trnh m ha, tc l bng cch s dng cch thc mc xch khi m
(CBC - Cipher Block Channing mode) trong hm m ha khng nh c p vo
tng XOR ca khi r v khi m trc . Php m lc ny c kiu cch k thut
nh m dng p dng i vi cc khi "ln".

Z Z Z
KKKkkKenhkKKKInh an
tonKKKKKKKKKKKKK
X
X
X
Y X
M ho
E
K
(.)
Gii m
D
K
(.)
M ho
E
K
(.)
Ngun
kho
Thm m
Nhn tin Ngun r
Hnh 1.3: M hnh h mt kho b mt
1.1.3.2. H mt khng i xng (h mt kho cng khai)
Nm 1976, Diffie v Hellman trng i hc tng hp Stanford a ra
mt dng mi ca h mt vi tn gi l h mt kho cng khai (Public-key


8
Cryptosystem). im khc bit gia h mt khng i xng v h mt i xng
chnh l kho m dch. Trong h mt khng i xng, kho m v kho dch khc
nhau, hn na chng khng ch khc nhau m cn c tnh ton trong mi quan h
tng tc theo cc hm ton hc no . y l h mt hin i da trn c s cc
thnh tu ca ton hc v cng ngh thng tin, th hin ch yu trn phc tp
tnh ton v tin dng trong qu trnh phn phi kho, in hnh cho h mt ny
l cc bi ton kho cng khai nh RSA, Diffie Hellman
Hnh 1.4: M hnh h mt kho cng khai
B m ho
B gii m

X=D
K2
(E
K1
(X))
Bn r
(X)
Ngi gi
(A)
Ngi nhn
(B)
Kho cng
khai (K
1
)
Kho b mt
(K
2
)
Bn m
Y=E
K1
(X)
Qu trnh m dch c m t nh sau:
Y = E
K1
(X)
X = D
K2
(E
K1
(X))
K
1
= f (K
2
)
K
2
= f (K
1
)
trong Y - bn m; X - bn r dch; K
1
- kho m; K
2
- kho dch.
H mt vi kho cng khai c xc nh bi 3 thut ton to kho, m ho
v dch m. Thut ton to kho c cng khai, c th cung cp cho n u vo
dng ngu nhin r c di cn thit v nhn c trn u ra cp kho (k
1
,k
2
). Mt
trong hai kho (chng hn kho k
1
) c cng b rng ri, n c gi l kho cng
khai, cn kho th hai c giu kn v c gi l kho b mt. Cc thut ton m
ho E
K1
v dch m D
K2
phi c bo m vi bn r bt k m u c:
D
K2
(E
K1
(m)) = m .


9
1.1.4. Phn loi h m.
M khi v m dng l hai loi hnh m ho c bn, thc hin chc nng m
dch thng tin b mt trong mt h thng s dng mt m. Chng thuc h m i
xng, s dng mt kho b mt cho cc tc v m ho v gii m.
M dng: L mt dng bin i lot, bin i tun t bn m theo bt (k t).
B to dy kho hay cn gi l b to kho chy sinh ra cc bt k
1
, k
2
,, k
i
,Dy
kho ny c cng m un 2 vi dy cc bt ca bn r: p
1
, p
2
,, p
i
, thnh
bn m: c
i
= p
i
k
i
. Ti pha nhn, bn m c cng modulo 2 vi dy kho ng
nht c bn r: c
i
k
i
= p
i
k
i
k
i
= p
i
.
Trong h m dng thay th ngu nhin one-time pad (kho dng mt ln), C.E.
Shannon ch ra rng nu kho l dy ngu nhin l tng (cc phn t kho xut
hin c lp, ng xc sut) th h mt l hon thin. Tc l, thm m khng th
khai thc c g d c bao nhiu bn m trong tay. Tuy nhin, iu bt li ca h
mt ny l vic to kho, qun l v phn phi kho vi mt khi lng ln hoc
khong cch xa s rt kh khn, tn km. V th cn phi nghin cu cch to kho
bng cc thut ton ton hc, v chng c gi l kho gi ngu nhin.
M khi: Vn t ra theo mt gc khc, mi mt ln m, kho c
ly ngu nhin trong khng gian kho sau c nh li v dng m ho cho tt
c cc khi bn r trong phin lin lc hoc trong sut thi gian n nh no .
Nh vy c th xem, m khi l mt h m thay th tt nh, vi khng gian kho
ln. Khi c nh mt di kho (hay khng gian kho) ln tn cng
vt cn trn chng l v ngha, th vn t ra cho cc nh thit k m khi l phi
tm kim cc hm t hp thay th c khuych tn hay bt nh tt thm m
cho d c kh nhiu cp r-m tng ng cng khng th c thi gian hay khng
c thut ton tm ra c kho c th c s dng. Theo C.E.Shannon, cc
hm t hp thay th c th s dng cc php bin i thnh phn c bn nh hon
v, php nn-gin, php th gin n...
Song song vi vic nghin cu cc m php, cc nghin cu tn cng, phn
tch, thm m cc h ny cng pht trin. Cho ti nay, c hai phng php tn cng
mnh nht i vi m khi l: tn cng vi sai v tn cng tuyn tnh.


10
1.1.5. nh gi mt ca h thng truyn tin mt
Nhim v ch yu ca h thng truyn tin mt l gi b mt ca thng tin c
truyn trn knh tin trc s tn cng, khm ph ca m thm. Nh vy mt ca
h thng truyn tin mt hon ton ph thuc vo an ton ca h mt m c
dng trong n. C hai quan im c bn v an ton ca mt h mt:
Th nht l an ton tnh ton: o ny lin quan n kh nng tnh ton
cn thit khm ph, tn cng mt h mt. Mt h mt l an ton v mt tnh ton
nu thut ton tn cng, khm ph h thng cn t nht N php ton m N l mt
s rt ln no . Vn l ch, khng c mt h mt thc t bit no c th
chng t l an ton theo nh ngha ny. Trn thc t, ngi ta gi mt h mt l
an ton v mt tnh ton nu c mt phng php tt nht ph h ny nhng yu
cu v mt thi gian ln n mc khng th chp nhn c.
Th hai l an ton khng iu kin: o ny lin quan n an ton ca
cc h mt khi khng c hn ch no c t ra v kh nng tnh ton m m thm
c th thc hin. Mt h mt c xem l an ton khng iu kin (tuyt mt hay l
tng) nu n khng th b tn cng, khm ph vi kh nng tnh ton khng hn
ch. Tt nhin ta cng phi xt n cc kiu tn cng ca m thm xy dng cc
h thng an ton hn na.
Trong h thng truyn tin mt kho mt m quyt nh bo mt ca ton b
h thng. Trong [1] a ra tiu chun ca h thng truyn tin mt nh sau:
mt cn thit s xc nh thut ton ph hp cho vic m ho v gii m.
Tiu chun ny th hin mt nguyn l rt c bn l mt thut ton m ho n gin
cng c th mnh ngn chn cc i tng m thm "chn bt tnh c" hoc
bo mt truyn tin trong mt khong thi gian ngn.
Khng gian kho v thut ton m ho khng c qu phc tp. Tiu chun
ny cho thy rng khng nn hn ch s la chn cc kho hoc cc kiu bn tin r
m thut ton m ho lm vic trn . Nu thut ton m ho ch lm vic vi cc
bn tin r c cng di th l mt thut ton yu, d b khm ph. Tng t, rt
kh la chn kho m tng cc phn t ca kho l mt s nguyn t. Nhng hn
ch nh vy s lm cho vic s dng thut ton m ho rt phc tp. Mc d mt


11
thut ton m ho phc tp s tng bo mt ca h thng, nhng s lm thi gian
x l, truyn tin tng ln mt cch ng k. Nn mt thut ton m ho ph hp l
thut ton ti u gim thiu nhng tr ngi cho vic truyn tin.
Cc li trong qu trnh m ho khng c lan truyn v gy ngt tin trong
cc bn tin r nhn c khi gii m. M ho c th gy li cho qu trnh truyn tin
hoc lm sai lch ni dung thng tin t cc bn tin m cng b sai lch theo hoc
b gin on ton b qu trnh truyn tin. Do chng ta cn hn ch ti a vic gy
li bi qu trnh m ho.
Kch thc hay di ca bn tin m khng c ln hn di ca bn tin
r ban u, nu iu ny xy ra n s khng th mang c nhiu thng tin nh bn
tin r v thi gian truyn tin trn knh cng s b tng theo.
Nhn chung cc tiu chun ny c xut nhm nh gi cht lng ca h
thng truyn tin mt. Trong iu kin hin nay nh s pht trin mnh m ca khoa
hc v cng ngh c bit l cng ngh FPGA, cc thut ton m ho, gii m c
th c thit k cng ho trong cc thit b bo mt nn vic xy dng mt
ti u cho tng h thng vi tng mc ch c th s c thc hin mt cch thun
li.
1.2. C s l thuyt v m khi
1.2.1. Khi nim v m khi
M php khi l h cc bin i thun nghch cc khi (phn di xc nh)
ca bn r. Thc t, m php khi l h mt thay th trn b ch ci cc khi (php
th c th mt hoc nhiu b ch ci tu thuc vo iu kin ca m php khi).
Cc m php khi hin nay c s dng rt ph bin.
Gi s F
2
l trng Galois hai phn t. K hiu F
2
m
l khng gian vc t cc
b m-tuples cc phn t ca F
2
. Trong phn ny gi thit khng mt tng qut rng,
bn r X, bn m Y ly cc gi tr trong khng gian vc t F
2
m
, cn kha Z ly gi
tr trong khng gian vc t F
2
k
. Nh vy m-l di bt ca cc khi r v m, cn
k-l di bit ca kha b mt.
nh ngha 1.1: H m khi kha b mt l mt nh x E: F
2
m
x S
z
F
2
m
, sao cho


12
vi mi z S
z
, E(., z) l mt nh x c ngc t F
2
m
vo F
2
m
.
Hm ngc E(., z) c gi l hm m ha tng ng vi kha z. nh x
nghch o ca E(., z) c gi l hm gii m tng ng vi kha z v s c k
hiu l D(., z). Chng ta vit Y = E(X, Z) i vi mt m khi c ngha l bn m Y
c xc nh bi bn r X v kha b mt Z theo nh x E. Tham s m c gi l
di khi cn tham s k c gi l di kha ca h m khi . C kha ng
ca h m khi c xc nh bi s k
t
= log
2
(#(S
z
)) bit. Nh vy di kha s
bng c kha ng nu v ch nu S
z
= F
2
k
, tc l mi b k-bit nh phn u l mt
kha c hiu lc. Chng hn i vi chun m d liu DES, di kha l k = 64
bit, trong khi c kha ng ca n l k
t
= 56 bit. Ch rng y ta xem xt cc m
khi c di khi m bng di khi r.
1.2.2. Nguyn l thit k m khi.
Mt h m khi tt l phi "kh ph v d s dng". C hai hm m ha E(., z)
v hm gii m D(., z) nn d dng tnh ton. Cn vic gii kha z t y = E(x, z) v
x = D(y, z) nn l bi ton kh. Nguyn l thit k cho mt h m khi c th chia
thnh cc nguyn l ng dng v cc nguyn l an ton.
1.2.2.1. Nguyn l thit k chung v an ton
C hai nguyn l thit k c chp nhn chung i vi cc m an ton thc t
l cc nguyn l v mo (confusion) v khuych tn (diffusion) c gi
bi Shannon.
- Nguyn l v mo (confusion):
S ph thuc ca kha trn bn r v bn m nn phi phc tp sao cho n
khng c ch g i vi thm m. Chng hn, phng trnh nh phn m t m khi
nn l phi tuyn v phc tp sao cho vic gii kha z t x v y=E(x, z) l khng
th.
- Nguyn l v khuych tn (diffusion):
Vi mi kha c th hm m ha khng nn c s ph thuc thng k no
gia cc cu trc n gin trong bn r v cc cu trc n gin trong bn m v
rng khng c quan h n gin no gia cc hm m ha khc nhau. Nguyn l


13
khuych tn i hi, chng hn mt h m khi cn c thit k c tnh y -hay
hon thin, tc l mi bit r v mi bit kha u nh hng ti mi bit m.
1.2.2.2. Nguyn l thit k cho ng dng
Mt h m khi c th ng dng c phn cng v phn mm. Trong ng dng
cng thng c thc hin bi cc chp VLSI, FPGA c tc cao. Trong ng
dng mm phi c tnh mm do v gi thnh thp. Trn c s c tnh khc nhau
ca phn cng v phn mm, cc nguyn l thit k m khi cng chia thnh hai
phn.
- Nguyn l thit k cho ng dng mm:
S dng khi con: Cc thao tc m khi nn thc hin trn cc khi con c
di t nhin cho phn mm l 8, 16, 32 bit. Hon v bit l kh thc hin trong phn
mm nn trnh.
S dng cc php ton n gin: Cc thao tc m trn cc khi con nn chn
d dng cho ng dng vi cc tp lnh c s ca cc b x l chun chng hn nh
php cng, php nhn, php dch ...
- Nguyn l thit k cho ng dng phn cng:
S tng t trong php m ha v php gii m: Qu trnh m ha v gii m
nn ch khc nhau cch s dng kha mt sao cho cng mt thit b c th s
dng c cho c php m ha v php gii m.
Cu trc u: H m khi nn c cu trc u c th d ng dng cng
ngh VLSI, FPGA trong vic thit k.
1.2.3. Cc tham s ca m khi
1.2.3.1. di khi m
mt h m khi l an ton, di khi m ca n phi ln ngn cn cc
tn cng phn tch thng k, tc l khng cho i phng thu c thng tin c
ch no v khi r no thng xut hin nhiu hn cc khi r khc. Ngoi ra
di khi m cng phi c chn sao cho s cc cp r/m m i phng c th
thu nhn c trong thc t phi nh hn rt nhiu so vi 2
m
.
Khi di khi ca h m tr nn ln th phc tp ca ng dng cng tng
theo. D rng phc tp trong ng dng chn ngu nhin hm c ngc l tng


14
theo c m so vi di khi, nhng ch c hm n gin mi xut hin ngu
nhin, iu ny to c hi cho hm m ha thc t khi di khi m l ln. Tuy
nhin, Shannon ch ra rng s d dng trong tnh ton cc hm m ha E(x, z) v
hm gii m D(y, z) vi mi z khng suy ra c vic gii tm kha z t cc phng
trnh y = E(x, z) v x = D(y, z) s l d dng khi bit x v y.
1.2.3.2. di kha k v c kha ng k
t
mt h m khi an ton chng li tn cng vt cn kha, c kha ng cn
phi ln sao cho php m ha cn cho tn cng ny l vt xa kh nng
ca thm m. Mt khc, di kha k cng cn nh mc no sao cho vic to,
phn phi v lu tr kha c th thc hin c hiu qu v an ton. Chng hn,
DES c di kha l 64 bt, cn c kha ng l 56 bit. Tn cng vt cn kha l
khng th nhng cng khng l qu xa vi. Nhiu gi mun tng c kha ng
ca DES. Chng hn, m rng c kha dng ca DES ti 128 bit bng php m bi
ba dng hai kha xem l mt cch thc chun s dng DES.
2
1 k
t

1.2.4. Cc cu trc m khi c bn


1.2.4.1. Cu trc m Feistel
Phn ln cc h m khi trn th gii hin nay l da trn cu trc m ho-gii
m Feistel c cc c tnh c bn sau:
- di ca mi khi r bng di ca mi khi m, v l mt s chn m = 2.L.
- Bn r c chia thnh cc khi P = (x
0
, x
1
) c di 2. L, v x
0
= x
1
=L.
- Kho k l mt tp kho con: k
1
, k
2
, .., k
n
.
- Mi k
i
c tng ng vi mt php bin i F
i
trn khi c L.
- Bn r P c m ho theo n-bc nh sau:
Bn r:
Vng 1: (x
0
, x
1
) (x
1
, x
2
)
P = (x
0
, x
1
)
Vng 2: (x
1
, x
2
) (x
2
, x
3
)
---------------------------------
Vng i: (x
i-1
, x
i
) (x
i
, x
i+1
)
----------------------------------


15
Vng n: (x
n-1
, x
n
) (x
n
, x
n+1
)
C = (x
n+1
, x
n
)
Bn m l:
trong x
i+1
= x
i-1
F
i
(x
i
)
Vi cu trc m ho trn y, qu trnh gii m s rt n gin: Gi nguyn
cc thao tc nh qu trnh m ho, ch cn thay i th t s dng kho v cc hm
vng tng ng: k
n
, k
n-1
, .., k
1
; F
n
, F
n-1
, .., F
1
.
Nhn xt:
a) u im:
- Cu trc m Feistel trn y rt thun tin cho m ho - gii m m bo tc
nhanh v tin li cho vic cng ho cc chng trnh m ho - gii m khi.
- Cc hm vng F
i
c th c cu trc hon ton ging nhau, tc l F
i
= F, min sao
chng l hm c tnh cht mt m tt, do s thun tin cho thao tc m ho - gii
m.
b) Nhc im:
Qua m hnh cu trc m ho gii m Feistel trn c th thy ngay cc dng
kho coi l yu nh sau (vi gi thit F
i
F):
- Kho yu l cc kho c dng:
k
n
= k
1
;
k
n-1
= k
2
;
k
n-2
= k
3
;
---------
Tc l D(.) = E(.), hay l E
2
= I. Nh vy thm m ch cn m ho chnh bn
m thu c l s c c bn r cn tm.
- Cp kho na yu l cc cp kho c dng:
k
n
(A) = k
1
(B);
k
n-1
(A) = k
2
(B);
k
n-2
(A) = k
3
(B);
----------------
iu ny c ngha l thm m c th dng thao tc m ho ca ngi B gii
m cc bn m ca ngi A v ngc li. Tc l ta c: E
A
= D
B
, v E
B
= D
A
.


16
Tt nhin cc dng kho trn y l khng c php s dng trong cc m
hnh m khi tng ng.
- Trong cu trc Feistel trn mi php lp ch mt na khi vn bn x l c
thay i, iu dn n s cn thit phi tng s lng lp t c bn
vng bo v theo yu cu.
- Khng tn ti cc tiu chun r rng no chn hm F, tuy nhin thng hm
l dy cc thay th phi tuyn ph thuc vo kho, trn ln cc hon v v chuyn
dch.
1.2.4.2. Cu trc cng -nhn
Cu trc cng-nhn c th xem nh l mt trong cc kiu ht nhn cu to nn
cc hm vng, trong hon ton s dng cc php ton s hc tng i n gin
v c chn lc cn thn. Mt s cu trc bin i khc nh cc hp nn, cc php
hon v, cc php dch vng, chng c s dng trong chun m d liu DES,
trong h m d liu Xvit (GOST)... Cu trc cng-nhn c xut bi J. L.
Massey v X. Lai khi h xy dng nn mt chun m d liu mi l PES v sau
c ci tin i tn thnh IDEA. M hnh ca cu trc cng-nhn c th hin
trn hnh 1.5.
U
1
U
2

Z
1
+

+ Z
2

V
1
V
2
Hnh 1.5 : S cu trc cng-nhn.
Trong s trn cc php ton v + l cc php nhn modulo hoc cng
modulo trn cc nhm tng ng vi khng gian u vo ca cc hng t: U
1
, U
2
l
cc vc t u vo, V
1
, V
2
l cc vc t u ra, Z
1
, Z
2
l cc kho.
Theo cc chuyn gia mt m, thc hin bin i theo s cu trc cng-nhn


17
trn y s m bo tnh cht khuych tn tt cho php m ho.
1.2.5. Cc m lp
1.2.5.1. M lp v hm vng
Mt m khi c gi l m lp nu n da trn c s lp mt hm n gin f
mt vi ln nh m t trong hnh 1.6 mi php lp c gi l mt vng. u vo
ca mi vng l hm ca u ra ca vng trc v ca mt kha con c thit
k t kha b mt y bi mt lc to kha. Mt m khi kha b mt nh
th vi r-php lp c gi l mt m lp r-vng. Hm f c gi l hm vng. V
d: DES l mt m lp 16-vng.
Phng php lp c s dng trong thit k m khi l do n bao hm tt c
cc nguyn l thit k c bn nu trn. Mt hm vng n gin c th c ng
dng hiu qu, trong khi php lp ca mt hm vng c chn hp l c th cung
cp mo v khuych tn cn thit. Cc chuyn gia v mt m ch ra rng trong
thm vi sai i vi mt m Markov phc tp d liu ca tn cng ny s tng
theo hm m vi s vng lp trong khi phc tp ng dng ch tng c tuyn tnh.
Z
Y(r)
Y(r-1)
Y(2) Y(1) Y(0)=X
f
Lc to kho
ff f
Z
(3)
Z
(2)
Z
(1)
Hnh 1.6: Mt m lp r vng vi hm vng f
1.2.5.2. Cu trc ca m lp tng t E/D
Trong thc t, hu ht cc xut m khi u tun th qui tc bt thnh vn
l nn cu trc h m sao cho thun tin cho qu trnh m ho - gii m. Cu trc
Feistel l mt trong nhng kiu c cu trc tng t E/D. Qu trnh gii m hon


18
ton ging nh qu trnh m ho, ch khc l dng cc kho con vi th t ngc
li. Gn tng t nh th, l h m IDEA cng c cu trc kiu tng t E/D.
1.2.6. an ton ca cc h m khi
Trong m hnh h mt kho b mt hnh 1.3 mt m khi c s dng nhm
bo v chng s d d khng mong mun ca bn r. Nhim v ca thm m l ph
h m ny theo ngha h c th m ra c cc bn r t cc bn m chn bt c.
Theo [1],[2],[7] mt h m l b ph hon ton nu nh thm m c th xc nh
c kha b mt ang s dng v t h c th c c tt c cc thng bo mt
cch d dng nh l mt ngi dng hp php. Mt h m l b ph thc t nu
thm m c th thng xuyn m ra c cc bn r t cc bn m nhn c,
nhng vn cha tm ra c kha.
an ton lun gn vi cc e da tn cng. Chng ta gi s rng k tn cng
lun c th truy nhp ti mi th c truyn thng qua knh khng an ton. Tuy
nhin, c th c cc thng tin khc i vi thm m. Kh nng tnh ton ca thm
m phi lun c xem xt trc khi xem xt an ton ca mt m c th b truy
nhp.
Mt gi thit c chp nhn ph bin nht trong mt m l thm m i
phng lun c th truy nhp hon ton ti cc bn m c truyn trn knh khng
an ton.
Mt gi thit c chp nhn khc na l:
Gi thit Kerckhoff: Thm m i phng l c bit ton b chi tit ca
qu trnh m ha v gii m ch tr gi tr kha b mt.
Gi thit Kerckhoff suy ra rng an ton ca mt h mt kha b mt ch
cn ph thuc vo chnh kha mt m thi. Di gi thit Kerckhoff, cc tn cng
c th c phn loi theo cc tri thc ca thm m nh sau:
- Tn cng ch bit bn m: Thm m i phng khng bit thm t thng tin
g ngoi bn m nhn c.
- Tn cng bn r bit: Thm m i phng bit thm mt vi cp R/M
i vi kha ang dng.
- Tn cng bn r la chn: Thm m i phng c th t c cc bn m


19
tng ng vi cc bn r n nh c bit bt k i vi kha ang dng.
Tn cng bn r la chn l tn cng mnh nht trong cc tn cng trn. Nu
mt h m l an ton chng li tn cng bn r la chn th n cng an ton trc
cc tn cng khc. Trong thc t, nn dng h m c an ton chng li tn cng
bn r la chn, ngay c khi thm m i phng him c c hi thu lm c
thng tin g hn so vi tn cng ch bit bn m.
1.3. Gii thiu mt s k thut m khi.
1.3.1. Chun m d liu DES
M t y ca DES (Data Encryption Standard) c nu trong Cng b s
46-2 v cc chun x l thng tin Lin bang (M) vo 15.1.1977. Chun m d liu
DES l mt k thut m khi c cu trc dng Feistel, thc hin m ho mt xu bt
x ca bn r di 64 bng mt kho 56 bt. Bn m nhn c cng l mt xu bt
c di 64. M t mc cao v h thng nh sau: (M t chi tit ca DES s c
trnh by trong chng 3 ca lun vn):
Thut ton tin hnh theo 3 giai on:
1. Vi bn r cho trc x, mt xu bt x
0
s c xy dng bng cch hon v
cc bt ca x theo php hon v c nh ban u IP. Ta vit: x
0
= IP(X) = L
0
R
0
, trong
L
0
gm 32 bt u v R
0
l 32 bt cui.
2. Sau tnh ton 16 ln lp theo mt hm xc nh. Ta s tnh L
i
R
i
, 1 i
16 theo quy tc sau:
L
i
= R
i-1
R
i
= L
i-1
f(R
i-1
,K
i
)
trong k hiu php hoc loi tr ca hai xu bt (cng theo modulo 2). f l mt
hm bao gm cc php hon v, php th, php cng modulo 2, cn K
1
, K
2
, . . . , K
16

l cc xu bt di 48 c tnh nh hm ca kho K (trn thc t mi K
i
l mt
php chn hon v bt trong K). K
1
, . . ., K
16
s to thnh bng kho. Mt vng ca
php m ho c m t trn hnh 1.7.
3. p dng php hon v FP

cho xu bt R
16
L
16
, ta thu c bn m y. Tc l
y= FP

(R
16
L
16
). Hy ch th t o ca L
16
v R
16


20
L
i-1
R
i-1

F
K
i
+
L
i
R
i

Hnh 1.7: M t mt vng ca DES
Php gii m c thc hin nh dng cng thut ton nh php m nu u
vo l y nhng dng bng kho theo th t ngc li K
16
,,K
1
. u ra ca thut
ton s l bn r x.
1.3.2. Chun m d liu X vit
M t chi tit ca thut ton m ho X vit (GOST) c cng b trong
GOST 28147-89. Thut ton GOST l mt v d ca h mt kiu DES cng vi lch
trnh kho c n gin ho ti a, l mt trong nhng kiu c trng ca h m
khi s dng cu trc Feistel vi ht nhn l cc hp th, php dch vng, kt hp
vi cc php ton s hc nh php XOR v php cng mdulo. M hnh m ho -
gii m d liu ca GOST cng gn tng t nh DES, tuy nhin n m bn r c
di 64 bt thnh bn m c di 64 bit kha c di 256 bit.
M t thut ton GOST nh sau:
Thut ton GOST gm 32 vng lp. Mi vng lp c ch ra hnh 1.8. C
hai phn t l b mt trong thut ton ny: kha m K c di 256-bit v nh
ngha cc S-box S
1
,, S
8
.
Kha mt m K= (K
0
, , K
7
) c lu tr trong thit b lu tr kha (key
storage unit-KSU) nh mt dy ca 8 t 32-bit (K
0
, , K
7
). Mi t kho 32-bit K
i



21
c gi l kha thnh phn (i=0,,7). m mt vn bn 64-bit, trc ht n
c chia thnh 2 na 32-bit v c t vo thanh ghi 32-bit R
1
v R
2
. Ni dung
ca thanh ghi R
1
c cng theo modulo 2
32
vo thnh kha thnh phn K
0
(b cng
CM
1
), tc l R
1+
K
0
(mod 2
32
). Dy thu c 32 bit c chia thnh 8 khi 4 bit, 8
khi 4 bit ny l u vo ca 8 S-box tng ng S
1
,, S
8
. Mi S
i
, i=1,,8 l mt
R
2
R
1
+
S
1
.. S
8
R
+
R
1
R
2
K
0


K
7
CM
2
K S
CM
1
KSU


Hnh 1.8: S mt vng lp ca GOST
php hon v. 8 u ra 4-bit ca cc S-box c lu vo thanh ghi dch R, ni dung
ca thanh ny c dch tri 11 bit (v pha bit bc cao). Ni dung ca thanh R by
gi c cng modulo 2 (Exclusive-Or hoc XOR) vi ni dung ca thanh ghi R
2
bng b cng CM
2
. Ni dung t s c lu trong R
1
v gi tr c ca R
1
c lu
tr trong R
2
v n y kt thc vng lp th nht.
Cc vng lp khc tng t nh vng lp th nht. Trong vng lp th hai,
chng ta s dng kha K
1
t KSU. Cc vng lp th 3, 4, 5, 6, 7, 8 s dng tng
ng cc kho thnh phn K
2
, K
3
, , K
7
. Cc vng lp t 9 n 16 v t 17 n 24
cng s dng cc kho thnh phn ny. Cc vng lp t 25 n 32 s dng cc kho
thnh phn theo th t ngc li, tc l vng lp th 25 s dng kha K
7
, vng lp


22
th 26 s dng kha K
6
v c tip tc nh vy. Vng lp cui cng dng kha K
0
.
Cho nn th t ca cc kha thnh phn trong 32 vng lp l:
K
0
,., K
7
, K
0
,., K
7
, K
0
,., K
7
, K
7
,., K
0
.
Sau 32 vng lp, u ra t b cng CM
2
c t trong R
2
, cn R
1
gi nguyn
gi tr c. Ni dung ca thanh ghi R
1
v R
2
l bn m 64-bit cho bn r c 64-bit.
1.3.3. Thut ton m ho d liu IDEA
Thut ton IDEA (International Data Encryption Algorithm) [2],[7] c pht
trin bi Xuejia Lai & James Massey ca vin Cng ngh Thy s. IDEA c cu trc
mt phn ca cu trc Feistel, thc hin m ho mt xu bt x ca bn r di 64
bng mt kho 128 bt, bn m nhn c cng l mt xu bt c di 64.
Cc php ton s dng trong IDEA
- Php XOR, k hiu l
- Php cng cc s nguyn module 2
16
(modulo 65536) vi d liu vo v ra l
cc s nguyn khng du 16 bit. K hiu php ton l
- Php nhn cc s nguyn modulo 2
16
+1 (modulo 65537) vi d liu vo v ra
l cc s nguyn 16 bit khng du, ngoi tr mt khi gm tt c cc bit 0 c coi
nh biu din 2
16
. K hiu php ton l
1.3.3.1. Qu trnh m ho ca IDEA.
Theo cch thit k ca thut ton, mi bit u ra ca vng u tin ph thuc
vo mi bt ca 64bit u vo r v mi bt ca kho con. Ton b thut ton c 8
khi lp, mi khi lp li c 4 vng lp con theo cu trc cng/nhn (Addition &
Multiplication - MA).
u vo r 64 bit c chia thnh 4 b 16 bit (X
1
,X
2
,X
3
,X
4
) lm u vo ca
khi lp s 1 thc hin theo MA vi 6 khi kha con ca kha u vo (mi khi
kha con 16 bit). Cc khi tip theo, ly u ra ca khi trc lm u vo v tip
tc thc hin theo MA vi 6 khi kha con k tip. Cui cng l mt hm bin i
u ra dng 4 kho con cn li, ti y 4 khi 16 bit c kt hp to thnh u ra
m 64 bt.

Hnh 1.10 m t hot ng ca vng u tin, cu trc cc vng sau u ging


23
vng trc. Vng lp bt u bng mt php bin i kt hp 4 khi con u vo vi
4 kho con theo MA. Bn khi ra ca php bin i ny c kt hp bng php
XOR to thnh hai khi 16 bit l u vo ca cu trc MA. Cu trc MA ly hai
kho con nh u vo v kt hp cc u vo cho hai khi 16 bit u ra. Cui
cng 4 khi u ra t php bin i trn c kt hp vi hai khi u vo ca cu
trc MA dng php XOR to ra bn khi u vo cho vng tip theo.
Hai u vo c sinh ra bi cc u vo th hai v th ba (x2 v x3) c tro
i to ra cc u ra th hai v th ba (w12 v w13). iu ny lm tng kh
nng trn gia cc bit c x l v to cho thut ton chu c cc phn tch m
khc nhau.
128 bit key Z
y1
x1 x4 x3 x2
Vng 1
z1
z6
w11 w12 w13 w14
Vng 2
z7
z12
w71 w72 w73 w74
Vng 8
z43
z48
w81 w82 w83 w84
Bin i ra
z49
z52
y4 y3 y2

z1
16
z52
16
B sinh kha con
64 bt m
64 bit r X
Hnh 1.9: S cu trc ca IDEA
Ch : Giai on th chn c tn l giai on bin i ra (hnh 1.11). N c
cng cu trc nh cc vng trn. Ch khc l u vo th hai, th ba c tro i
trc khi tham gia vo cc php ton php dch c cng cu trc nh php m.
1.3.3.2. Sinh kho con.
52 kho ph ly t 128 bit kho chnh. Tm kho ph u c nhn Z
1
,Z
2
,...,Z
8
,
vi kho Z
1
gm 16 bit u, kho Z
2
tng ng 16 bit k tip, cho n kho Z
8
tng



24

z2
z1
x1 x2 x3 x4
z3
z4
z5
z6

Hnh 1.10: Chi tit mi vng n
ca IDEA



w82 w81 w83 w84
z49 z50 z51 z52
y1 y2 y3 y4
Hnh 1.11: Php bin i ra ca
qu trnh m ho IDEA

ng 16 bit cui. Sau dch tri 25 bt v 8 kho con tip theo c trch ra. Th tc
s thc hin lp li cho n khi 52 kho con c sinh ra. S ny cung cp mt
k thut hiu qu cho vic thay i cc bit kho c dng cho cc kho con trong 8
vng lp ca m IDEA.
1.3.3.3. Qu trnh gii m ca IDEA
Qu trnh gii m c bn ging nh qu trnh m ho, bn m lm d liu vo
nhng vi kho con khc. Cc kho con gii m U
1
,U
2
,...,U
52
nhn c t cc kho
con m ho nh sau: Bn kho con u tin ca vng dch th i c nhn t bn
kho con u tin ca vng m ho (10-i). Trong giai on bin i ra c coi
nh vng th 9. Cc kho con dch th nht v th t l nghch o ca php nhn


25
modulo (2
16
+1) ca kho con m ho th nht v th 4. Vi cc vng th 2 n th
8, kho con gii m th 2 v 3 l nghch o ca php cng module (2
16
) ca cc
kho con m tng ng th 3 v th 2. Vi cc vng th nht v th 9, cc kho con
gii m th 2 v 3 l nghch o ca php cng module (2
16
) ca cc kho con m
ho tng ng th 2 v th 3.
Vi tm vng u tin, hai kho con cui cng ca vng gii m th i l hai
kho con cui cng ca vng m ho th (9-i).
1.3.4. Cc ch hot ng ca m khi
m ho bn r di tu , cc m khi c th c s dng 4 ch
lm vic thng gp nht trong cc h thng mt m bo v thng tin:
- Ch sch m in t (ECB-Electronic Code Book).
- Ch phn hi m (CFB-Cipher Feed Back).
- Ch lin kt khi m (CBC-Cipher Block Chaining)
- Ch phn hi u ra (OFB-Output Feed Back).
Ch ECB tng ng vi cch dng thng thng ca m khi: vi mt dy
cc khi bn r cho trc x
1
,x
2
,. . .( mi khi c 64 bt), mi x
j
s c m ho bng
cng mt kho K to thnh mt chui cc khi bn m c
1
c
2
... theo quy tc c
j
=
e
K
(c
j-1
x
j
) j 1.
Trong cc ch OFB v CFB dng kho c to ra s c cng mod 2 vi
bn r (tc l n hot ng nh mt h m dng). Ch OFB thc s l mt h m
dng ng b: dng kho c to bi vic m lp vc t khi to 64 bt (vc t IV).
Ta xc nh I
1
=IV v ri tnh dng kho O
1
O
2
. . . theo quy tc O
j
= e
K
(O
j-1
), j 1.
Dy bn r x
1
x
2
. . . x
j
sau s c m ho bng cch tnh c
j
= x
j
O
j
,j 1.
Trong ch CFB, bt u vi I
1
= IV (l mt vc t khi to 64 bt) v to
phn t O
j
ca dng kho bng cch m ho khi bn m trc . Tc O
j
= e
K
(c
j-1
),
j 1, cng nh trong ch OFB: c
j
= x
j
O
j
, j 1. Vic s dng CFB c m t
trn hnh 1.12c (ch rng hm m E
K
c dng cho c php m v php gii m
cc ch CFB v OFB).
Cng cn mt s bin tu ca OFB v CFB c gi l cc ch phn hi K
bt (1 < K < 64 ). y ta m t cc ch phn hi 64 bt. Cc ch phn hi


26
1 bt v 8 bt thng c dng trong thc t cho php m ho ng thi 1 bit (hoc
byte) s liu.
Bn ch cng tc c nhng u, nhc im khc nhau. ch ECB v
OFB, s thay i ca mt khi bn r x
j
64 bt s lm thay i khi bn m c
j
tng
ng, nhng cc khi bn m khc khng b nh hng. Cc ch CBC v CFB,
nu mt khi bn r x
j
b thay i th c
j
v tt c cc khi bn m tip theo s bi nh
hng. Nh vy cc ch CBC v CFB c th c s dng rt hiu qu cho mc
ch xc thc.

a) Ch sch m in t (ECB)
b) Ch lin kt khi m (CBC)


27

c) Ch phn hi m (CFB)







d) Ch phn hi u ra (OFB)

Hnh 1.12: Cc ch hot ng ca m khi



28
1.3.5. Mt s gii php k thut thit k m khi.
Vic thit k cc thut ton m khi trong thit b bo mt thng tin hin nay
c th thc hin theo cc k thut nh m t trong hnh 1.13
Thut ton m khi

ASIC FPGA
Inter,
RISC
DSP, P,
Smart card
Phn cng
Phn mm

Hnh 1.13: Cc k thut thit k m khi.
1.3.5.1. Thit k m khi bng chng trnh phn mm
Thit k thut ton m khi bng chng trnh phn mm v thc hin trn cc
b x l Intel, RISC hoc nhng trong mi trng DSP, Smart-Card..., hoc trn cc
my PC. u im ca k thut ny l khng ph thuc qu nhiu vo cng ngh
thit k, cho php thit k nhanh, c tnh mm do cao khi cn thay i thut ton
m ho c thc hin mt cch n gin. Tuy nhin k thut ny li b hn ch v
mt tc x l m ho - gii m, n ph hp vi nhng h thng truyn tin c tc
khng cao. Mt khc, vic s dng khng ht cc tnh nng ca mt thit b sn
c lm cho gi thnh tng ln, v khng thun li cho chuyn dng ho thit b bo
mt thng tin.


29
1.3.5.2. Thit k m khi bng cng c phn cng
Phn ln cc k thut m khi thng dng hin nay ang c dng bo
mt thng tin trong cc h truyn tin mt l c cu trc Feistel nh trnh by
trong phn 1.2.4, y l mt cu trc m khi rt thch hp cho vic thit k bng
phn cng. Tuy thit k thut ton m khi trn cc cng c phn cng khng mm
do bng phn mm nhng n li c mt s u im: Ti cng mt thi im cc
thit b phn cng cho php thay i cc php x l d liu mt cch linh hot hn
so vi phn mm. Tc x l d liu v an ton v mt vt l cao hn, bo mt
c thit k, khng ph thuc vo h iu hnh, rt thch hp trong vic thit k
nhng thit b bo mt chuyn dng v bo mt trong cc h thng truyn tin c tc
cao.
Trn th gii mt s hng sn xut cc thit b bo mt cng nghin cu
thit k cc thut ton m khi bng cc cng c phn cng nh: cng ngh ASIC,
cng ngh FPGA...,
Cng ngh ASIC cho php thit k thut ton m khi vi hu ht cc u im
ca gii php phn cng, v theo [18] tc m ho - gii m d liu khi thit k
thut ton m khi bng cng ngh ASIC c th ln ti vi Gigabt/s. Tuy nhin
thit k mt ng dng trn ASIC i hi phi u t dy chuyn cng ngh vi chi
ph kh ln c bit l khu ng chp. Ti Vit nam hin nay cc ng dng c
thit k trn ASIC sau khi thit k, kim tra v th nghim bng cc cng c dng
cho thit k th khu ng chp thng c t hng bi mt nh sn xut thit b
nc ngoi.
Cng ngh FPGA l mt s pht trin ca cng ngh ASIC, tuy tc x l d
liu c thp hn mt cht nhng n tha hng c nhng tnh nng u vit,
khc phc c mt hn ch ca ASIC. Ngi thit k s dng phn mm tin
hnh thit k vi cc phn t logic c bn v to cc gin kt ni. FPGA l mt
thit b logic c th c ngi s dng lp trnh trc tip m khng phi s dng
bt k mt cng c ch to mch tch hp no. iu ny cho php ch to ngay
thit b v v vy gi thnh sn phm thp.
FPGA c ng dng rng ri v kh l tng v chng c mc tch hp cao


30
trn chip, p ng yu cu phc tp v a dng. Thay v cc IC nguyn mu lp
ghp vo h thng ngi thit k c th to cc kt ni theo cc phn trong FPGA
ca mnh bng phn mm. Mt khc chng ta c th np li chng trnh mt cch
lin tc thay i cc thut ton m khi hoc thc hin cc thut ton khc.
1.3.5.3. La chn gii php thit k modul m khi Vit nam
Vit Nam hin nay cc thut ton m khi ch yu c thit k bng cc
chng trnh phn mm chy trn my PC, vic nghin cu c th cng ho cc
thut ton m khi trn cc cng c phn cng nhm p ng cc yu cu v tc
x l d liu, tnh ch ng, chuyn dng ho thit b bo mt cng nh gi thnh l
mt hng nghin cu mi.
Cng ngh FPGA vi nhng tnh nng u vit ca n c la chn nghin
cu thit k modul m khi nhm p ng nhng yu cu trn l mt s p dng,
nghin cu ph hp vi iu kin thc t v cng ngh v yu cu s dng Vit
Nam .
1.4. Kt lun chng 1
Trong bi cnh cnh tranh quyt lit gia cc t chc chnh tr x hi, cc cng
ty, cc quc gia... v s pht trin mnh m ca cc h thng vin thng nh hin
nay th vn bo mt v an ton thng tin rt quan trng, gii quyt vn ny
cn phi c cc phng php m ho-gii m ca mt m hin i.
Trong chng ny m t mt cch khi qut v m hnh ca mt h truyn
tin mt. Trnh by cc khi nim c bn v mt m t mt m c in cho n mt
m hin i (h mt kho b mt v h mt kho cng khai) v phn tch u, nhc
im ca mi h mt. ng thi trnh by mt s vn c s l thuyt v m
khi, mt s k thut m khi hin nay ang c ng dng trong cc h truyn tin
mt v vic la chn h m khi bo mt cho cc h truyn tin c tc cao bi
l:
M ha kha cng khai thng c tc rt chm so vi m ha kha b mt
ni chung v m khi ni ring (RSA modulo 1024bits c tc [1] bng 1/1500 ln
ca DES-16). Do vi cc ng dng i hi tc m ha cao nh m ha knh


31
truyn, thng tin trn mng (m bo trc tuyn v thi gian thc) th mt m
kha cng khai kh c th p ng c, tuy nhin vai tr chnh ca n l cc
khu xc thc, phn phi v tha thun kha cho mt s h m khi. Trong khi
m khi c th t c tc m ho d liu rt cao khi n c thit k cng ho
theo dng modul trn mt s cng c thit k phn cng nh cng ngh FPGA s
c cp ti chng 2 .


32
Chng 2
cng ngh fpga v ngn ng m t
phn cng vhdl

2.1. tng quan v cng ngh FPGA
2.1.1. Gii thiu v cng ngh FPGA
Cng ngh ch to mch vi in t ngy nay ang c mt s thay i ln: t
mt mch tnh hp vi in t vi c s thit b cng ngh tin tin ch to ra vi s
lng ln chuyn dn sang cc mch chuyn dng sn xut vi l nh ti cc c s
c iu kin cng ngh cha pht trin. S thay i c hnh thnh nh cc
cng c thit k t ng. ng lc chnh ca qu trnh thay i ny l gim thi
gian thit k, ch to vi mch v tng tnh linh hot cho ngi thit k lp trnh vi
nhng ng dng ring bit.
FPGA (Field-Programmable Gate Array), l mch tch hp c ln trong
cho php ngi lp trnh thay i cc thit k ca mnh m khng phi s dng bt
k mt cng c ch to mch tch hp no. FPGA l cng ngh tin tin nht hin
nay ca ngnh cng ngh ch to IC (Integrated Circuit) chuyn bit.
2.1.1.1. S pht trin ca cc thit b lp trnh c
Cc thit b lp trnh c ng vai tr quan trng lu di trong thit k cc vi
mch vi nhng ng dng ring bit trong ngnh in t-vin thng. Chng l cc
chp a dng c th c cu hnh theo nhiu cch cho ng dng. Loi u tin ca
thit b lp trnh c s dng rng ri l PROM (Programmable Read Only
Memory). PROM l thit b lp trnh ch c mt ln gm mt dy cc nh ch
c.
C hai loi PROM c bn, mt loi ch c th lp trnh bi nh sn xut gi l
mask programmable v mt loi c th lp trnh bi ngi s dng gi l field
programmable. Cc chp mask programmable c tc lm vic cao v cc kt ni
bn trong thit b c thc hin bng phn cng ngay t khi sn xut. Ngc li,


33
cc kt ni ca field programmable lun cn n mt s loi chuyn mch lp trnh
c (cu ch, transistos truyn...) v vy tc chm hn kt ni cng. Tuy nhin,
thit b field programmable c nhiu u im gi tr hn l s hn ch v tc nh:
- Cc chp field programmable r hn cc chp mask programmable khi sn
xut vi s lng nh.
- Cc chp field programmable c th lp trnh tc th trong mt thi gian rt
ngn, trong khi cc chp mask programmable khi sn xut phi mt hng thng.
Hai bin th ca PROM l EPROM (Erasable Programmable Read Only
Memory) v EEPROM (Electrically Erasable Programmable Read Only Memory)
chng iu c chung mt u im l c th xo v lp trnh nhiu ln.
Mt loi thit b lp trnh c khc c thit k c bit th hin cc
mch lgc l PLD (Programmable Logic Device): Mt PLD thng thng gm mt
dy cc cng AND c ni vi mt dy cc cng OR. Loi c bn nht ca PLD l
PAL (Programmable Array Logic). PAL gm mt khi cc cng AND lp trnh
c ni n mt khi cc cng OR c nh. Mt loi PLD khc linh hot hn l
PLA (Programmable Logic Array) cng c cu trc ging PAL nhng tt c cc kt
ni l lp trnh c.

Hnh 2.1: Cu trc ca PLA Hnh 2.2: Cu trc ca PAL
Cu trc ny c cc mt li ca cc ng ni theo chiu ngang v chiu
ng. Ti mi im giao nhau l mt cu tr, vi s tr gip ca cc cng c phn
mm , ngi thit k c th la chn mi ni no khng c ni th hu cu tr m
khng cn dng i (nung nng v thi t cu tr ). iu ny c thc hin
bi mt b np chng trnh.


34
Theo hnh 2.2 cc chn u vo c ni vo cc ng theo chiu ng, cc
ng nm ngang c ni vi cc cng AND - OR, ln lt cc ng ny c
ni vi cc Flip - Flop (nh: D, T, RS).
C hai loi PAL v PLA cho php thc hin cc mch lgc tc cao, tuy
nhin cu trc n gin ca chng ch cho php thc hin cc mch l gc c nh.
thc thi cc mch yu cu nhiu u vo v nhiu u ra c nhiu chp tinh
vi hn gi l thit b lgc lp trnh phc hp CPLD (Complex Programmable Logic
Devices), h ny l kt qu ca vic tng mt ca h PLDs ln nhiu ln . Khi
nim ny c hiu l c mt s khi PLD hoc cc macrocell (t bo v m)
trong mt thit b n cng vi cc ng ni lin a nng gia chng. Cc ng
ni ca cc n v logic n gin c th c thc thi trong mt khi n. Nhiu
n v logic phc tp yu cu nhiu khi v s dng cc ng ni a nng gia
chng to nn cc kt ni phc tp hn.


Hnh 2.3: Cu trc ca CPLD
Cc CPLDs cc k thch hp trong vic m t cc cng logic phc tp vi tc
ln 200 Mhz. Khun mu thi gian cho CPLD rt d tnh ton, bi th trc khi
bt u thit k chng ta c th tnh ton cc tc t u vo n u ra ca mnh
da trn khun mu ny. CPLDs a ra cch n gin nht thc hin mt thit
k, mt thit k c th c m t bi cc s hoc bng mt ngn ng m t
phn cng, n gin khi s dng cc cng c pht trin ti u ho, np v m


35
phng thit k. Cc cng c thit k to ra mt file chng trnh m file ny c
dng a cc chun logic vo trong mt chip CPLD cng vi chc nng mong
mun. Gi s nu cn c mt mt s thay i v thit k, chng ta c th a s
thay i thit k vo trong cng c pht trin CPLD v thc thi trn n sau c
th kim tra li ngay thit k. CPLD c mc tch hp rt cao v c ng gi trong
mt khun dng rt nh. iu ny cung cp mt gii php tuyt vi cho nhng
ngi thit k cn sn phm ca mnh c ng gi nh gn vi din tch bo mch
b gii hn v khong khng.
FPGA (mng cng c th lp trnh c theo hng) c cng ty Xilinx gii
thiu ln u vo nm 1985 nhm to ra mt thit b lp trnh c mt tch hp
cao. K t cho n nay c rt nhiu cc hng thit k v cung cp cc loi FPGA
nh Xilinx, Altera, Actel, Plus Logic
2.1.1.2. Cu trc c bn ca FPGA
FPGA gm mt dy cc phn t ri rc c th c kt ni vi nhau bng cc
ngun kt ni chung. Cc kt ni gia cc phn t c th lp trnh c. Hnh 2.4
gii thiu v m hnh tng qut ca mt FPGA. N gm dy 2 chiu cc logic block
c th c kt ni bng cc ngun kt ni chung. Ngun kt ni l cc on dy
(segment) c th c chiu di khc nhau, bn trong cc kt ni l cc chuyn mch
lp trnh c dng ni cc logic block vi cc segment hoc gia cc segment
vi nhau. Mch lgc c ci t trong FPGA bng cch nh x lgc vo cc logic
block ring r v sau ni cc logic block cn thit qua cc chuyn mch. Trong
c cc khi:
- Cc khi logic (logic block): cu trc v ni dung ca logic block c gi l
kin trc ca n. Kin trc ca khi logic c th c thit k theo nhiu cch khc
nhau. Mt s khi logic c th ch l cc cng NAND 2 u vo, tuy nhin cng c
th n l mt b dn knh (multiplexer), hay cc bng tm kim LUT (Luck-Up
Table). Trong mt s loi FPGA cc khi logic c th c cu trc hon ton ging
nh PAL. Hu ht cc khi logic cha mt s loi flip-flop h tr cho vic thc
hin cc mch tun t.
- Cc ngun ti nguyn kt ni: Cu trc v ni dung ca cc ngun kt ni


36
trong FPGA c gi l kin trc routing (routing architecture). Kin trc routing
gm cc on dy ni v cc chuyn mch lp trnh c. Cc chuyn mch lp
trnh c c th c nhiu cu to khc nhau. Ging nh khi logic, c nhiu cch
thit k kin trc routing nh : Transitor truyn (pass - transitor) c iu khin
bi cell SRAM, cu ch nghch (anti - fuse), EPROM transitor v EEPROM
transitor...


Logic
Block
Ti nguyn
kt ni
I/O Cell










Hnh 2.4: M t m hnh ca mt FPGA.
- Cc cng vo/ra: Cc c tnh I/OB ca cc u vo v u ra c h tr ti
19 cc chun tn hiu khc nhau bao gm: LVDS, BLVDS, LVPECL, LVCMOS,
HSTL, SSTL v GTL.
Cc khi c bn ca LB (Logic Block) ca FPGA chnh l Logic Cell (LC: gi
l t bo logic).
- Mi mt Logic Cell bao gm mt b to chc nng (hay b to hm) 4 u vo,
logic nh v phn t lu tr (Flip-Flop loi D). u ra b to chc nng ca mi
Logic Cell iu khin c u ra LB hoc u vo D ca Flip-Flop. Mi mt LB c
cha bn Logic Cell v c t chc thnh hai Slice tng t nhau, mt slice n c
dng nh hnh 2.5.
- Look-Up Tables (LUT): Cc b to chc nng ca FPGA thc hin nh LUT c


37
bn u vo. hot ng nh mt b to chc nng, mi mt LUT c th cung cp
mt RAM 16x1bit ng b. Hn na hai LUT trong mt Slice c th c kt hp
to RAM 16x2 bit hoc 32x1 bit ng b .
- Storage Element: Cc phn t lu tr trong slice ca FPGA c th c xp t
nh mt Flip-Flop loi D kch hot bng sn, hoc nh mt b cht nhy mc. Cc
u vo D c th c iu khin hoc bi b to chc nng trong slice hoc trc
tip t u vo cc slice (b qua b to chc nng). Thm cc ng Clock (CLK)
v Clock Enable(CE) (hnh 2.5), mi Slice c cc tn hiu Set

Hnh 2.5: Cu trc Logic Cell trong FPGA
v Reset ng b (SR v BY). ng SR p cc phn t lu tr v trng thi khi
to, c bit trong trng hp nhi cu hnh. ng BY p phn t lu tr v trng
thi ngc li. Nh c la chn hai ng ny c th c xp xp hot


38
ng khng ng b. Tt c cc tn hiu iu khin c th o ngc mt cch hon
ton c lp v chng c chia s bi hai Flip - Flop trong mt Slice.
- Block RAM: Trong FPGA hp nht mt vi b nh RAM theo khi thnh khi
ln hn (gi l SelectRAM +), iu ny cn b xung cc LUT RAM c phn
phi v kin trc b nh khng bn vng ny c thc hin trong cc LB, cc khi
b nh Block RAM c t chc theo cc ct.
Mt FPGA c cu trc ca cc Logic Cell (hoc cc module) v cc ng ni
(hnh 2.6), m cc ng ni ny nm di s iu khin ca ngi thit k. C
ngha l chng ta c th thit k, lp trnh v thay i mch khi mun. Vi h FPGA
ngy nay vt qua gii hn 10 triu cng.

Hnh 2.6: Cu trc ca FPGA
2.1.1.3. Phn loi FPGA
C nhiu loi FPGA ca cc nh sn xut khc nhau, tuy nhin chng c th
c chia thnh 4 loi chnh nh hnh 2.7.
Cu trc mng i xng (symmetrical array), cu trc hng (row-based), cu
trc PLD phn cp (hierachical PLD), cu trc a cng (sea-of-gate)
Xt v mt s dng c hai loi linh kin cu hnh cho cc kt ni ca FPGA :
Loi SRAM (Static Random Access Memory) c th lp trnh li nhiu ln v loi
OTP (One - Time Programmable) lp trnh mt ln. Hai loi ny khc nhau ch
thc thi ca logic cell v k thut to s kt ni trong thit b.


39
Cu trc hng Mng i xng
Ni kt



Logic Block







Cu trc a cng
(Kt ni ph ln Logic Block)
Logic Block



Ni kt
Cu trc PLD phn cp

PLD
Block

Hnh 2.7: Bn loi FPGA in hnh
Kiu hay c dng hn c l kiu SRAM v n c th lp trnh c nhiu
ln. Thc t th SRAM FPGA c np chng trnh li mi khi bt ngun, bi v
FPGA loi ny thc cht l mt chp nh theo mun. Vy ti sao li cn mt chip
PROM ni tip hoc b nh h thng cng vi mi SRAM FPGA. Cu trc ca hai
loi c th hin trong hnh 2.8 v 2.9.

Hnh 2.8: Cu trc SRAM FPGA (SRAM Logic Cell)


40
- Loi SRAM c th lp trnh li :
+ SRAM xc nh cc ng ni.
+ SRAM xc nh n v logic trong bng tra LUT.

Hnh 2.9: Cu trc ca OTP FPGA (OTP Logic Cell)
- Loi OTP cho php lp trnh mt ln :
+ Cc ng ni khng c php ni nh dng cu ch.
+ Logic l cc cng truyn thng.
Trong SRAM Logic Cell, thay v cc cng thng thng, mt bng tra LUT
xc nh u ra da vo gi tr ca cc u vo.
Trong OTP FPGAs s dng kt ni gia cc ng theo dng ni ngc (c
ngha ngc vi cu tr, s kt ni c to ra v khng b nng chy trong sut thi
gian np chng trnh) to ra cc kt ni c nh trong chip. Hn na, OTP
FPGA khng cn SPROM no khc, iu c ngha l np chng trnh vo thng
FPGA. Tuy nhin mi ln thay i mt thit k phi vt b i mt chip. Loi OTP
Logic Cell tng t nh h PLD vi cc cng v flip-flop nh D, T, hay RS .
2.1.1.4. ng dng ca FPGA
FPGA c th s dng trong hu ht cc ng dng hin ang dng CPLD, PLD
v cc mch tch hp nh. Di y l cc ng dng in hnh ca FPGA:
1. Cc mch tch hp ng dng c bit: FPGA l mt phng tin tng qut
nht thc hin cc mch logic s.
2. Thit k mch ngu nhin: Mch logic ngu nhin thng c thc hin


41
bng PAL. Nu tc ca mch khng i hi kht khe th mch c th thc hin
thay th bng FPGA.
3. Thay th cc chp tch hp nh cho mch ngu nhin: Cc mch trong cc
sn phm thng mi thng cha nhiu chp SSI (Small Scale Integrated). Trong
nhiu trng hp cc chip SSI ny c th c thay th bng FPGA v kt qu l
gim din tch ca bo mch i ng k.
4. Ch to mu: FPGA rt l tng cho cc ng dng to sn phm mu. Gi
thnh thc hin thp, thi gian ngn.
5. My tnh da trn FPGA: Mt loi my tnh mi c th c ch to vi cc
FPGA c th ti lp trnh ngay trn mch FPGA. Cc my ny c mt bo mch cha
cc FPGA m cc chn ni vi cc chip ln cn ging nh thng thng.
2.1.2. Qu trnh thit k c bn trn FPGA
2.1.2.1. Gii thiu v qu trnh thit k
Qu trnh thit k trn FPGA s dng h thng CAD (Computer Aided
Design). Hnh 2.10 biu din cc bc trong h thng CAD tiu biu to ra mt
mch FPGA. T trn hnh v ta thy, im bt u cho mch thit k l mch lgic
ban u. Bc ny cn mt s biu din mch, hay mt m t VHDL hoc mt
c t cc biu thc Boolean. T cc u vo nh vy, chng c chuyn thnh
dng chun nh l cc biu thc Boolean. Cc biu thc Boolean ny c x l
bng cng c ti u lgc (rt gn cc biu thc), mc ch ca vic ny l ti u
v din tch v tc ca mch thit k. Sau khi c ti u, cc biu thc
Boolean c chuyn ti mch lgc block ca FPGA thng qua chng trnh nh x
cng ngh (technology mapping), b nh x s ti thiu s khi c dng v gim
ng dn ti u v gi chm. Sau khi nh x mch vo cc logic block th cn
phi quyt nh t mi khi u, cng vic ny do chng trnh Placement gii
quyt. Bc cui cng trong h thng CAD l ni kt do phn mm Rounting thc
hin, chng n nh cc on dy FPGA v chn cc chuyn mch c th lp trnh
ph hp vi cc kt ni trong logic block. Sau khi thc hin xong bc ny, kt qu
ca CAD s c np vo n v lp trnh to ra chip FPGA cui cng.



42

Ti u lgic
nh x cng ngh
Rounting
Placement
n v lp trnh
Mch lgic ban u
Sn phm
C
A
D

Hnh 2.10. Qu trnh thit k trn FPGA
Sau y ta s nghin cu chi tit tng giai on ca qu trnh thit k CAD:
2.1.2.2. Ti u l gic
y chnh l cng vic sa li cu trc gim s phc tp ca mch ban u.
Trong giai on ny khng ch n kiu ca cc phn t s c dng sau ny
nn c gi l ti u khng ph thuc vo cng ngh (technology-independent).
Tin hnh ti u chnh l lm gim s d tha hoc loi b nhng biu thc con
chung. Mch sau khi c ti u c chc nng tng ng vi mch ban u.
2.1.2.3. nh x cng ngh
Sau khi ti u logic, nh x cng ngh s bin i mng ny thnh mch cui
cng. iu ny s c lm bng cch chn la tng phn ca mng v mi ci s


43
c thc hin bi mt trong nhng phn t ca mch c sn, v xc nh nhng
mch ny s c ni vi nhau nh th no. Sau y l 3 phng php nh x cng
ngh chnh.
a) nh x cng ngh da vo th vin: Phng php nh cng ngh ny
c tiu chun ho, trong ny l tp cc phn t mch c sn s c biu din
nh mt th vin cc hm v xy dng ti u c chia thnh 3 vn nh: Phn r
(decomposition), so trng (matching), lp ph (convering). u tin mng phn r
biu din bi cc cng NAND 2 u vo, s phn r bo m rng khng c nt
no trong mng l qu ln. Sau khi phn r, mng s c phn hoch thnh mt
rng cy, mch con ti u che ph tng cy v cui cng mch che ph ton b
mng c tp hp t cc mch con.
b) nh x cng ngh dng bng d tm: Bng d tm (Lookup table _ LUTs) l
c s ca nhng khi lgc trong FPGA. Mt bng gm K u vo l mt b nh k
thut s m n c th thc hin bt k hm Boolean no gm K bin. K u vo
c s dng nh v cho 2
K
bit nh c lu tr trong bng s tht ca hm
Boolean. Vi bng LUT gm K u vo c th thc hin c hm Boolean
khc nhau. Tuy nhin th vin biu din bng LUT K u vo li khng cn tt c
hm khc nhau do c s hon v cc u vo, o ngc cc cng vo v cng
ra v nh vy s gim thiu s lng hm trong th vin.
K
2
2
K
2
2
c) nh x cng ngh dng b dn knh (Multiplexer): Khi lgic da trn
Multiplexer bao gm ch yu l mt cy ca nhng b Multiplexer, cng vo ca
khi logic l b dn knh c cng vo la chn v cng vo d liu. Mt khi logic
c lp c ring bit ho hin thc nhng hm khc nhau thng qua vic ni
nhng cng vo ca n ti cc bin l cc hng s 0, 1. Nhng khi logic da trn
Multiplexer c th thc hin c rt nhiu nhng hm khc nhau v v th kh s
dng nh x cng ngh da vo th vin.
2.1.2.4. Sp xp cc phn t (Placement)
Giai on ny ca thit k gm cc cng vic chnh nh sau:
Phn chia h thng (System Partitioning): Mt h thng vi in t bao gm nhiu


44
khi chc nng, nu mt khi chc nng qu ln th chng ta phi thc hin vic
tch hoc phn chia chc nng ca khi ra lm cc khi nh hn theo mc ch
v nh hng m chng ta cn ch nh.
a) Ln s mt bng, b tr cc khi (Floorplanning): Sau khi phn chia h
thng xong s thc hin vic ln s mt bng, b tr cc khi. Floorplanning thc
hin cc cng vic nh ti thiu ha di kt ni v tr tn hiu gia cc khi, sp
t cc khi c nh v t li cc khi di ngc thc hin trc Placement,
cng vic sp t, b tr cc phn t logic trn tng khi, t chc cc vng kt ni
gia cc khi, phn phi mt bng cho ngun v cc ng vo ra...
b) Sp xp cc phn t (Placement): Placement l bc tip theo ca
Floorplanning, n thc hin vic sp t cc phn t logic vo mt khi di ng...
y l bc quan trng trong thit k mch v rt phc tp, nu Placement khng tt
s dn n vic chim din tch ln v gim tc thc thi, nhiu khi cn dn ti
kh nng khng Rounting c. Rt may l cng vic ny c thc hin hon ton
t ng.
Placement, System Partitioning v Floorplanning c th hiu chung l phn
chia h thng trn FPGA - tc l ln s mt bng, b tr cc khi l gic, v ta c
th gi chung l Placement.
c) Mc tiu v i tng ca Placement: Mc tiu chnh ca mt cng c
placement (Sp t b tr cc phn t logic trn tng khi) l sp t tt c cc phn
t logic trong cng cc khi di ng trn mt chip. V l tng m ni, i tng
ca placement l:
- Bo m cng c nh tuyn c th hon chnh bc nh tuyn.
- Ti thiu ho tt c cc khong tr trn ng kt ni.
- Lm cho mt ca chp cng cao cng tt.
- Ti thiu ho tiu th ngun.
- Ti thiu ho s xuyn nhiu gia cc tn hiu.
Cc i tng rt kh nh ngha theo cch gii quyt bng thut ton v
thm ch trong thc t rt kh gp. Cc cng c placement hin nay thng s dng
nhiu c im v cc tiu chun ring.


45
d) Gn chn (Pin Assignmen) : Mc ch ca vic gn chn l nh ngha tn
hiu m mi chn s nhn c. Vic gn chn c th thc hin c trong qu trnh
placement hoc sau qu trnh ny. Nu cc block khng c thit k th php gn
tt cng ci tin c placement, nu cc block c thit k th Pin Assignmen
c th thay i mt vi chn nh chc nng tng ng.
2.1.2.5. nh tuyn trn FPGA (rounting)
Rounting l cng vic cui cng trong qu trnh thit k, sau khi ta sp t
v b tr xong cc phn t logic trn cc khi di ng th y chnh l vic kt ni
bng cch nh tuyn cho chp .
Vic nh tuyn gm 2 bc: nh tuyn tng th v nh tuyn chi tit. nh tuyn
tng th c thc hin trc, sau cc nh tuyn chi tit thc hin theo nh
hng chung ca nh tuyn tng th a ra.
nh tuyn tng th ln k hoch i dy bng cch tm ra cc knh s c s
dng cho mc ch g, cho b phn no. C nhiu kiu nh tuyn tng th i vi
cc loi FPGA, tuy nhin cc thut ton ton tm ng ngn nht th tng t nhau.
C hai phng php chnh cho nh tuyn tng th l: mt ng chnh ti mt thi
im, hoc tt c cc ng cng mt ln. Cng vi s c mt ca gin thi gian
nh tuyn cc i tng, vn nh tuyn tr nn kh hn v yu cu c s hiu
bit v s khc nhau gia vic tm ng ngn nht v tm ng vi tr nh
nht. Cc kiu nh tuyn chi tit khc nhau gm c nh tuyn knh v nh tuyn
da trn vng hoc ma trn. nh tuyn chi tit vi 2 lp kim loi l vn c
cp n nhiu nht.
Cc vn chnh ca nh tuyn l:
- nh tuyn c phn thnh nh tuyn tng th v chi tit.
- Cc thut ton nh tuyn phi ph hp vi cc thut ton placement.
- nh tuyn khng th hon thnh nu khng i dy c.
- Cc ng ngun v xung nhp c iu khin trong trng hp c bit.
- rng cc ng ngun v xung nhp ng b c thit lp bng tay.
2.1.2.6. Ti np chng trnh
y l khu to ra sn phm ca thit k. Ti chng trnh nhn chung c


46
xem nh l ti thng tin xung thit b d bin i nh SRAM FPGA. Thng tin cu
hnh ca thit b c np vo trong b nh ca thit b. Lung cc bit m n c
truyn i c cha tt c cc thng tin nh ngha logic v cc ng ni ca thit k
v thng tin ny khc nhau i vi thit k khc nhau.
Cc thit b SRAM mt i cu hnh ca chng khi mt ngun v vy cc lung
bit cn phi ct u gii quyt bi ton. Mt ni thng c dng ct
thng tin cu hnh thit b, l PROM ni tip. y l thnh phn kt hp vi phn
cng m n ni t my tnh ti bo mch m bo mch ny c cha thit b ch.
Np chng trnh c dng lp chng trnh cho tt c cc thit b logic c
th lp trnh c khng b thay i, chng hn nh PROM ni tip. Vic np
chng trnh thc hin ging chc nng nh ti chng trnh, ring cc thng tin v
cu hnh vn cn sau khi mt in.
2.1.3. Gii thiu v FPGA ca hng ALTERA:
2.1.3.1. Cc loi FPGA trn th trng:
Trong ngnh cng nghip ch to IC ang rt pht trin v phm vi ngy cng
m rng khp th gii th ch c mt s hng i u v chim c th trng trong
vic cung cp cc sn phm FPGA. Trong phi k ti ba hng ln l: Xilink,
Actel v Altera. Hin nay, Vit Nam Xilink v Altera c kh nhiu cc h
thng in t s dng cc thit b FPGA v tc ng dng ca chng ang ngy
mt tng ln. M t tm tt mt s loi FPGA trn th trng trong bng 2.1.

Hng

Kin trc tng qut

Kiu khi logic

Cng ngh lp trnh

Xilink Symmetrical Array Look-up Table Static RAM
Altera Hierachical-PLD PLD Block EPROM
Actel Row-based Multiplexers-Based Anti-fuse
Plessey Sea-of-gates NAND-gate Static RAM
Plus Hierachical-PLD PLD Block EPROM
AMD Hierachical-PLD PLD Block EPROM


47
QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse
Algotronix Sea-of-gates Multiplexers &
Based Gates
Static RAM
Concurent Sea-of-gates Multiplexers &
Based Gates
Static RAM
Crosspoint Row-based Transistor Pairs &
Multiplexers
Anti-fuse
Bng 2.1: Mt s loi FPGA trn th trng
2.1.3.2. c im thit b FPGA ca hng Altera
Kin trc c bn ca Altera FPGA l da trn cng ngh lp trnh EPROM,
hnh 2.11 minh ha kin trc tng qut ca Altera FPGA MAX 7000. Bao gm mt

I
/
O

C
o
n
t
r
o
l
B
l
o
c
k
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
I/O ControlBlock
I/O ControlBlock
I
/
O

C
o
n
t
r
o
l
B
l
o
c
k











Hnh 2.11: Kin trc tng qut ca Altera FPGA MAX 7000
mng ln cc Block lp trnh c gi l Logic Array Block (LABs) c kt ni
vi nhau bi cc ngun ti nguyn rounting.
- Thi gian thit k, thi gian m phng v ch to nhanh.
- Tc x l ca cc thit b cao.


48
- Gi thnh, chi ph u t thp hn so vi cc hng khc, mc ri ro trong
u t thp.
- Kh nng tha hnh cao.
- p ng hu ht cc yu cu t n gin ti phc tp.
- H thng c mc tch hp v n nh cao.
- Cng c h tr v pht trin c cung cp y .
- Ph hp vi kh nng v xu th pht trin ca cc h thng s.
Nhn chung, h thng cng nh cc thit b ca Altera c mc chi ph u t
so vi mc u t ban u vo cc cng ngh cao trong lnh vc in t - vin thng
Vit Nam hin nay l tng i cao. Bn cnh , n i hi c i ng khoa hc
tip thu, nghin cu v s dng c o to k lng v c trnh cao.
2.1.3.3. Cc h FPGA ca hng Altera
Tt c cc h thit b Altera c ch to theo cng ngh CMOS. Gm cc h:
Ma trn logic lp trnh c APEX (Advanced ProgrammablE logic matriX), ma
trn phn t logic linh hot FLEX (Flexible Logic Element MatriX) v ma trn
chui a phn t MAX (Multiple Array matriX), STRATIX... Mi h thit b c c
im ring vi cu trc khc nhau ph hp vi nhiu h thng s c mc tch hp
khc nhau v to ra s a dng trong cc ng dng.

H thit b Cc chn I/O s dng S cng lgc
APEX 20K 95 800 30.000 1.500.000
FLEX 10K 59 470 10.000 200.000
FLEX 8000 68 208 2.500 16.000
FLEX 6000 71 218 16.000 24.000
MAX 9000 52 216 10.000 12.000
MAX 7000 36 212 600 10.000
MAX 5000 28 100 600 3.750
Classic 22 68 300 900
Bng 2.2: S cng s dng v cc chn I/O ca cc h FPGA Altera


49
H linh kin APEX 20K
APEX 20K l dng sn phm c thit k theo kin trc MultiCore, n l s
kt hp nhng tnh nng mnh ca LUT (Look Up Table - bng s tht) v product-
term (cc kt ni) vi mt cu trc b nh c tng cng. Nhng sn phm c
xy dng theo kiu LUT cho php ti u ho tnh nng hot ng v hiu qu cho
cc thit k ng dn d liu, thanh ghi, cc b x l ton hc v cc b x l tn
hiu s. K thut product-term c ti u cho cc ng dn t hp phc tp nh
cc my trng thi. K thut LUT v product-term kt hp vi cc chc nng b nh
cng vi hng lot cc MegaCore v cc chc nng AMPP lm kin trc APEX 20K
thch hp c bit cho thit k cn tch hp ton b h thng trn mt chip. S dng
nhng k thut ny, ta c th tch hp ton b h thng vo mt chip thuc h
APEX 20K.
2.1.4. Cc cng c thit k
2.1.4.1. Gii thiu v EDA
Cc cng c EDA (Electronic Design Automation) ngy nay l cc cng c
ch yu c s dng trong nghin cu v pht trin cc vi mch cng nh cc h
IC tin tin v c gi l cng nghip EDA. Ngnh cng nghip EDA cung cp cc
sn phm, dch v, cng c v c nhiu t chc s dng, cng chnh l cc
cng c c ngi thit k s dng pht trin cc chip my tnh ngy cng phc
tp, thng minh v nhiu tnh nng mi hn.
Cng c EDA c chia thnh cc sn phm chnh sau:
1. Cng c thit k mch in t c h tr my tnh CAE (Computer-Aided
Electronics).
2. Cng c v mch in - PCB v thit k module a chip MCM (Printed Circuit
Board and Multi-Chip Module Layout).
3. Cng c thit k IC (IC Layout).
4. Cng c ch to cc cht bn dn thng minh SIP (Semiconductor Intellectual
Property).
5. Cng c thit k v h tr (Design services and consulting).


50
Nhim v ca EDA l tp hp, phn tch v cung cp thng tin phc v cho
ngi thit k.
Nn cng nghip EDA ngy cng pht trin v dn dn kt ni vi cc cng
ngh mi khc nh cc h thng qun tr nh cung cp v thnh phn - CSM
(Component & Supplier Management), cc h thng phn phi in t, cung cp
dch v thit k, thit k ch to ASIC v chip vi x l, h thng thit k c kh c
tr gip ca my tnh - MCAD (Mechanical Computer-Aided Design),
Mi hng c nhng cng c EDA ca ring mnh. Phn tip theo lun vn
trnh by 2 phn mm chnh c hng Altera a ra pht trin thit b ca mnh.
2.1.4.2. Gii thiu cng c thit k Quartus II.
Cng c thit k Quartus II l h thng pht trin th t ca hng ALTERA
cho cc linh kin lp trnh c. N a ra cc c trng rt mnh rt ngn chu
trnh thit k v tng nng sut thit k. S dng ch yu cho thit k cc h chp
FPGA c dung lng ln nh APEX 20K, STATIC...
Cc c im chnh l:
- H tr a x l (Multi-processor) v tng cng kh nng bin dch li rt
ngn chu trnh thit k.
- Phng php tch hp ton b h thng trn mt chip kt hp vi tnh nng
son tho mc khi, tnh ton theo nhm v h tr m rng cho cc siu chc nng
(MegaFunction) s t chc cc s pht trin h thng s tt hn, nng cao hiu
sut lm vic v cht lng ca h thng.
- Cc tnh nng giao tip d dng vi cc phn mm EDA khc cho php ngi
thit k s dng cc cng c m h quen thuc thit k cho cc mch t hp
logic lp trnh c ca hng ALTERA.
- Kh nng h tr k thut bng cch tip cn trc tip ti h c s d liu trc
tuyn ca ALTERA t phn mm Quartus II lm mi thnh vin trong b phn
thit k lm vic c hiu qu hn.
- H tr mch t hp logic lp trnh c APEX 20K vi cht lng cao v kh
nng tch hp ton b h thng trn mt chip (System-on-a-Programmble-Chip).
u im chnh ca Quartus II:


51
- Rt ngn thi gian bin dch vi trnh bin dch nStep Compiler: cc thit k
phc tp thng xuyn yu cu lp li mt vi thit k n gin t c kt qu
mong mun. Trnh bin dch nStep Compiler ca Quartus II cho php ngi thit k
lm thay i mt b phn trong thit k v t c kt qu m khng cn bin dch
li ton b chng trnh. Phn mm Quartus II ch bin dch cc phn thit k
thay i. Trnh bin dch nStep Compiler s dng kh nng tng hp mi kiu
CoreSyn ca ALTERA. Trnh bin dch s phn tch cc thit k, sau phn chia
cc chc nng ca mt thit k vo cc phn t logic da trn bng tm kim, cc
macrocell (th vin phn t) hoc cc khi logic b nh t hp (RAM, ROM) thch
hp trong FPGA .
- Ci tin chu trnh kim tra v phn tch logic kiu SignalTap: phn mm
Quartus lm gim thi gian kim tra thit k bng cch cung cp mt trnh m
phng thi gian y c trng v mt trnh m phng mc truyn thanh ghi.
Kh nng phn tch logic SignalTap tch hp cc chc nng ca mt b phn tch
logic vo phn mm cho php ngi thit k thc hin vic kim tra phn cng trn
thit b ang hot ng ti tc h thng thc t.
- Tch hp NativeLink (lin kt ngc) vi cc cng c EDA khc: c trng
tch hp NativeLink lm thun tin cho vic truyn thng tin d dng gia phn
mm Quartus II v cc cng c EDA khc tng cng ton b hiu sut ca b
cng c EDA ca ngi thit k. c trng NativeLink cho php ngi thit k s
dng cc c lng v v tr v l trnh c sn ca Quartus II trong cc cng c EDA
khc ti u cc giai on tng hp.
- Kh nng nh v li v ti u thi gian: phn mm Quartus II cho php sa li
v ti u thi gian d dng hn. N c th ch ra ngun gy li trc tip trong cc
file thit k ca cc cng c EDA, tng cng qu trnh sa li v iu chnh cc
tham s thi gian.
2.1.4.3. Gii thiu cng c thit k MAX + PLUS II:
Phn mm pht trin MAX + PLUS II cung cp mt mi trng thit k hon
chnh p ng y cc nhu cu thit k c th. MAX + PLUS II m bo thit k
d dng, x l nhanh v lp trnh cho cc linh kin PLD mt cch trc tip.


52
Phn mm MAX + PLUS II tch hp y cc chc nng v c lp vi kin
trc phn cng trong vic thit k logic vi cc mch t hp logic lp trnh c ca
hng ALTERA thuc cc h Classic, ACEX 1K, MAX 3000, MAX 5000, MAX
7000, MAX 9000, FLEX 6000, FLEX 8000 v FLEX 10K. MAX + PLUS II cung
cp mt phm vi thit k logic y bao gm cc thit k phn tng, son tho s
thit k, tng hp logic ti u, phn chia thit k, m phng thit k mc bng
mch c v thi gian v chc nng, phn tch chi tit thi gian, nh v li t ng,
lp trnh v kim tra cc IC. MAX + PLUS II cng c th s dng cc file thit k
theo tiu chun cng nghip ca cc phn mm thit k khc nh cc file kiu
EDIF, VHDL,Verilog HDL, OrCAD Schematic, Xilinx Netlist Format. N cng cho
php vit cc tp thit k kiu EDIF, VHDL, Verilog HDL, VITAL - Compliant
giao tip vi cc phn mm thit k CAE tiu chun cng nghip khc.
Ngi thit k c th tch hp cc thit k c to vi cc phn mm thit k
ca ALTERA nh A+PLUS, SAM+PLUS vo cc thit k ca MAX+PLUS II.
Trnh bin dch bo m rng cc thit k trong MAX+PLUS II s c to hon
chnh trong cc IC mt cch hiu qu nht.
u im chnh ca MAX+PLUS II:
- MAX+PLUS II cung cp mt giao din s dng ha phong ph v mt h
thng tr gip c tnh minh ha rt d s dng. H thng MAX+PLUS II hon chnh
bao gm nhiu ng dng tch hp tr gip ngi thit k tng bc t thit k n
lp trnh IC.
- Cc trnh thit k trong MAX+PLUS II nh Graphic Editor, Text Editor,
Waveform Editor, Floorplan Editor, Symbol Editor cng s dng chung nhiu cng
c v c trng thit k. Cc trnh son tho cho php ngi thit k thc hin cc
cng vic tng t nhau.
- Ngi thit k c th t hp cc kiu tp thit k khc nhau trong mt n
thit k v chn cc nh dng thit k s lm vic tt nht cho mi khi chc nng.
Vic thit k c lp kin trc phn cng gip ngi thit k khng phi lo lng v
vic thit k ca mnh s ph hp vi IC loi no.
- Ngi thit k c th lm vic vi cc ng dng MAX+PLUS II khc nhau ti


53
cng mt thi im. V d, ngi thit c th m nhiu tp thit k v truyn thng
tin gia chng trong khi vn bin dch v m phng cc n khc. C th quan st
ton b s phn cp ca cc tp thit k v di chuyn d dng t mc phn cp
ny ti mc phn cp khc. Khi m mt tp thit k, MAX+PLUS II s chy t
ng mt trnh son tho thit k thch hp.
- Trnh bin dch MAX+PLUSII l ht nhn trung tm ca MAX+PLUS II, n
cung cp mt qu trnh x l rt mnh gip ngi thit k c th to c mt kin
trc ti u nht bn trong cc IC. Vic nh v li t ng v ti liu v nguyn nhn
v cch sa li s lm vic sa i thit k rt n gin. Ngi thit k c th to
cc file u ra trong cc nh dng khc nhau dng cho m phng, phn tch thi
gian, v lp trnh cc IC nh file EDIF, Verilog HDL, VHDL s dng cc cng
c EDA tiu chun cng nghip. Ti mi bc trong qu trnh thit k, phn mm
MAX+PLUS II gip ngi thit k tp trung nhiu vo cng vic m khng phi
quan tm nhiu n cch s dng phn mm.
- Tnh nng siu t hp ca MAX+PLUS II s ci tin nng sut v cht lng
ca cc ng dng. N gip ngi thit k kim sot ton b h thng mt cch d
dng v hiu qu.
2.1.5. Cc ngn ng m t phn cng
H tr mnh m cho vic thit k mch vi in t l nhng ngn ng m t
phn cng (HDLs - Hardware Description Langgues). Trong qu trnh thit k, cc
ngn ng m t phn cng chnh l cc cng c thit k nhm mc ch m phng,
to mu, kim tra, thit k nh ngn ng m t hnh vi, ngn ng m t dng d
liu, s lin kt kt ni. Mt s ngn ng HDL nh sau:
- AHPL l mt HDL m t dng d liu.
- CDL (Computer Design Language): Ngn ng m t dng d liu pht trin
trong qa trnh o to.
- CONLAN (Consensus Language): Ngn ng m t phn cp phn cng.
- IDL (Interactive Design Language): Ngn ng to t ng cu trc PLA ca
hng IBM.
- TEGAS (Test Generation and Simulation): H thng to tn hiu kim tra v


54
m phng cc mch s, y l ngn ng cu trc.
- VHDL (Very high speed integrated circuits HDL) l ngn ng m t phn cng
c cng nhn tiu chun IEEE t nm 1987. N l ngn ng c y sc mnh
cho vic m t, thit k mt ng dng t n gin cho n phc tp.
- Verilog l mt ngn ng h tr phn cp thit k, n xut hin sau ngn ng
VHDL c c im rt r s dng. Cng vi VHDL, ngn ng Verilog c chun
ho v c s dng rt rng ri cc nc.
2.2. ngn ng m t phn cng VHDL
2.2.1. Gii thiu chung v ngn ng VHDL
VHDL (VHSIC Hardware Description Laguage) l mt ngn ng c dng
m t cc h thng in t s. VHSIC (Very High Speed Integrated Circuits) do
chnh ph M khi xng vo u nhng nm 1980. Cc cng ty tham gia chng
trnh VHSIC nhn thy rng h cn phi c mt cng c no thit k cc gin
u vo cho cc IC chuyn dng c ln, v h xut vic lp ra mt ngn
ng m t phn cng dng m t cu trc v chc nng ca cc mch tch hp.
K t , VHDL ra i v c pht trin, sau c t chc IEEE (Institude
of Electrical and Electronic Engineers) chp nhn coi nh l tiu chun ti M.
Phin bn u tin l tiu chun IEEE 1076-1987 (cn c gi l VHDL-87). Phin
bn ny c b sung sa i nm 1993 thnh IEEE 1076-1993 (cn c gi l
VHDL-93).
VHDL c thit k nhm thay th cho mt s khu cn thit trong qu trnh
thit k. u tin, n cho php m t cu trc ca mt bn thit k, tc l lm th
no c th phn tch bn thit k thnh cc bn thit k con, v lm th no
kt ni cc bn thit k con li vi nhau. Th hai l n cho php m t c im
chc nng ca cc bn thit k tng t nh trong ngn ng lp trnh. Th ba l da
vo kt qu t c, n cho php mt bn thit k c th m phng c trc khi
a vo sn xut, v vy cc nh thit k c th so snh mt cch nhanh chng vic
thay th v kim tra iu chnh chnh xc m khng mt thi gian v chi ph vo
vic ch to mu th u tin.


55
2.2.1.1. M t cu trc
Mt h thng in t s c th c m t thnh cc khi - cn gi l module
vi cc u vo v u ra. Cc gi tr in u ra c mi quan h vi cc gi tr
trn cc u vo. Hnh 2.12.a biu din mt v d nh vy, khi F c hai u vo A
v B, v c mt u ra Y.
S dng ngn ng VHDL m t khi F, th ta gi khi F l mt thc th
(entity) thit k, v cc u vo v u ra l cc cng (port).
C mt cch m t chc nng ca khi F, l chng ta m t cc khi con
(sub-module) thnh phn ca n. Mi mt khi con c gi l mt tp hp
(instance) ca mt s thc th, v cc cng ca cc tp hp c ni li bng cc
ng tn hiu (signal).
Hnh 2.12.b m t khi F l mt tp hp gm cc thc th G, H v I. Kiu m
t ny c gi l m t cu trc (structural). Cc thc th G, H v I cng c m
t theo cu trc tng t nh vy.


a) Khi F c hai u vo v mt u ra; (b) Khi F gm 3 thc th G, H, I
Hnh 2.12: S khi mt module m t bng VHDL
2.2.1.2. M t hot ng
Trong nhiu trng hp, vic m t cu trc khng tng ng vi vic m t
hot ng. Thc t thng dng cch m t hot ng theo kiu t di ln da vo
m t cu trc. V d, khi thit k h thng in t th khng cn phi m t c th
cu trc bn trong ca tng IC m ch cn m t theo chc nng ca cc khi ca h
thng m thi. Trng hp ny c gi l m t chc nng (fuctional) hoc m t


56
hnh vi (behavioural).
minh ho cho iu ny, chng ta gi s rng chc nng ca thc th F trong
hnh 2.12.a l mt mch OR o. Khi m t hot ng ca F ta c th bin i theo
i s Boolean nh sau: B A B A Y . . + =
i vi cc mch c chc nng hot ng phc tp hn, th khng th biu
din theo cc chc nng u vo c. Trong cc h thng c phn hi ngc, u
ra thng l cc hm chc nng theo thi gian. Ngn ng VHDL cho php gii
quyt vn ny bng cch m t hot ng theo khun dng chng trnh lp trnh.
2.2.1.3. M hnh thi gian theo cc s kin ri rc
Khi chc nng hot ng v cu trc ca khi c ch nh r, ngi thit
k c th m phng khi bng cch kch hot theo m t hot ng ca n. iu
ny c th thc hin c bng cch m phng qu trnh hot ng c ri rc
thnh cc bc theo thi gian. Ti mt vi thi im m phng, khi u vo c
kch hot bng cch thay i gi tr trn cng u vo. Khi ny phn ng li bng
cch thc hin m lnh theo m t hot ng ca n c gn v to ra cc gi tr
mi a n ng tn hiu gi ti cc cng u ra ca n ti cc thi im m
phng tip theo sau, cng vic ny c gi l k hoch giao tc (scheluding a
transaction) trn tn hiu . Nu gi tr mi khc gi tr trc c trn ng
tn hiu, th s c mt s kin (event) xy ra, v cc khi khc vi cc u vo
c kt ni vi ng tn hiu c th s c kch hot.
Qu trnh m phng bt u vi mt pha c gi l pha khi ng
(initialisatoin phase), v sau cc qu trnh c thc hin lp li hai giai on
trong mt chu k m phng (simulation cycle). Trong pha khi ng, tt c cc tn
hiu c cung cp sn cc gi tr khi ng, thi gian m phng c a v 0, v
mi mt chng trnh hot ng ca mt khi c kch hot.
Trong giai on u tin ca chu k m phng, thi gian m phng c nng
ln thnh thi gian sm nht ti thi im m giao tc c thc hin. Tt c cc
giao tc c a vo ti thi im ny u c kch hot, v iu ny c th gy
ra mt s s kin no .
Trong gian on th hai ca chu k m phng, tt c cc khi phn ng li i


57
vi cc s kin va xy ra trong giai on mt s kch hot chng trnh hot ng
ca chng. Cc chng trnh thng l k hoch giao tc trn cc tn hiu u ra
ca chng. Khi tt c cc chng trnh kt thc hot ng, chu k m phng c
lp li. Nu khng c thm thao tc no th qu trnh m phng hon thnh.
Mc ch ca vic m phng l bit thm thng tin v s thay i trong h
thng ti tng thi im. Vic ny c th thc hin c gim st bi chng trnh
gim st m phng (simulation monitor). Chng trnh ny nhm mc ch ghi li
qu trnh hot ng theo tng thi im ti cc im dng phn tch v sau.
2.2.2. M hnh t chc
2.2.2.1. Th vin thit k
Khi ngi thit k vit m t cc hot ng VHDL th phi ghi li dng cc tp
thit k (design file), sau dng mt trnh bin dch phn tch c php ca
chng v a chng vo thnh lp mt th vin thit k (Design Library). Mt s
cc cu trc ca VHDL c th c phn tch ring r a vo th vin thit k.
Cc cu trc c gi l cc n v th vin (Library Units). Cc n v th vin
chnh (primary) bao gm cc m t u vo, cc m t ng gi thnh phn chnh
v cc m t cu hnh. Cc n v th vin ph (secondary) bao gm cc thn
chng trnh kin trc v cc thn ca cc ng gi thnh phn chnh. Cc n v
th vin ph thuc vo c im giao din ca chng trong cc n v th vin
chnh tng ng, v n v chnh phi c phn tch trc bt k n v ph no
tng ng.
Cc th vin c tham chiu s dng cc nh danh c gi l cc tn
logic (logic name). Tn ny phi c dch bi h iu hnh ch thnh mt tn lu
tr hot ng c lp. V d, cc th vin thit k c th hot ng nh cc tp c s
d liu (database file), v tn logic phi c dng c th xc nh tn tp c s
d liu. Cc n v th vin trong th vin c cung cp c th tham chiu n
thng qua hu t tn ca chng vi tn logic th vin.
C hai loi th vin c bit hon ton c th s dng c cho tt c cc n
v thit k, v khng cn t tn trong mnh th vin. Th vin u tin c tn l


58
work, n tham chiu th vin thit k ang lm vic vo n v thit k hin ti s
c t dnh cho ngi phn tch. Sau khi t vo n v thit k, cc n v thit
k c phn tch trc trong tp thit k c th tham chiu s dng tn th
vin c sn l work.
Th vin c bit th hai c gi l std, v n cha cc dng ng gi
standard v textio. Standard bao gm tt c cc kiu nh ngha sn v cc hm
chc nng. Tt c cc thnh phn con trong cc ng gi u c th s dng
c, v khng cn s dng cc mnh truy xut chng.
2.2.2.2. Cc cu hnh
Chng ta cp n mt thnh phn c khai bo c th c coi nh
mt mu cho mt thc th thit k. S rng buc ca mt thc th ti mu ny t
c thng qua mt m t cu hnh. M t ny c th c s dng ch nh cc
hng s chung trong thc t cho cc thnh phn v khi. Nh vy m t cu hnh
(configuration declaration) ng vai tr chnh trong vic t chc m t thit k khi
chun b cho vic m phng hoc cc x l khc.
2.3. kt lun chng 2.
Chng 2 lun vn trnh by nhng nt c bn v cng ngh FPGA. Gii
thiu mt cch khi qut v s pht trin ca linh kin lp trnh c, quy trnh thit
k mt sn phm trn cng ngh FPGA, mt s c im tm tt ca cc ngn ng
m t phn cng trong m t c bn v ngn ng m t phn cng VHDL l
ngn ng s c dng trong qu trnh thit k modul (chi tit v ngn ng VHDL
c th tham kho trong [6],[15],[16]). Trn c s cng ngh FPGA v cc thut ton
m khi c trnh by trn vic la chn thut ton m khi m phng
cng nh qu trnh thit k modul m khi s c trnh by trong chng 3.






59
Chng 3
Phng php thit k modul m khi
trn cng ngh Fpga

3.1. cu trc ca Modul m khi
3.1.1. Cu trc chung
Nguyn l thit k v cu trc ca thut ton m khi c trnh by trong
chng I ca lun vn. Trn c s , cu trc ca modul m khi c xy dng
nh s hnh 3.1.

Kho m

Khi x l m
ho/gii m d
liu.
iu khin
D liu ra D liu vo
Hnh 3.1: Cu trc chung ca modul m khi
Trong :
- Khi d liu vo (ra) l bn tin r (m) c di M bt .
- Khi x l m ho/gii m d liu l khi ng vai tr chc nng chnh ca
modul m khi, c nhim v m ho hay gii m d liu theo thut ton m khi
c chn la.


60
- Kho m di K bt c nhim v kt hp vi cc hm ton hc ca thut
ton m khi thc hin m ho hay gii m khi d liu.
- Khi iu khin thc hin nhim v iu khin ton b hot ng ca modul.
3.1.2. Mt s yu cu i vi modul m khi
Module m khi dng trong h truyn tin mt phi tho mn mt s yu cu
c bn sau:
- V mt mt m: Phi m bo yu cu bo mt, yu cu nghip v mt m tu
theo cc cp mt khc nhau ph thuc vo ni dung thng tin cn bo mt.
- V mt k thut cng ngh: Phi m bo tc m ho, tc gii m ph
hp vi tc lung d liu ca h thng truyn tin.
- V mt h thng: Phi ghp ni c vi cc thit b truyn tin, ng b gia
phn m ho v gii m, hn ch thp nht cc kh nng gy li cho ton b h
thng truyn tin mt
- V mt s dng: C tnh tin dng v chuyn dng, c tin cy cao trong khi
hot ng, linh hot trong qu trnh x l, gi thnh ph hp, hiu qu kinh t cao.
3.2. la chn thut ton cho m phng thit k
3.2.1. La chn thut ton.
Vic la chn thut ton m khi m phng thit k c ngha chng minh
v kh nng cng nh cch thc tin hnh khi thit k mt h m khi trn FPGA
nn n phi p ng c cc tiu ch:
- Mang y c trng c bn ca cu trc Feistel.
- c ph bin rng ri v c kim chng trn thc t.
Trong s cc thut ton m khi c cng b, thut ton DES p ng
c hai tiu ch trn, v:
- DES c y cc c trng ca cu trc Feistel nh c trnh by trong
mc 1.2.4 v trong mt s cu trc bin i khc nh cc hp nn, cc php hon
v, cc php dch vng li mang nhng c trng ca cu trc cng - nhn.
- DES c tha nhn l chun mt m ca M t cui nhng nm 1970,
c s dng rng ri trn th gii.


61
3.2.2. M t thut ton DES.
Thut ton DES [1],[7] thc hin m ho bn r X c di 64 bits vi kho m K
c di 56 bt, cho bn m l mt xu bt Y c di 64 bits.
Thut ton DES hot ng 4 ch : ECB, CBC, CFB, OFB trong , ch
ECB l ch hot ng tiu biu ca m khi v t y v sau thut ng DES c
hiu l DES lm vic ch ECB.
Lc ca thut ton DES c m t trn hnh 3.2.
Thut ton tin hnh theo 3 giai on:
Giai on 1. Vi bn r cho trc x, mt xu bt x
0
s c xy dng bng
cch hon v cc bt ca x theo php hon v c nh ban u IP. x
0
= IP(X) = L
0
R
0
,
trong L
0
gm 32 bt u v R
0
l 32 bt cui.
Giai on 2. Sau tnh ton 16 ln lp theo mt hm ton hc xc nh,
tnh L
i
R
i
, 1 i 16 theo quy tc sau:
L
i
= R
i-1
R
i
= L
i-1
f(R
i-1
,K
i
)
trong k hiu php hoc loi tr ca hai xu bt (cng theo modulo 2). F l mt
hm s c m t sau, cn K
1
,K
2
, . . . ,K
16
l cc xu bt di 48 c tnh nh
hm ca kho K. (trn thc t mi K
i
l mt php chn hon v bt trong K). K
1
, . . .,
K
16
s to thnh bng kho. Mt vng ca php m ho c m t trn hnh 3.3.
Giai on3. p dng php hon v FP

cho xu bt R
16
L
16
, ta thu c bn m
y. Tc l y=FP (R
16
L
16
). Hy ch th t o ca L
16
v R
16
.
3.2.2.1. Hm F trong thut ton DES
Hm F: C hai bin vo.
- Bin th nht A l xu bt di 32.
- Bin th hai J l mt xu bt di 48. u ra ca f l mt xu bt di 32.
a) Bin th nht A c m rng thnh mt xu bt di 48 theo mt hm m
rng c nh E. E(A) gm 32 bt ca A (c hon v theo cch c nh) vi 16 bt
xut hin hai ln.
b) Tnh E(A) J v vit kt qu thnh mt chui 8 xu 6 bt =B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
.


62
Hnh 3.2: Lc ca thut ton DES.
c) Bc tip theo dng 8 bng S
1
, S
2
, ...,S
8
(c gi l cc hp th S-BOX). Vi
mi S
i
l mt bng 416 c nh c cc hng l cc s nguyn t 0 n 15. Vi xu
bt c di 6 (k hiu B
i
= b
1
b
2
b
3
b
4
b
5
b
6
), ta tnh S
j
(B
j
) nh sau: Hai bt b
1
b
6
xc
nh biu din nh phn ca hng r ca S
j
( 0 r 3) v bn bt (b
2
b
3
b
4
b
5
) xc nh
biu din nh phn ca ct c ca S
j
( 0 c 15 ). Khi S
j
(B
j
) s xc nh phn t
S
j
(r,c); phn t ny vit di dng nh phn l mt xu bt c di 4 (bi vy, mi
S
j
c th c coi l mt hm m m u vo l mt xu bt c di 2 v mt xu


63
Hnh 3.3: Mt vng ca DES

L
i-1
R
i-1

F
K
i
+
L
i
R
i
J
E
+
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
S
1
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
E(A)
P
S
2
S
3
S
4
S
5
S
6
S
7
S
8
F(A,J)F(A,J)
E(A)
Hnh 3.4: Hm F ca thut ton DES


64
bt c di 4, cn u ra l mt xu bt c di 4). Bng cch tng t tnh cc
C
j
= S
j
(B
j
), 1 j 8.
d) Xu bt C = C
1
C
2
... C
8
c di 32 c hon v theo php hon v c nh P.
Xu kt qu l P(C) c xc nh l F(A,J).
Hm F c m t trn hnh 3.4. Ch yu n gm mt php th (s dng hp S-
BOX ), tip sau l php hon v P; 16 php lp ca F s to nn mt h mt tch.

Php hon v ban u IP
58 50 42 34 26 18 10 2
60 52 44 36 28 20 12 4
62 54 46 38 30 22 14 6
64 56 48 40 32 24 16 8
57 49 41 33 25 17 9 1
59 51 43 35 27 19 11 3
61 53 45 37 29 21 13 5
63 55 47 39 31 23 15 7
Bng 3.1: Cc tham s ca php hon v ban u IP
Bng ny c ngha l bt th 58 ca x l bt u tin ca IP(x); bt th 50 ca x
l bt th hai ca IP(x), .v.v . . .
Php hon v FP
40 8 48 16 56 24 64 32
39 7 47 15 55 23 63 31
38 6 46 14 54 22 62 30
37 5 45 13 53 21 61 29
36 4 44 12 52 20 60 28
35 3 43 11 51 19 59 27
34 2 42 10 50 18 58 26
33 1 41 9 49 17 57 25
Bng 3.2: Cc tham s ca php hon v FP


65
Bng chn E bt
32 1 2 3 4 5
4 5 6 7 8 9
8 9 10 11 12 13
12 13 14 15 16 17
16 17 18 19 20 21
20 21 22 23 24 25
24 25 26 27 28 29
28 29 30 31 32 1
Bng 3.3: Cc tham s ca hm m rng E
Hp th S -Box :
S
1
14 4 13 1 2 15 11 8 3 10 6 12 5 9 0 7
0 15 7 4 14 2 13 1 10 6 12 11 9 5 3 8
4 1 14 8 13 6 2 11 15 12 9 7 3 10 5 0
15 12 8 2 4 9 1 7 5 11 3 14 10 0 6 13

S
2
15 1 8 14 6 11 3 4 9 7 2 13 12 0 5 10
3 13 4 7 15 2 8 14 12 0 1 10 6 9 11 5
0 14 7 11 10 4 13 1 5 8 12 6 9 3 2 15
13 8 10 1 3 15 4 2 11 6 7 12 0 5 14 9

S
3
10 0 9 14 6 3 15 5 1 13 12 7 11 4 2 8
13 7 0 9 3 4 6 10 2 8 5 14 12 11 15 1
13 6 4 9 8 15 3 0 11 1 2 12 5 10 14 7
1 10 13 0 6 9 8 7 4 15 14 3 11 5 2 12



66
S
5
2 12 4 1 7 10 11 6 8 5 3 15 13 0 14 9
14 11 2 12 4 7 13 1 5 0 15 10 3 9 8 6
4 2 1 11 10 13 7 8 15 9 12 5 6 3 0 14
11 8 12 7 1 14 2 13 6 15 0 9 10 4 5 3

S
7
4 11 2 14 15 0 8 13 3 12 9 7 5 10 6 1
13 0 11 7 4 9 1 10 14 3 5 12 2 15 8 6
1 4 11 13 12 3 7 14 10 15 6 8 0 5 9 2
6 11 13 8 1 4 10 7 9 5 0 15 14 2 3 12

S
8
13 2 8 4 6 15 11 1 10 9 3 14 5 0 12 7
1 15 13 8 10 3 7 4 12 5 6 11 0 14 9 2
7 11 4 1 9 12 14 2 0 6 10 13 15 3 5 8
2 1 14 7 4 10 8 13 15 12 9 0 3 5 6 11
Bng 3.4: Tham s ca cc hp S-Box
Php hon v P trong hm F :
P
16 7 20 21
29 12 28 17
1 15 23 26
5 18 31 10
32 27 3 9
19 13 30 6
22 11 4 25
Bng 3.5: Cc tham s ca php hon v P


67
3.2.2.2. Lc to kho m dch.
y l phn m t vic tnh ton bng kho t kho K. Trn thc t, K l mt
xu bt di 64, trong 56 bt l kho v 8 bt kim tra tnh chn l nhm pht
hin sai. Cc bt cc v tr 8,16,24,32,40,48,56,64 c xc nh sao cho mi byte
cha mt s l cc s "1". Bi vy mt sai st n l c th pht hin c trong
mi nhm 8 bt. Cc bt kim tra b b qua trong qu trnh tnh ton bng kho.
a) Vi mt kho K c di 64 bt cho trc, loi b cc bt kim tra tnh chn
l v hon v cc bt cn li ca K theo php hon v c nh PC-1.
PC-1(K) = C
0
D
0
b) Vi i thay i t 1 n 16:
C
i
= LS
i
(C
i-1
)
D
i
= LS
i
(Di-1)
Trong LS
i
l php dch vng tri, ph thuc vo gi tr ca i. Vi i = 1,2,9
hoc 16 th dch vng sang tri 1 v tr, cn cc gi tr khc ca i th dch vng sang
tri 2 v tr.
Hon v PC-1
57 49 41 33 25 17 9
1 58 50 42 34 26 18
10 2 59 51 43 35 27
19 11 3 60 52 44 36
63 55 47 39 31 23 15
7 62 54 46 38 30 22
14 6 61 53 45 37 29
21 13 5 28 20 12 4
Bng 3.6: Cc tham s ca php hon v PC-1
Hon v PC-2
14 17 11 24 1 5
3 28 15 6 21 10
23 19 12 4 26 8


68
16 7 27 20 13 2
41 52 31 37 47 55
30 40 51 45 33 48
44 49 39 56 34 53
46 42 50 36 29 32
Bng 3.7: Cc tham s ca php hon v PC-2
Nh ni trn, mi vng s dng mt kho 48 bt gm 48 bt nm trong K.
Php gii m c thc hin nh dng cng thut ton nh php m nu u
vo l Y nhng dng bng kho theo th t ngc li K
16
,...K
1
. u ra ca thut
ton s l bn r X.

K

C
0
D
0
LS
1
C
1
D
1
PC-2
.
.
LS
16
LS
16
C
16
D
16
PC-2 K
16
K
1
LS
1
PC-1
Hnh 3.5: S tnh kho ca thut ton DES.


69
3.3. phng php thit k modul des trn fpga
3.3.1. Quy trnh v cng c thit k
3.3.1.1. Quy trnh thit k
Phng php thit k nhm p dng DES trn cng ngh FPGA hon ton tun
th theo qui trnh thit k mt ng dng trn cng ngh FPGA c trnh by
trong chng 2. Thc cht ca vic thit k modul m khi trn FPGA l vic lp
trnh thit lp cu hnh ghp ni cc phn t mch c sn trn linh kin FPGA
nhm thc thi cc khu x l ca thut ton DES khi thc hin php m/gii m
cng nh hot ng ca cc khi chc nng.
Qu trnh thit k c thc hin theo cc bc sau:
a) Xy dng cc khi hm c bn ca thut ton m khi DES bng ngn ng
m t phn cng.
b) Bin dch v kim tra tng khi chc nng mc RTL (Register Transfer
Level)
c) Tng hp v ti u v mt logic
d) t v nh ng i cho cc thit b chuyn dng.
e) Kim tra thit k .
f) Np cu hnh cho phn cng.
Cc bc b, c, d ch yu do cng c thit k thc hin mt cch t ng.
3.3.1.2. Cng c thit k.
Trong chng 2 lun vn trnh by tng qut v cng ngh cng nh ngn
ng m t phn cng VHDL v gii thiu mt s hng chuyn sn xut linh kin
FPGA trong cc h sn phm ca hng ALTERA l nhng sn phm ph bin
trn th trng hin nay. V vy cng c thit k c chn nh sau:
a) Cng c phn mm:
- Thit k cc khi hm c bn ca DES bng ngn ng VHDL.
- H cng c pht trin cho thit k logc Quartus II ca ALTERA.
b) Cng c phn cng:
FPGA c s dng trong thit k l dng linh kin ca ALTERA.


70
3.3.2. S khi chc nng ca modul m khi DES trn FPGA
3.3.2.1. S khi tng qut.
T cu trc chung ca modul m khi v thut ton DES, s khi tng qut
ca modul m khi gm cc thnh phn m t trn hnh 3.6.
- Khi vo/ra d liu: Vo/Ra d liu r/m; vo kho m; di khi d liu
l 64 bt.
- Khi FPGA DES: Tnh ton kho con; thc hin cc hm m ho, gii m
theo thut ton DES.
- Khi iu khin: Cc tn hiu iu khin hot ng ca Modul.
- Khi cu hnh cho FPGA.



FPGA
DES
iu khin
D liu ra D liu vo
Kho m vo
Cu
hnh
Hnh 3.6: S khi tng qut ca modul m khi DES trn FPGA
3.3.2.2. M t qu trnh m ho gii m ca DES.
M t chung v qu trnh m ho/gii m ca thut ton DES trn hnh 3.7.
- Khi m ho: D liu r c di 64 bt c chuyn vo hon v IP, sau
i qua 16 vng lp vi cc kho t K
1
, K
2
,...., K
16 ,
tip theo d liu c chuyn vo


71
hon v FP cho ra bn m.
- Khi gii m thc hin theo th t ngc li so vi khi m ho vi cc kho
t K
16
, K
15
,...., K
1

Hnh 3.7: Qu trnh m ho/gii m DES
K
1
K
15
K
16
K
16
K
2
K
1
Bn r








Tnh
ton
kho
con
Hon v IP Hon v IF
Vng 1
Vng 1
Vng 2
Vng 16
Hon v FP
Hon v FP
Bn m
Vng 2
Vng 16
Bn r
Bn m
3.3.2.3. S khi chc nng ca modul DES.
Hnh 3.8 m t cc chc nng chnh ca modul DES gm :
- Khi vo/ra d liu (Converter).
- Khi thc hin php hon v IP.
- Khi thc hin m ho/gii m DES 16 vng (Des16).
- Khi tnh kho con cho cc vng lp ca DES (Deskey).
- Khi thc hin php hon v FP.
- Cc tn hiu iu khin (Control)


72

Data_out
Data_in
32 L
0
32 R
0
32 R
0
32 L
0
48
48
48
K
1
K
16
K
1
64

IP
Tnh
kho

DES

16 vng


FP
EN
Clk
Reset
64
64
En/De
Key
Hnh 3.8: M t chc nng modul m ho DES
Chc nng cc chn tn hiu ca modul DES c m t trong bng 3.8.
Tn chn tn
hiu
Kiu I/O M t
Reset Input t trng thi ban u cho ton b h thng
Clk Input H thng xung nhp. Cung cp nhp cho hot ng
ca cc khi trong modul
EN Input Tn hiu cho php: EN=1 cho php h thng
hot ng; EN=0 dng hot ng ca h thng.
En/De Input E/D=1 Ch m ho.
E/D=0 Ch gii m.
Key[1..64] Input Kho m: 64 bt(56 bt kho + 8 bt kim tra)
Data_in [1.64] Input 64 bt d liu vo
Data_out[1.64] Output 64 bt d liu m ra trong ch m ho hoc d
liu r trong ch gii m.
Bng 3.8: M t cc tn hiu vo ra ca modul DES
Hot ng ca cc khi trong modul m khi s c ln lt m t bng
ngn ng m t phn cngVHDL. Phn m t chi tit c nu trong ph lc.


73
3.3.3. M t hot ng ca cc khi trong modul DES bng VHDL
M t thut ton DES bng VHDL s c thc hin t mc m t khi cao
nht (Top Level) sau s ln lt i vo cc chc nng chnh ca tng khi c bn.
Cn c theo s khi ca Modul, phn mm chc nng ca cc khi s c xy
dng thnh cc tp tin chnh nh m t trong bng 3.9. Cc th vin chun IEEE v
LPM ca QUARTUS-II s c s dng trong chng trnh. Phn khai bo cc thc
th trong modul DES s dng cc tn hiu c kiu l STD_LOGIC v
STD_LOGIC_VECTOR c nh ngha trong IEEE std_1164-1993.

Tn tp tin M t chc nng
Des.vhd M t modul DES mc cao nht (Top Level).
IP.vhd, FP.vhd M t cc php hon v IP, FP.
Des1.vhd M t hot ng mt vng lp ca DES.
Des16.vhd M t ton b hot ng 16 vng lp ca DES
Deskey.vhd M t vic tnh ton kho cho cc vng lp ca DES .
Control.vhd M t ton b hnh vi iu khin ca DES
Converter.vhd M t vic ly d liu Vo/Ra ca DES.
Bng 3.9: Danh sch cc tp tin ca modul DES.
Data_in[1..64]
En




Code DES
Clk
Reset
En/De
Key[1..64]
Data_out[1..64]

Hnh 3.9: Cu trc I/O ca DES trn cng c Quartus


74
Modul DES c tng hp t m t hot ng ca cc khi chc nng bng
VHDL (DES.vhd). M t khai bo modul DES mc cao nht (Top Level) bng
VHDL nh sau:
library ieee;
use ieee.std_logic_1164.all;
entity DES is port
( data_in : in std_logic_vector(1 to 64);
en_de : in std_logic;
En : in std_logic;
key : in std_logic_vector(1 TO 64);
clk : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 TO 64));
end DES;
architecture structural of DES is
component IP
component control;
component des16;
componet deskey;
component converter;
component FP;
end structural;

M t modul DES mc cao ngoi vic khai bo cu trc ca modul chng ta
phi xy dng cc thnh phn chc nng trong modul:
- Khi cc php hon v.
- Khi control.
- Khi des16 (bao gm des1).
- Khi deskey.
- Khi converter.
3.3.3.1. Khi cc php hon v.
Php hon v IP: D liu u vo Data_in [1..64] c hon v IP sau chia
thnh hai phn L
0
[1..32] v R
0
[1..32]. Tham s ca php hon v IP c m t
trong bng 3.1. Thc cht ca php hon v c thc hin bng phn cng chnh l
vic kt ni v tr cc dy tn hiu theo tham s ca php hon v.



75
M t php hon v IP bng VHDL nh sau:
32
64 32
64
Data_in
Hon v IP
R
0
L
0

Hnh 3.10: S thc th php hon v IP
library ieee;
use ieee.std_logic_1164.all;
entity ip is port
( data_in: in std_logic_vector(1 TO 64);
l
0
: out std_logic_vector(1 TO 32);
r
0
: out std_logic_vector(1 TO 32));
end ip;
architecture behavior of ip is
begin
l
0
(1)<=data_in(58); sp xp v tr ca cc dy tn hiu theo php hon v
IP. Tc l dy tn hiu th 58 ca data_in c gn cho dy tn hiu th 1 ca l
0.
....
r0x(32)<=data_in(7); dy tn hiu th 7 ca data_in c gn cho dy tn
hiu th 32 ca r
0
.
end behavior;

Cc php hon v FP, PC-1, PC-2, P c thc hin tng t nh IP.
3.3.3.2. M t khi DES16
Khi des16 l thnh phn chnh ca modul DES vi 16 vng lp. Ti u vo d
liu c rng l 64 bt c chia thnh 2 phn, cc thanh ghi c to ra t cc
Triger D ca FPGA L
0
[1..32] v R
0
[1..32] s dng nhn d liu u vo sau
hon v IP ng thi cng l vng m d liu t u ra ca cc vng lp quay v.
Ti u ra, 2 thanh ghi L
i
[1..32] v R
i
[1..32] cng c s dng lu gi kt qu
v quay tr v u vo sau mi vng lp do khi iu khin tc ng, ng thi l
vng m d liu ca vng lp th 16 trc khi qua php hon v FP.



76

reset
Clk
Kho m
Lo Ro

16 vng lp
iu khin
Li
Ri
IP
FP
Hnh 3.11: M t 16 vng lp ca DES
Cc vng lp ca DES c cu trc c bn ging nhau, v vy mt vng lp ca
DES s c m t trong tp tin des1.vhd.

6 4
S1
Key
32
S2
S8

EP

P
.
.
.
.

XOR1

XOR2
6 4
6 4
32
32
48 32
48
R
i
L
i

Reg_L
Reset
Clk
Lo
Ro
32
32

Reg_R
Hnh 3.12 : S thit k ca mt vng lp.


77
M t mt vng lp ca DES c trnh by trong phn 3.2.2 gm cc php
ton nh sau:
EP : Hm m rng d liu ca R
i
t 32 bt thnh 48 bt.
XOR1 : Php cng modul 2 gia kho K
i
v d liu u ra ca hm EP.
S-BOX : Cc hp th.
P : Hon v d liu u ra ca cc hp S-BOX.
XOR2 : Php cng modul 2 gia kt qu ca P v L
i
.
Cc thnh phn khi mu xm trong s to nn hm F ca DES.
M t khai bo cu trc ca khi des1 v cc hm trong vng lp bng VHDL
nh sau:
entity des1 is port
( clk : in std_logic;
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32);
key : in std_logic_vector(1 to 48);
lo,ro : out std_logic_vector(1 to 32));
end round;
architecture behaviour of des1 is
M t tn hiu kt ni gia cc hm trong des1.
signal e : std_logic_vector(1 to 48);
signal b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: std_logic_vector(1 to 6);u vo ca 8 hp th.
signal so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x
: std_logic_vector(1 to 4); u ra ca 8 hp th.
signal ppo,r_toreg32,l_toreg32 : std_logic_vector(1 to 32);
M t cu trc hm des1 bao gm.
component ep
component xor1
component sbox1
...
component sbox8
component p
component xor2
component reg32
end;


78
a) Hm EP: 32 bt d liu ti thanh ghi bn phi R
i
[1..32] c m rng thnh
48 bt theo tham s m t bng 3.3; kt qu chuyn ti e[1..48]. Thc hin php
m rng d liu c th c m t nh sau:
entity ep is port
( ri : in std_logic_vector(1 to 32);
e : out std_logic_vector(1 to 48));
end ep;
architecture behavior of ep is
begin
e(1)<=ri(32); e(47)<=ri(32); ly ni dung ca v tr th 32 trong thanh
ghi R
i
gn vo v tr s 1 v v tr s 47 ca e.
....
end behavior;

b) Hm XOR1: Thc hin cng modul 2 gia kho trong thanh ghi K[1..48] v
d liu chuyn n qua e[1..48], kt qu a vo 8 hp S-BOX theo th t v tr cc
bt d liu: [1..6] vo hp S-BOX1; [7..12] vo hp S-BOX2;... ; [43..48] vo hp
S-BOX8.
M t cu trc ca XOR1 bng VHDL nh sau:
entity xor1 is port
( e : in std_logic_vector(1 to 48);
b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: out std_logic_vector (1 to 6);
k : in std_logic_vector (1 to 48));
end xor1;
architecture behavior of xor1 is
signal XX : std_logic_vector( 1 to 48);
begin
XX<=k xor e;
b1x<=XX(1 to 6); bt [1..6] a vo hp th s 1.
b2x<=XX(7 to 12);
....
b8x<=XX(43 to 48); bt [43..48] a vo hp th s 8.
end behavior;

Hm XOR2 cng c m t tng t nh hm XOR1.
c) Hp th S-BOX: C 8 hp S-BOX trong mi vng ca DES, cu trc mt hp


79
S-BOX c m t nh hnh 3.13. Trong FPGA chng ta s dng cc bt ROM
lu cc tham s ca cc hp S-BOX.
u vo d liu b l xu bt c di 6, qua hp th d liu ti u ra S
1
l
xu bt c di 4.
4 6
b S-BOX1
S
1

Hnh 3.13 : S thc th hp S-BOX
M t hp th S-BOX1 bng VHDL.
entity sbox1 is port
( b : in std_logic_vector(1 to 6);
s1 : out std_logic_vector(1 to 4));
end sbox1;
architecture behaviour of sbox1 is
begin
process(b)
begin
case b is
when "000000"=> s1<=To_StdLogicVector(Bit_Vector'(x"e"));
S dng To_StdLogicVector chuyn i kiu d liu ca xe c xc nh
bi hng, ct a vo S
1
[1..4]

;

when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
...
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end;

Cc hp th S-BOX2,..., S-BOX8 cng c thc hin tng t nh S-BOX1.
M t tham s ca cc hp th c trnh by trong bng 3.4.


d) Hon v P: Thc hin hon v d liu ti u ra ca cc hp th theo tham s
m t bng 3.5; phng php thc hin tng t nh hon v IP c trnh by
trn.


80
3.3.3.3. Khi deskey (tnh ton kho).
S tnh kho c m t trn hnh 3.14. Nhim v ca khi deskey l tnh
ton kho cho 16 vng lp ca DES mi kho con c di 48 bt t 56 bt c kho
ng (64 bt kho u vo loi b 8 bt kim tra chn l) .



key_in
56 56
PC-1
Dch vng
LS
i

PC-2
Lp 16 ln
C
0


D
0
key_out(K
i
)
48
64
Hnh 3.14: S khi to kho con.
M t cu trc ca khi tnh kho con bng VHDL nh sau:

entity deskey is port
( key_in : in std_logic_vector(1 to 64);
shift : in std_logic_vector(1 to 3);
clk : in std_logic;
key_out: out std_logic_vector(1 to 48));
end deskey;
architecture behaviour of deskey is
signal c,d,c1,d1 : std_logic_vector(1 to 28);
component pc1; php hon v PC-1.
component shifter; php dch vng tri.
component pc2; php hon v PC-2.
M t cch thc ni dy tn hiu gia cc thnh phn trong khi tnh kho
begin
pc_1: pc1 port map ( key=>key_in, c0x=>c, d0x=>d );
shifter_comp: shifter port map ( datac=>c, datad=>d, shift=>shift,
clk=>clk, datac_out=>c1, datad_out=>d1 );
pc_2: pc2 port map ( c=>c1, d=>d1, k=>ki );
end behaviour;



81
a) Khi PC-1, PC-2: T 64 bt kho vo cho trc, loi b 8 bt kim tra tnh
chn l v hon v 56 bt cn li theo php hon v c nh PC-1 theo tham s m t
bng 3.6 v php hon v PC-2 theo tham s m t bng 3.7.
b) Khi dch vng: 56 bt kho sau hon v PC-1 c chia lm hai phn
C
0
[1..28] v D
0
[1..28], sau mi phn C
0
v D
0
c dch vng sang tri mt hoc
hai v tr tu theo tng vng kho con c th do khi control iu khin, kt qu
c chuyn ti C
i
, D
i
a ti php hon v PC-2 to thnh kho con K
i
c di
xu bt l 48, ng thi ni dung ca C
i
, D
i
li c quay tr v u vo php dch
vng tnh kho con tip theo.
3.3.3.4. Khi Control (iu khin)
Nhim v chnh ca khi iu khin l:
- iu khin vic vo/ra d liu: Bn r, bn m v kho.
- iu khin thc hin 16 vng lp ca DES vi cc kho K
1
,...,K
16
trong ch
m ho v K
16
,...,K
1
trong ch gii m.
- iu khin vic tnh ton kho.
S dng 3 bt th hin cc trng thi trong php dch vng tri mt hoc hai v
tr v ly kho ca khi iu khin tnh ton kho :

Gi tr cc bt M t chc nng
000 Khng dch vng tri; khng ly kho mi.
001 Khng dch vng tri; ly kho mi.
010 Dch vng tri 1 v tr; khng ly kho mi.
011 Dch vng tri 1 v tr; ly kho mi.
100 Dch vng tri 2 v tr; khng ly kho mi.
101 Dch vng tri 2 v tr; ly kho mi.
Khc Bo li

Cc trng thi iu khin vic tnh ton kho nh sau:
Init (trng thi ban u): Ly kho mi, dch vng tri mt v tr.
State 1 : Dch vng tri mt v tr.


82
State 2,3,4,5,6,7 : Dch vng tri hai v tr.
State 8 : Dch vng tri mt v tr.
State 9,10,11,12,13,14 : Dch vng tri hai v tr.
State 15 : Dch vng tri mt v tr.
State 16 : Dng.
mi trng thi iu khin mt kho con s c sinh ra phc v cho tc v
m ho - gii m ca mi vng lp tng ng.
3.3.3.5. Khi Converter (ly d liu vo/ra)
Khi converter c nhim v ly d liu vo hoc ra. V nguyn tc, d liu
vo/ra c th a song song hoc ni tip ph thuc yu cu ca mt bi ton c th
no .
Vi phng thc a d liu vo song song 64 bt c th gim c s chu k
xung nhp cho mt qu trnh m ho/gii m mt khi d liu. Tuy nhin phng
thc ny i khi li ph thuc vo dung lng cng lgc v s chn vo/ra ca
FPGA. V d: EP20K100TC144-3 c 144 chn vo/ra trong 95 chn dnh cho
ngi s dng.
Gi s vic ly d liu vo/ra bao gm:
- 64 bt cho d liu r vo.
- 64 bt cho kho vo.
- 1 bt cho reset.
- 1 bt cho clock.
- 1 bt cho chn ch m ho/gii m.
- 64 bt cho d liu m ra.
Nh vy tng s chn vo/ra phi dng s l: 195 chn, ln hn nhiu so vi
s chn ca mch EP20K100TC144-3 chn la a vo s dng trong qu trnh
thit k.
Vi phng thc ni tip th ngc li, s dng s chn vo/ra t hn v tit
kim s cng lgc nhng s chu k xung nhp dnh cho mt qu trnh m ho/gii
li cn nhiu hn v vy tc m ho/gii m chm hn.



83

Clk

Converter
unload
load
64 16
Data_in Data_out
Hnh 3.15: M t khi vo/ra d liu
Trong thc t, cn phi quan tm n vic kt hp c hai phng thc ly d
liu vi nhau nhm m bo tnh ti u ca thit k, t la chn linh kin phn
cng thch hp cho ng dng. minh ho cho mt phng n thit k thc t, khi
64 bt d liu c ly thnh 4 ln ni tip nhau, mi ln ly song song 16 bt.
Nh vy s cn 4 chu k xung nhp cho vic ly 64 bt d liu. Hnh 3.15 minh ho
cho v d ny, trong tn hiu load; unload iu khin vic ly d liu.
3.3.3.6. Tng hp cc khi chc nng ca modul DES

Key [1:16]
Data_int
clk
reset
Control_unit
Control
Load_cl
Load_key
Clk Load_pl
Reset Output_clk
Shit [1:3]
Unload_pl
Unload_key
Converter data
Clk
Input Output [1..64]
load
Unload
converter
datapath
Clk
Load_cl
0nput_cl C[1:64]
Data_in [1:64]
reset
xkey[1:48]

Enciph
Des16
Converter_key
Clk
Input[1:16] Output[1:64]
load
Unload
converter
Key_proc
Clk
shit1:3] kl[1:48]
lhe_key[1:64]
Enciph
deskey
En/De
Data_out
Hnh 3.16: S lin kt gia cc khi trong modul DES
Khi cc khi chc nng trong DES c m t xong, cn phi tin hnh lin kt
cc khi vi nhau.


84
C 2 phng php thc hin chnh:
- S dng ch Block Diagram trong Quartus.
- S dng mt m t bng ngn ng m t phn cng VHDL.
3.3.3.7. Kim tra thit k
a) Kim tra thit k bng chng trnh m phng Waveform Edit:
Sau mi bc thit k chng trnh, vic kim tra s hot ng ca khi chc
nng vi mc ch khng nh tnh ng n ca thit k theo cc yu cu t ra c
th thc hin nh s tr gip bi chng trnh Waveform Edit ca cng c Quartus
II vi vic cho b tham s vc t u vo m phng, sau khi chy chng trnh
Simulation u ra s thu c kt qu. Nu vic thit k cha t cc yu cu ny,
ngi thit k bt buc phi quay li kim tra tng bc trong qu trnh thit k.
Vic kim tra DES c th thc hin theo phng php Test Vector c trnh
by trong 3.3.5.
b) Kim tra thit k trn phn cng:
Np chng trnh c bin dch cho phn cng v tin hnh kim tra phn
tch trc tip trn phn cng theo phng php Test Vector.
3.3.4. Phn cng m phng module DES
module DES thit k trn FPGA c th hot ng c c lp, cn phi
thit k mt bng mch ph tr theo s hnh 3.17:
3.3.4.1. Khi x l chnh (m ho/gii m)
y l phn chnh thc thi ton b cc hot ng ca modul m khi. Ton b
chng trnh thit k thut ton DES v cc chc nng khc ca modul bng ngn
ng m t phn cng sau khi qua cc giai on ca trnh bin dch, ti u, t v
nh ng, kim tra s c np v thc hin trn cho FPGA. Vic chn linh kin
FPGA hon ton ph thuc vo cc yu cu ca mt nhim v c th. V d: Cc
yu cu v tc x l phi p ng c tc d liu ca ng dng, s chn
vo/ra tn hiu ph thuc vo phng thc ly d liu vo/ra, s lng cc cng
logic ca linh kin phi m bo tng ng vi s lng cc cng logic ca chng
trnh thit k, gi thnh sn phm...


85
EN
M ho/Gii m

FPGA

d
liu
ra
kho
m
Reset
En/De
to xung
nhp

d
liu
vo
Ic cu
hnh
Cp mv

Hnh 3.17: S khi phn cng ca modul m khi DES
3.3.4.2. Khi cu hnh cho FPGA
Vic cu hnh cho FPGA c thc hin theo hai giai on.
- Giai on 1: Np mm dng cho vic kim tra kt qu trong tng giai on
hoc ton b qu trnh thit k. Vi mi khi chc nng c chia ra trong qu trnh
thit k modul ngoi vic kim tra s hot ng ca khi bng chng trnh m
phng Vector Waveform File ca cng c Quartus II nh trnh by trong phn
3.3.3.7, ngi thit k c th kim tra s hot ng ca cc khi bng cch np cu
hnh ca khi thng qua cp ByteBlasterMV (MV) ra thit b phn cng phn
tch xem hot ng ca khi c ng so vi yu cu cha. Nu khi chc nng hot
ng cha ng yu cu th quay li kim tra thit k. Cu hnh ny trong phn cng
s b xo khi tt ngun nui.


86

Hnh 3.18: S ghp ni gia FPGA v cp MV
- Giai on 2: Np cng sau khi kim tra ton b hot ng ca modul
theo ng yu cu thit k, ngi thit k tin hnh np cu hnh cho phn cng
bng thit b np trnh ALL-11C. IC lu gi cu hnh c chn phi ph hp
vi linh kin FPGA.


Hnh 3.19: S ghp ni gia FPGA v linh kin cu hnh
3.3.4.3. Cc phn mch khc.
- Mch to xung nhp: To xung Clock cung cp cho ton b modul.
- Khi ngun c thit k cho ra cc ngun in p DC +5V; +2,5V; +3,3V
cung cp cho cc vi mch.
3.3.5. Kim tra s hot ng ca DES trong modul m khi
Vic thit k module m khi DES, cng nh cng ho cc thut ton phc tp
khc trn cng ngh FPGA phi tr li mt cu hi: liu vi mch FPGA thit k


87
c hot ng ng nh m t l thuyt ca thut ton? kim tra tnh ng n
ca thit b phn cng thit k, ngi ta thng thc hin bng phng php kim
tra theo vector (test vector)[17], trong mi vector l mt b thng tin bao gm:
thng tin u vo, thng tin cn x l v thng tin kt qu, tu theo tng thut ton
phi nh gi. Nhng vector kim tra ny c ngi xy dng thut ton to ra
bng cng c l thuyt. Vic kim tra vector c thc hin theo hai phng php:
- Phng php kim tra vector c tnh sn kt qu KAT (Know Answer Test)
- Phng php kim tra vector ngu nhin (Monte - Carlo).
Trong hai phng php trn, KAT c s dng ph bin nht. C s ca Test
vector l cc gi tr vector kim tra c tnh ton sn. Sau khi cng b, phn ln
cc thut ton x l d liu c kh nng cng ho u c tnh trc cc vector
kim tra nhm to c s cho nh sn xut thit b x l d liu theo thut ton
kim tra thnh phm.
i vi thut ton DES, cc gi tr vector kim tra c cng b trong ti liu:
NIST Special Publication 800-17. Hai bng vector kim tra chnh l VPKAT
(Variable Plaintext Know Answer Test) v VKKAT(Variable Key Know Answer
Test).
Kim tra vi bn r bin i (VPKAT)
Qu trnh m ho c kim tra bng cch thc hin kim tra vi bn r bin
i, trong phn cng cn kim tra (ITU: Implemantation Under Test) s nhn cc
gi tr ca bn r cho trc trong vector u vo h thng kim tra (MOVS Modes
of Operation Validation System). Kho phin c t gi tr bng 1 nhng v tr
l.
Php kim tra VPKAT c thc hin nh sau:
1. MOVS thit lp:
a) Kho phin: Key=0101010101010101 (t parity l)
b) Bn r ban u: PT
1
=8000000000000000
c) Gi Key v PT
1
n IUT
2. IUT thc hin thut ton m ho d liu vi Key v gi kt qu cho MOVS.
3. MOVS so snh kt qu tnh ton trong IUT vi bn m c tnh sn.


88
Kim tra vi kho bin i (VKKAT)
Kim tra vi kho bin i c thc hin nh sau: ITU nhn c vector u
vo gm c gi tr kho thay i v gi tr bn r c nh l 0
Php kim tra vi kho bin i (VKKAT) c thc hin nh sau:
1. MOVS thit lp:
a) Kho phin: Key
1
= 800101010101010101
b) Bn r ban u: PT = 0000000000000000
c) Gi Key
1
v PT n IUT
2. IUT thc hin thut ton m ho d liu vi Key v gi kt qu ti MOVS
3. MOVS so snh kt qu thc hin ca IUT vi bng vector tnh trc.
3.4. kt qu thit k modul m khi des
3.4.1. Kt qu thit k trn thc t
Qu trnh xy dng v thit k modul m khi DES c thc hin trn c s
xy dng cc khi chc nng ca thut ton DES bng m t VHDL trong phn
3.3.3 v cc yu t v phn cng trong phn 3.3.4.
3.4.1.1. S phn cng ca modul
a) Modul DES: Trong modul s dng chp EP20K100TC144-3 thuc h APEX
20K ca ALTERA.
Nhng c im chnh ca chp EP20K100TC144-3 ca Altera:
EP20K100TC 144-3 cung cp 100.000 cng s dng, 144 chn vo ra trong
c 95 chn I/O dnh cho ngi s dng, 4406 thanh ghi, 53.248 bt RAM, ROM, s
dng ngun nui 2.5 VDC, lm vic vi xung nhp cao nht l 133 MHz. S chn
tn hiu ca EP20K100TC 144-3 c nu trong ph lc.
b) IC cu hnh: C th dng loi EPC1, EPC2... tu theo dung lng ca thit
b. Vi h linh kin APEX 20K ca Altera c th dng IC cu hnh loi EPC2LC 20.
File chng trnh DES.SOF c np cho EPC2LC20 bng b np ALL-11C.
EPC2 LC20 l mt loi SRAM c dung lng l 1.655 Kbt s dng ngun
nui l 5.0 V v 3.3 V.



89

Control
Control
+3,3V +5V +2,5V
Enciph
Reset
MOdul des

Apex20k
Ep20k100tc144-3

d
liu
ra

74LS373

kho
m

d
liu
vo

74LS244
Bng
led
hin
th
t/h
vo
to xung
nhp Khi ngun
Bng
led
hin
th
t/h
ra
EPC2lc
20
Cp mv
Hnh 3.20: S khi phn cng ca modul m khi trn thc t.
Chc nng cc chn tn hiu vo/ra ca EPC2 LC20 c m t bng 3.10.
STT
Tn Vo/Ra M t
1 TDO Output Ni vi cp JTAG nu cp ny c s dng.
2 DATA Output D liu ra ni tip. D liu c cht ti y n
khi chn tn hiu nCS c mc cao th d liu s
c np cho linh kin FPGA.
3 TCK Input Chn nhp ca JTAG. Chn ny ni ti GND nu
nh cp JTAG khng c s dng.
5 VCCSEL Input Chn ch ngun cung cp Vcc. VCCSEL phi
c ni ti GND nu linh kin s dng ch
ngun cung cp l 5V v ni ti Vcc nu linh
kin s dng ch ngun cung cp l 3.3V.



90
8 OE(3) Output OE=1 cho php a d liu vo linh kin,
OE=0 reset li b m.
9 nCS(3) Input Vo chn chp cu hnh khi phi dng nhiu IC
cu hnh cho mt linh kin FPGA.
10 GND t Chn ni t. Ni t in 0.2mF lc ngun
gia Vcc v GND.
11 TDI Input Chn vo d liu ca mch JTAG. Khng c
ni chn ny nu nh mch JTAG khng c
s dng.
12 nCASC Output Ni ti chn nCS ca IC cu hnh tip theo nu
nh trong mch dng nhiu hn mt IC cu
hnh.
13 nINIT_CONF(3) Output Chn tn hiu ny c ni vi nCONFIG ca
linh kin FPGA t IC cu hnh qua cp JTAG
14 VPPSEL Input Tng t nh chn s 5
18 VPP Power Cung cp ngun. Vi EPC2 chn ny c ni
ti Vcc.
19 TMS Input Chn ch JTAG. Ni chn ny ti Vcc nu
nh mch JTAG khng s dng.
20 VCC Power Cung cp ngun.
Bng 3.10: Chc nng cc tn hiu vo/ra ca EPC2 LC 20
Ch : (3) Cc chn OE, nCS, v nINIT_CONF trn EPC2 khi s dng ni mt
in tr 1K vi Vcc.
c) Mch cht d liu vo/ra: D liu vo/ra c th c thit k dng ni tip
hay song song tu thuc vo h thng truyn tin c th c chn lm i tng
ghp ni. Trong thit k modul thun tin cho vic m phng tn hiu, mch cht
d liu c thit k ring, s dng vi mch 74LS 244 cng vi 8 cm chuyn mch
(mi cm c 8 chuyn mch ) to ra 64 bt d liu m phng cho tn hiu u
vo, vi mch 74LS 373 cht 64 bt d liu u ra hin th ra LED, cc tn hiu iu
khin (control) c a ra t chp FPGA nhm iu khin vic ly d liu vo/ra.
thun tin cho qu trnh m phng, kho m c np sn trong modul m khi.


91
d) Bng n LED hin th: Dng trong qu trnh m phng mc ch l ch th
cc bt d liu u vo v u ra. LED trng thi sng ch th cho mc lgc
1 v trng thi tt ch th cho mc lgc 0.
e) Mch to xung nhp: To xung Clock cung cp cho ton b modul vi tn s
hot ng 24MHz.
f) Khi ngun: c thit k cho ra cc ngun in p DC +5V; +2,5V; +3,3V
cung cp cho cc vi mch.

Hnh 3.21: Hnh nh modul m khi DES c thit k
3.4.1.2. Kim tra kt qu thit k
Module DES, sau khi c cng ho bng cng ngh FPGA, c kim tra
theo phng php Test vector nhm kim chng tnh ng n trong hot ng trn
chp FPGA. Sau khi kim tra tng vector theo hai bng vector kim tra, module DES
cho kt qu ng nh tnh ton l thuyt, chng t hot ng ca modul DES
trn FPGA hon ton chnh xc.


92
3.4.2. nh gi kt qu thit k modul m khi
Cn c vo cc yu cu i vi modul m khi, vic thit k m phng modul
m khi vi thut ton DES, s dng chp EP20K100TC 144-3 t c cc kt
qu nh sau:
- thit k ch to 2 modul m khi vi thut ton DES trn cng ngh FPGA.
- Ton b thut ton DES c thit k ng gi trn chp FPGA, hot ng
chnh xc so vi m t v l thuyt, m bo c cc yu cu v kt cu vt l v
tnh n nh khi hot ng.
- V tc m ho/gii m d liu: Phng php thit k trn s dng s chu k
xung nhp cho mt qu trnh m ho l 24, trong 8 chu k dnh cho ly d liu v
kho, 16 chu k dnh cho 16 vng lp, d liu ra c ly song song 64 bt. Nh
vy vi xung nhp 24 MHz, d liu u vo m ho 64 bt th tc m ho d liu
tnh theo l thuyt l:(24 MHz/s * 64bt)/24 = 64Mbt/s. Vi cc loi chp FPGA
khc nhau s hot ng vi cc tc xung nhp khc nhau. Chp
EP20K100TC144-3 lm vic vi xung nhp cao nht l 133 MHz, nh vy tc
m ho d liu tnh theo l thuyt s t: (133MHz/s * 64 bt) / 24 355 Mbt/s.
- V hiu sut s dng chp FPGA: S cng logc s dng cho thit k l (tnh
theo %): 67.740 gate/100.000 gate = 67,74%. S chn tn hiu vo/ra s dng cho
thit k l: 83/95 87%.
Trong thc t nhiu h thng truyn tin hin i c tc truyn d liu rt
ln v vy t c tc m ho/gii m d liu cao hn, c th s dng hng
thit k theo phng php ng ng (pipeline). Thay v x l mt khi d liu
trong mt thi im, thit k pipeline c th x l hai hay nhiu khi d liu trong
cng mt thi im. Thut ton DES vi 16 vng lp, thit k pipeline y s
c to ra bi pipeline 16 tng. Phng php ny cho tc x l d liu tng mt
cch ng k, tuy nhin s cng logc s dng cng tng rt nhiu c ngha rng
phi dng chp FPGA c s lng cng lgc ln.
Khi thit k modul m khi bo mt cho mt ng dng c th, ngi thit
k s phi xc nh mt cn cho ng dng, tnh ton v la chn chp FPGA
thch hp v tc x l d liu, hiu sut s dng chp...


93
Kt lun

Bo mt tin tc lun l mt nhu cu cn thit v cp bch i vi cc h thng
truyn tin, c bit trong lnh vc an ninh, quc phng. H thng truyn tin cng
hin i th vic tch hp cc gii thut mt m cng kh v lun l thch thc t ra
i vi k thut trong iu kin nn khoa hc v cng ngh ca Vit nam cn c
nhiu mt hn ch. Vi nhu cu bo mt cho cc h thng truyn tin tc ln,
hng ti chuyn dng ho thit b bo mt tnh ch ng, c lp trong cc thit
b mt m ngy cng cao th vic to ra mt cu trc vt l s dng m khi trong
x l mt thng tin trn cng ngh FPGA l mt gii php u vit hin nay. y l
mt hng nghin cu, c kh nng p dng ph hp vi iu kin thc t v cng
ngh v yu cu s dng Vit Nam .
Qua thi gian nghin cu lun vn hon thnh c nhim v, mc tiu t
ra v t c nhng kt qu chnh nh sau:
trnh by tng quan v m hnh v cc gii php bo mt trong h thng
truyn tin mt, nhng vn c bn nht v nguyn l thit k v cu trc ca mt
h m khi. Qua nghin cu, kho st v phn tch la chn c thut ton m
khi c cu trc Fiestel l mt cu trc ht sc c bn v thun li cho vic cng
ha trn cc cng c phn cng.
Phn tch u, nhc im ca cc k thut thit k m khi, v la chn thit
k modul m khi trn cng ngh FPGA. T trnh by tng quan v cng ngh
FPGA, gii thiu mt cch khi qut v s pht trin ca linh kin lp trnh c,
quy trnh thit k mt sn phm trn cng ngh FPGA, mt s c im tm tt ca
cc ngn ng m t phn cng trong i su m t c bn v ngn ng m t phn
cng VHDL l ngn ng c dng trong qu trnh thit k modul m khi.
Vi cng ngh FPGA v cc thut ton m khi kho st, lun vn la
chn chun m d liu DES cho vic thit k m phng modul m khi nhm chng
minh v kh nng cng nh cch thc tin hnh khi thit k mt h m khi trn
cng ngh FPGA. nghin cu thit k ch to thnh cng hai modul m khi vi
thut ton DES trn cng ngh FPGA v th nghim trn thc t.


94
Bng kt qu nh trn hon ton c th thit k modul m khi vi nhng thut
ton m khi khc, phn cng c thit k c th p ng cho nhng thut ton
m khi c dung lng v tc tnh ton tng ng nh s linh hot, mm do
trong thit k ca cng ngh FPGA.
Trn c s kt qu nghin cu t c ca lun vn, c th tip tc pht
trin theo cc hng sau:
S dng k thut ng ng (pipeline) trong thit k thut ton m khi trn
cng c phn cng nhm nng cao tc x l d liu.
Nghin cu p dng vn v trao i kho gia cc modul m khi trong h
truyn tin mt.
Thit k thit b bo mt vi thut ton m ho ca Vit Nam v tch hp cho
h thng truyn tin mt c th.
Mt ln na ti xin chn thnh cm n PGS.TS Xun Tin, cng cc thy
gio khoa V tuyn in t - HVKTQS, cm n cc ng nghip cng tc ti Cc
C yu - BTTM to iu kin, gip ti trong qu trnh hc tp v hon thnh
lun vn.
















95
Ti liu tham kho

Ting Vit

1. Nguyn Bnh (1996), Mt m: L thuyt v thc hnh, Hc vin k thut qun
s, H Ni.
2. Ban C yu Chnh ph (2004), C s mt m hin i, H Ni.
3. Nguyn Tng Cng, Phan Quc Thng (2003), Cu trc v lp trnh cc h
x l tn hiu s, NXB Khoa hc v k thut, H Ni.
4. ng Vn Chuyt, Nguyn Tun Anh (2001), C s l thuyt truyn tin,
NXB Gio dc, H Ni.
5. Nguyn Minh c (2004), B vi x l thit k bng my tnh cc h thng k
thut s, NXB Tng hp TP. H Ch Minh.
6. H Trung M (2002), VHDL v thit k s, i hc Bch khoa thnh ph H
Ch Minh.

Ting Anh

7 A.J.Menezes, P.C.Van Oorschot, S.A.Vanston (1997), Handbock of applied
cryptography, CRC Press 1997.
8.
Altera Corporation (1997), MAX+PLUS II: Programmable Logic
Development System, United States of America.
9. Altera Corporation (1997), Quartus II, United States of America.
10. Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu, Steve Y-L Lin (1992),
High-Level Synthesis Introdution to Chip and System Design,
11. Douglas R. Stinson (1995), Crytography: Theory And Practice, CRC Press, Inc.
12. Don Davis (Winter 2002), Architectural Synthesis: Unleashing the Power of
FPGA System-Level Design, Xcell Journal, (Issue 44), pages 30 34, Xilinx,
United States of America.
13. Giovanni De Micheli, Rajesh K. Gupta (3/1997), Hardware/Software


96
Co-Design, Proceedings of the IEEE, (Vol. 85, No 3), pages 349 - 364.
14. Michael John Sebastian Smith (1997), Application-Specific Integrated
Circuits, Hardcover (www.Amazon.com), United States of America.
15. Peter J.Ashenden (1990), The VHDL CooKBook, University of Adelaide,
South Australia.
16. Roger Lipsett & Carl Schaefer (1989), VHDL: Hardware Description and
Design, Kluwer Academic Publishers, United States of America.
17 Sharon Keller, Miles Smid (2/1998), NIST Special Publication 800-17,
U.S. Department of Commerce.
18. Ngun tham kho t Internet
- www.altera.com
- www.actel.com
- www.intel.com


















I
PH LC 1
Quartus II Version 4.2 Build 157 04/05/2005 SJ Full Version
CHIP "DES" ASSIGNED TO AN: EP20K100TC144-3

Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCC_INT : 1 : power : : 2.5V : :
DataIn[0] : 2 : input : LVTTL/LVCMOS : : : Y
DataIn[1] : 3 : input : LVTTL/LVCMOS : : : Y
GND : 4 : gnd : : : :
DataIn[2] : 5 : input : LVTTL/LVCMOS : : : Y
DataIn[3] : 6 : input : LVTTL/LVCMOS : : : Y
DataIn[4] : 7 : input : LVTTL/LVCMOS : : : Y
DataIn[5] : 8 : input : LVTTL/LVCMOS : : : Y
DataIn[6] : 9 : input : LVTTL/LVCMOS : : : Y
DataIn[7] : 10 : input : LVTTL/LVCMOS : : : Y
cs[0] : 11 : output : LVTTL/LVCMOS : : : Y
GND_IO : 12 : gnd : : : :
cs[1] : 13 : output : LVTTL/LVCMOS : : : Y
cs[2] : 14 : output : LVTTL/LVCMOS : : : Y
cs[3] : 15 : output : LVTTL/LVCMOS : : : Y
VCC_INT : 16 : power : : 2.5V : :
GND : 17 : gnd : : : :
MSEL0 : 18 : input : : : :
MSEL1 : 19 : input : : : :
GND+ : 20 : : : : :
VCC_INT : 21 : power : : 2.5V : :
NCONFIG : 22 : input : : : :
cs[4] : 23 : output : LVTTL/LVCMOS : : : Y
cs[5] : 24 : output : LVTTL/LVCMOS : : : Y
cs[6] : 25 : output : LVTTL/LVCMOS : : : Y
cs[7] : 26 : output : LVTTL/LVCMOS : : : Y
GND* : 27 : : : : :
VCC_IO : 28 : power : : 3.3V : :
GND* : 29 : : : : :
GND* : 30 : : : : :
GND* : 31 : : : : :
GND* : 32 : : : : :
GND* : 33 : : : : :
GND : 34 : gnd : : : :
GND* : 35 : : : : :
VCC_INT : 36 : power : : 2.5V : :
res_out[0] : 37 : output : LVTTL/LVCMOS : : : Y
res_out[1] : 38 : output : LVTTL/LVCMOS : : : Y
res_out[2] : 39 : output : LVTTL/LVCMOS : : : Y
res_out[3] : 40 : output : LVTTL/LVCMOS : : : Y
res_out[4] : 41 : output : LVTTL/LVCMOS : : : Y
GND_IO : 42 : gnd : : : :
res_out[5] : 43 : output : LVTTL/LVCMOS : : : Y
res_out[6] : 44 : output : LVTTL/LVCMOS : : : Y
res_out[7] : 45 : output : LVTTL/LVCMOS : : : Y


II
res_out[8] : 46 : output : LVTTL/LVCMOS : : : Y
res_out[9] : 47 : output : LVTTL/LVCMOS : : : Y
res_out[10] : 48 : output : LVTTL/LVCMOS : : : Y
res_out[11] : 49 : output : LVTTL/LVCMOS : : : Y
res_out[12] : 50 : output : LVTTL/LVCMOS : : : Y
TMS : 51 : input : : : :
TCK : 52 : input : : : :
Clk : 53 : input : LVTTL/LVCMOS : : : Y
GND : 54 : gnd : : : :
VCC_INT : 55 : power : : 2.5V : :
GND+ : 56 : : : : :
STATUS : 57 : bidir : : : :
CONF_DONE : 58 : bidir : : : :
res_out[13] : 59 : output : LVTTL/LVCMOS : : : Y
res_out[14] : 60 : output : LVTTL/LVCMOS : : : Y
VCC_IO : 61 : power : : 3.3V : :
res_out[15] : 62 : output : LVTTL/LVCMOS : : : Y
res_out[16] : 63 : output : LVTTL/LVCMOS : : : Y
res_out[17] : 64 : output : LVTTL/LVCMOS : : : Y
res_out[18] : 65 : output : LVTTL/LVCMOS : : : Y
res_out[19] : 66 : output : LVTTL/LVCMOS : : : Y
res_out[20] : 67 : output : LVTTL/LVCMOS : : : Y
res_out[21] : 68 : output : LVTTL/LVCMOS : : : Y
res_out[22] : 69 : output : LVTTL/LVCMOS : : : Y
res_out[23] : 70 : output : LVTTL/LVCMOS : : : Y
res_out[24] : 71 : output : LVTTL/LVCMOS : : : Y
GND_IO : 72 : gnd : : : :
VCC_INT : 73 : power : : 2.5V : :
GND : 74 : gnd : : : :
res_out[25] : 75 : output : LVTTL/LVCMOS : : : Y
res_out[26] : 76 : output : LVTTL/LVCMOS : : : Y
GND : 77 : gnd : : : :
res_out[27] : 78 : output : LVTTL/LVCMOS : : : Y
res_out[28] : 79 : output : LVTTL/LVCMOS : : : Y
res_out[29] : 80 : output : LVTTL/LVCMOS : : : Y
res_out[30] : 81 : output : LVTTL/LVCMOS : : : Y
res_out[31] : 82 : output : LVTTL/LVCMOS : : : Y
res_out[32] : 83 : output : LVTTL/LVCMOS : : : Y
res_out[33] : 84 : output : LVTTL/LVCMOS : : : Y
VCC_CKLK : 85 : power : : 2.5V : :
VCC_INT : 86 : power : : 2.5V : :
GND : 87 : gnd : : : :
GND_CKLK : 88 : gnd : : : :
VCC_IO : 89 : power : : 3.3V : :
TDI : 90 : input : : : :
nCE : 91 : input : : : :
GND+ : 92 : : : : :
DCLK : 93 : bidir : : : :
DATA0 : 94 : input : : : :
res_out[34] : 95 : output : LVTTL/LVCMOS : : : Y
res_out[35] : 96 : output : LVTTL/LVCMOS : : : Y
res_out[36] : 97 : output : LVTTL/LVCMOS : : : Y
res_out[37] : 98 : output : LVTTL/LVCMOS : : : Y
res_out[38] : 99 : output : LVTTL/LVCMOS : : : Y


III
res_out[39] : 100 : output : LVTTL/LVCMOS : : : Y
res_out[40] : 101 : output : LVTTL/LVCMOS : : : Y
res_out[41] : 102 : output : LVTTL/LVCMOS : : : Y
res_out[42] : 103 : output : LVTTL/LVCMOS : : : Y
res_out[43] : 104 : output : LVTTL/LVCMOS : : : Y
res_out[44] : 105 : output : LVTTL/LVCMOS : : : Y
GND_IO : 106 : gnd : : : :
res_out[45] : 107 : output : LVTTL/LVCMOS : : : Y
VCC_INT : 108 : power : : 2.5V : :
res_out[46] : 109 : output : LVTTL/LVCMOS : : : Y
res_out[47] : 110 : output : LVTTL/LVCMOS : : : Y
res_out[48] : 111 : output : LVTTL/LVCMOS : : : Y
res_out[49] : 112 : output : LVTTL/LVCMOS : : : Y
res_out[50] : 113 : output : LVTTL/LVCMOS : : : Y
res_out[51] : 114 : output : LVTTL/LVCMOS : : : Y
res_out[52] : 115 : output : LVTTL/LVCMOS : : : Y
VCC_IO : 116 : power : 3.3V : :
res_out[53] : 117 : output : LVTTL/LVCMOS : : : Y
res_out[54] : 118 : output : LVTTL/LVCMOS : : : Y
res_out[55] : 119 : output : LVTTL/LVCMOS : : : Y
res_out[56] : 120 : output : LVTTL/LVCMOS : : : Y
res_out[57] : 121 : output : LVTTL/LVCMOS : : : Y
res_out[58] : 122 : output : LVTTL/LVCMOS : : : Y
TDO : 123 : output : : : :
GND+ : 124 : : : : :
VCC_INT : 125 : power : : 2.5V : :
GND : 126 : gnd : : : :
GND+ : 127 : : : : :
nCEO : 128 : output : : : :
TRST : 129 : input : : : :
res_out[59] : 130 : output : LVTTL/LVCMOS : : : Y
res_out[60] : 131 : output : LVTTL/LVCMOS : : : Y
res _out[61] : 132 : output : LVTTL/LVCMOS : : : Y
res _out[62] : 133 : output : LVTTL/LVCMOS : : : Y
GND_IO : 134 : gnd : : : :
res_out[63] : 135 : output : LVTTL/LVCMOS : : : Y
GND* : 136 : : : : :
En/De : 137 : input : LVTTL/LVCMOS : : : Y
GND* : 138 : : : : :
done : 139 : output : LVTTL/LVCMOS : : : Y
GND* : 140 : : : : :
GND* : 141 : : : : :
GND* : 142 : : : : :
rdy_to_ld : 143 : output : LVTTL/LVCMOS : : : Y
VCC_IO : 144 : power : : 3.3V : :







IV
Ph lc 2:
Chng trnh m t DES bng VHDL

DES.VHD

library ieee;
use ieee.std_logic_1164.all;
entity DES is port
( pt : in std_logic_vector(1 TO 16);
key : in std_logic_vector(1 TO 16);
clk : in std_logic;
reset : in std_logic;
ct : out std_logic_vector(1 TO 64)
);
end DES;
architecture structural of DES is
component control
port (
reset : in std_logic;
clk : in std_logic;
load_new_pt : out std_logic;
output_ok : out std_logic;
load_pt : out std_logic;
unload_pt : out std_logic;
load_key : out std_logic;
unload_key : out std_logic;
shift : out std_logic_vector(1 to 3)
);
end component;
component Des16
port (
pt : in std_logic_vector(1 TO 64);
xkey : in std_logic_vector(1 TO 48);
reset : in std_logic;
clk : in std_logic;
load_new_pt : in std_logic;
output_ok : in std_logic;
ct : out std_logic_vector(1 TO 64));
end component;
component deskey
port (
the_key : in std_logic_vector(1 to 64);
shift : in std_logic_vector(1 to 3);
clk : in std_logic;
ki : out std_logic_vector(1 to 48)
);
end component;


V
component converter
port (
input : in std_logic_vector(1 to 16);
load : in std_logic;
unload : in std_logic;
clk : in std_logic;
output : out std_logic_vector (1 to 64)
);
end component;
signal load_new_pt : std_logic;
signal output_ok : std_logic;
signal load_pt_sig : std_logic;
signal unload_pt_sig : std_logic;
signal load_key_sig : std_logic;
signal unload_key_sig : std_logic;
signal shift_sig : std_logic_vector(1 to 3);
signal ki_sig : std_logic_vector(1 to 48);
signal key_sig : std_logic_vector(1 to 64);
signal pt_sig : std_logic_vector(1 to 64);
begin
control_unit : control port map(reset=>reset, clk=>clk,
load_new_pt=>load_new_pt,output_ok=>output_ok,load_pt=>load_pt_sig,unload
_pt=>unload_pt_sig,load_key=>load_key_sig,unload_key=>unload_key_sig,
shift=>shift_sig );
converter_pt : converter port map ( input=>pt, load=>load_pt_sig,
unload=>unload_pt_sig, clk=>clk, output=>pt_sig );
converter_key : converter port map ( input=>key,
load=>load_key_sig,unload=>unload_key_sig,clk=>clk,
utput=>key_sig );
datapath : Des16 port map ( pt=>pt_sig, xkey=>ki_sig,
reset=>reset,clk=>clk,load_new_pt=>load_new_pt, output_ok=>output_ok,
ct=>ct );
key_proc : deskey port map ( the_key=>key_sig, shift=>shift_sig,
clk=>clk, ki=>ki_sig );
end structural;


IP.VHD

library ieee;
use ieee.std_logic_1164.all;
entity ip is port
( pt : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32));
end ip;
architecture behavior of ip is


VI
begin
l0x(1)<=pt(58);l0x(2)<=pt(50);l0x(3)<=pt(42);l0x(4)<=pt(34);
l0x(5)<=pt(26);l0x(6)<=pt(18);l0x(7)<=pt(10);l0x(8)<=pt(2);
l0x(9)<=pt(60);l0x(10)<=pt(52);
l0x(11)<=pt(44); l0x(12)<=pt(36);
l0x(13)<=pt(28); l0x(14)<=pt(20); l0x(15)<=pt(12); l0x(16)<=pt(4);
l0x(17)<=pt(62); l0x(18)<=pt(54); l0x(19)<=pt(46); l0x(20)<=pt(38);
l0x(21)<=pt(30); l0x(22)<=pt(22); l0x(23)<=pt(14); l0x(24)<=pt(6);
l0x(25)<=pt(64); l0x(26)<=pt(56); l0x(27)<=pt(48); l0x(28)<=pt(40);
l0x(29)<=pt(32); l0x(30)<=pt(24); l0x(31)<=pt(16); l0x(32)<=pt(8);
r0x(1)<=pt(57); r0x(2)<=pt(49); r0x(3)<=pt(41); r0x(4)<=pt(33);
r0x(5)<=pt(25); r0x(6)<=pt(17); r0x(7)<=pt(9); r0x(8)<=pt(1);
r0x(9)<=pt(59); r0x(10)<=pt(51); r0x(11)<=pt(43); r0x(12)<=pt(35);
r0x(13)<=pt(27); r0x(14)<=pt(19); r0x(15)<=pt(11); r0x(16)<=pt(3);
r0x(17)<=pt(61); r0x(18)<=pt(53); r0x(19)<=pt(45); r0x(20)<=pt(37);
r0x(21)<=pt(29); r0x(22)<=pt(21); r0x(23)<=pt(13); r0x(24)<=pt(5);
r0x(25)<=pt(63); r0x(26)<=pt(55); r0x(27)<=pt(47); r0x(28)<=pt(39);
r0x(29)<=pt(31); r0x(30)<=pt(23); r0x(31)<=pt(15); r0x(32)<=pt(7);
end behavior;

DES16.VHD

library ieee;
use ieee.std_logic_1164.all;
entity des16 is port
( pt : in std_logic_vector(1 TO 64);
xkey : in std_logic_vector(1 TO 48);
reset : in std_logic;
clk : in std_logic;
load_new_pt : in std_logic;
output_ok : in std_logic;
ct : out std_logic_vector(1 TO 64));
end des16;
architecture behavior of des16 is
component ip
port (pt : in std_logic_vector(1 TO 64);
l0x : out std_logic_vector(1 TO 32);
r0x : out std_logic_vector(1 TO 32));
end component;
component mux32
port ( e0 : in std_logic_vector (1 to 32) ;
e1 : in std_logic_vector (1 to 32) ;
o : out std_logic_vector (1 to 32) ;
sel : in std_logic );
end component;
component des1
port ( clk : in std_logic;


VII
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32);
k : in std_logic_vector(1 to 48);
lo,ro : out std_logic_vector(1 to 32));
end component;
component ov32
port ( e : in std_logic_vector (1 to 32) ;
o1 : out std_logic_vector (1 to 32) ;
o2 : out std_logic_vector (1 to 32) ;
clk : in std_logic;
sel : in std_logic );
end component;
component fp
port ( l,r : in std_logic_vector(1 to 32);
ct : out std_logic_vector(1 to 64));
end component;
signal left_in : std_logic_vector(1 to 32);
signal right_in : std_logic_vector(1 to 32);
signal mux_l_to_round : std_logic_vector(1 to 32);
signal mux_r_to_round : std_logic_vector(1 to 32);
signal round_l_to_ov : std_logic_vector(1 to 32);
signal round_r_to_ov : std_logic_vector(1 to 32);
signal ov_l_to_mux : std_logic_vector(1 to 32);
signal ov_r_to_mux : std_logic_vector(1 to 32);
signal ov_l_to_fp : std_logic_vector(1 to 32);
signal ov_r_to_fp : std_logic_vector(1 to 32);
begin
initial_p:ip port map (pt=>pt,l0x=>left_in,r0x=>right_in );
mux_left : mux32 port map (e0=>ov_l_to_mux, e1=>left_in,
o=>mux_l_to_round, sel=>load_new_pt );
mux_right: mux32 port map ( e0=>ov_r_to_mux,
e1=>right_in,o=>mux_r_to_round, sel=>load_new_pt );
round: des1 port map ( clk=>clk, reset=>reset,
li=>mux_l_to_round, ri=>mux_r_to_round, k=>xkey,
lo=>round_l_to_ov, ro=>round_r_to_ov );
ov_left: ov32 port map ( e=>round_l_to_ov, o1=>ov_l_to_mux,
o2=>ov_l_to_fp, clk=>clk, sel=>output_ok );
ov_right: ov32 port map ( e=>round_r_to_ov, o1=>ov_r_to_mux,
o2=>ov_r_to_fp, clk=>clk, sel=>output_ok );
final_p: fp port map ( l=>ov_r_to_fp, r=>ov_l_to_fp, ct=>ct );
end behavior;

DES1.VHD

library ieee;
use ieee.std_logic_1164.all;
entity des1 is port
( clk : in std_logic;


VIII
reset : in std_logic;
li,ri : in std_logic_vector(1 to 32);
k : in std_logic_vector(1 to 48);
lo,ro : out std_logic_vector(1 to 32));
end des1;
architecture behaviour of des1 is
signal e : std_logic_vector(1 to 48);
signal b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: std_logic_vector(1 to 6);
signal so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x
: std_logic_vector(1 to 4);
signal ppo,r_toreg32,l_toreg32 : std_logic_vector(1 to 32);
component xp
port ( ri : in std_logic_vector(1 TO 32);
e : out std_logic_vector(1 TO 48));
end component;
component desxor1
port ( e : in std_logic_vector(1 TO 48);
b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: out std_logic_vector (1 TO 6);
k : in std_logic_vector (1 TO 48) );
end component;
component sbox1
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox2
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox3
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox4
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox5
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox6
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component sbox7
port ( b : in std_logic_vector(1 to 6);


IX
so : out std_logic_vector(1 to 4));
end component;
component sbox8
port ( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end component;
component pp
port ( so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x
: in std_logic_vector(1 to 4);
ppo : out std_logic_vector(1 to 32));
end component;
component desxor2
port ( d,l : in std_logic_vector(1 to 32);
q : out std_logic_vector(1 to 32));
end component;
component reg32
port ( a : in std_logic_vector (1 to 32);
q : out std_logic_vector (1 to 32);
reset : in std_logic;
clk : in std_logic );
end component;
begin
xpension : xp port map(ri=>ri, e=>e );
des_xor1 : desxor1 port map (e=>e, k=>k, b1x=>b1x,
b2x=>b2x, b3x=>b3x, b4x=>b4x, b5x=>b5x, b6x=>b6x, b7x=>b7x, b8x=>b8x );
s1a: sbox1 port map (b=>b1x,so=>so1x);
s2a: sbox2 port map (b=>b2x,so=>so2x);
s3a: sbox3 port map (b=>b3x,so=>so3x);
s4a: sbox4 port map (b=>b4x,so=>so4x);
s5a: sbox5 port map (b=>b5x,so=>so5x);
s6a: sbox6 port map (b=>b6x,so=>so6x);
s7a: sbox7 port map (b=>b7x,so=>so7x);
s8a: sbox8 port map (b=>b8x,so=>so8x);
pperm: pp port map(so1x=>so1x,so2x=>so2x,so3x=>so3x, so4x=>so4x,
so5x=>so5x, so6x=>so6x, so7x=>so7x, so8x=>so8x, ppo=>ppo);
des_xor2: desxor2 port map(d=>ppo,l=>li,q=>r_toreg32);
l_toreg32<=ri;
register32_left: reg32 port map( a=>l_toreg32, q=>lo, reset=>reset,
clk=>clk );
register32_right: reg32 port map( a=>r_toreg32, q=>ro, reset=>reset,
clk=>clk );
end;

SBOX1

library ieee;
use ieee.std_logic_1164.all;


X
entity sbox1 is port
( b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4));
end sbox1;
architecture behaviour of sbox1 is
begin
process(b)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));


XI
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end;

DESKEY.VHD

library ieee;
use ieee.std_logic_1164.all;
entity deskey is port
( the_key : in std_logic_vector(1 to 64);
shift : in std_logic_vector(1 to 3);
clk : in std_logic;
ki : out std_logic_vector(1 to 48));
end deskey;
architecture behaviour of deskey is
signal c,d,c1,d1 : std_logic_vector(1 to 28);
component pc1
port ( key : in std_logic_vector(1 TO 64);
c0x,d0x : out std_logic_vector(1 TO 28));
end component;
component shifter
port ( datac : in std_logic_vector(1 to 28);
datad : in std_logic_vector(1 to 28);


XII
shift : in std_logic_vector(1 to 3);
clk : in std_logic;
datac_out : out std_logic_vector(1 to 28);
datad_out : out std_logic_vector(1 to 28));
end component;
component pc2
port ( c,d : in std_logic_vector(1 TO 28);
k : out std_logic_vector(1 TO 48));
end component;
begin
pc_1: pc1 port map ( key=>the_key, c0x=>c, d0x=>d );
shifter_comp: shifter port map ( datac=>c, datad=>d, shift=>shift,
clk=>clk, datac_out=>c1, datad_out=>d1 );
pc_2: pc2 port map ( c=>c1, d=>d1, k=>ki );
end behaviour;

converter.vhd

library ieee;
use ieee.std_logic_1164.all;
entity converter is port
( input : in std_logic_vector(1 to 16);
load : in std_logic;
unload : in std_logic;
clk : in std_logic;
output : out std_logic_vector (1 to 64));
end converter;
architecture behavior of converter is
signal memory : std_logic_vector( 1 to 48);
begin
process(load,clk)
begin
if (clk'event and clk = '1') then
if(load = '1') then
memory <= input & memory(1 to 32);
end if;
end if;
end process;
process(unload,clk)
begin
if (clk'event and clk = '1') then
if(unload = '1') then
output <= memory & input;
end if;
end if;
end process;
end behavior;


XIII
control.vhd

library ieee;
use ieee.std_logic_1164.all;
entity control is port
( reset : in std_logic;
clk : in std_logic;
load_new_pt : out std_logic;
output_ok : out std_logic;
load_pt : out std_logic;
unload_pt : out std_logic;
load_key : out std_logic;
unload_key : out std_logic;
shift : out std_logic_vector(1 to 3));
end control;

REG32.VHD
library ieee ;
use ieee.std_logic_1164.all;
entity reg32 is
port( a : in std_logic_vector (1 to 32);
q : out std_logic_vector (1 to 32);
reset : in std_logic;
clk : in std_logic );
end reg32;
architecture synth of reg32 is
signal memory : std_logic_vector (1 to 32) ;
begin
process(clk,reset)
begin
if(reset = '1') then
memory <= (others => '0');
else
if(clk = '1' and clk'event) then
memory <= a;
end if;
end if;
end process;
q <= memory;
end synth;



B GIO DC V O TO B quc phng
HC VIN K THUT QUN S
-----------------------------------------


Hong Vn Qun


nghin cu thit k
modul m khi dng trong x l mt
thng tin trn cng ngh fpga

Chuyn ngnh: K thut v tuyn in t v thng tin lin lc
M s: 2.02.03



LUN VN THC S K THUT

NGI HNG DN KHOA HC:
PGS.tS - xun tin


H Ni - 2005


B GIO DC V O TO B quc phng
HC VIN K THUT QUN S
--------------------------------------------

lun vn thc s k thut

Tn ti:
Nghin cu thit k modul m khi dng trong x l mt thng tin
trn cng ngh Fpga

Chuyn ngnh: K thut v tuyn in t v thng tin lin lc
M s: 2.02.03
Ngy giao ti lun vn: 21/10/2004
Ngy hon thnh lun vn: 16/05/2005

Ngi thc hin:
H v tn: Hong Vn Qun Cp bc: i u
Lp: V tuyn in t v thng tin lin lc Kha: 15
H: o to tp trung

Cn b hng dn:
H v tn: Xun Tin Cp bc: i t
Hc hm, hc v: PGS.TS n v cng tc: Khoa V tuyn in t


H ni - 2005