for pipos

module pipos (c, d,q);

input c;
input [3:0]d;
output reg[3:0]q;
always @(posedge c)
begin
q[3]<=d[3];
q[2]<=d[2];
q[1]<=d[1];
q[0]<=d[0];
end
endmodule
//testbench
module pipos_test;
reg c;
reg [3:0] d;
wire [3:0] q;
pipos uut(.clk (clk),.d (d),.q(q));
initial
begin
c = 0;
d = 0;
#100;
d=4'b 1001;

end
always #5 c=~c;
endmodule
******************************
for sipo
module sipo(c,si,so);
input c,si;
output so;
reg [3:0]q=0;
always @(posedge c)
begin
q[3]<=si;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
assign so=q[0];
endmodule
/testbench:
module sipo_test;
reg c;
reg si;
wire[3:0] q;
sipo utt(.c(c),.si(si),.q(q));
initial
begin
c=0;
si=1;
#10;
si=0;
#10;
si=0;
#10;
 si=1;
end
always #5 c=~c;
endmodule
******************************
module piso(c,d,mode,so);
input c;
input [3:0]d;
output so;
reg[3:0]q=0;
always @(posedge c)
begin
if(mode)
q<=d;
else
begin
q[3]<=1'bx;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
end
assign so=q[0];
endmodule
//testbench
module pipos_test;
reg c;
reg[3:0]d;
wire [3:0] q;
pipos uut(.c(c),.d(d),.q(q));
initial
begin
c=0;
d=0;
#100;
d=4'b=1001;
end
always #5 c=~c;
endmodule