Modeling Nanoscale MOSFETs By a Neural Network Approach

Min Fang, Jin He, Jian Zhang, Lining Zhang, Mansun Chan, and Chenyue Ma
Abstract - This paper presents modeling nanometer MOSFETs by a neural network approach. The principle of this approach is firstly introduced and its application in modeling DC and conductance characteristics of nano-MOSFET is demonstrated in details. It is shown that this approach does not need parameter extraction routine while its prediction of the transistor performance has a small relative error within 1% compared with measure data, thus its result is as accurate as that BSIM model. .

II. NEURAL NETWORK PRINCIPLE PROPAGATION ALGORITHM

AND

BACK

I. INTRODUCTION
Following the ITRS prediction, the CMOS integrated circuit will soon approach 32nm technology generation in two or three years, and the compact model for such nanoscale MOSFETs is highly required for the device optimization and circuit analysis. The traditional device models such as BSIM and PICM models use the threshold voltage method to construct the compact model framework. Such a model approach, however, is generally believed to be outdated due to the regional characteristics, too many fitting parameter which lead to complex parameter extraction routine, thus requires a paradigm shift in the core model structure. In such a background, the advanced MOSFET model approaches such as surface potential based and charge-based become popular in compact modeling community in recent several years. These new developments will replaced the threshold voltage based model for us to be sued in the nanoscale MOSFET circuit simulation and analysis. In this paper, we forsake the traditional method and develop a neural network approach to modeling nanoscale MOSFET transistor. When comparing with the measured data, the accuracy of this appraoch is satisfactory for the compact modeling application because the relative error is within 1%. The paper is divided into four sections, the section one is a simple introduction, and in section two we give a description of the neural network principle and its algorithm-back propagation algorithm. In section three, we design a neural network to model the DC and conductance performance of different size MOSFET device. In section four we show the neural network method result compared with the measurement data and BSIM model. The final is the conclusion and acknowledgement.
Min Fang Jin He and Mansun Chan are with the Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China; Jin He, Jian Zhang, Lining Zhang, and Chenyue Ma are with TSRC, Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education, EECS, Peking University, Beijing, China, E-mail: jinhe@ime.pku.edu.cn

We first describe the neural network structure to better understand what neural network is and why it has the ability to model nanoscale MOS transistor performance. We start the neural network from the external input-output-point-of-view, and also from the internal neuron information processing point-of-view. The most popularly used neural network structure is the multiplayer perception (MLP) as shown in Fig.1. A typical neural network structure has two types of basic components, namely, the processing elements and interconnections between them. The processing elements are called neuron and the connections between the neurons are known as links or synapses. Every link has a corresponding weight parameter associated wit it. Each neuron receives stimulus from other neurons connected to it, processes the information, and produced an output. Neurons that receive stimuli from outside network are called input neurons, while neurons whose outputs are used externally are called output neurons. Neurons that receive stimuli from other neurons and whose outputs are stimuli for other neurons in the network are known as hidden neurons. Different neural network framework can be constructed by using different type and amount of neurons and by connecting them differently. The type and amount determine the network scale and the connecting algorithm determines network efficiency and accuracy. In this paper, we used a so-called back propagation algorithm, which may be suitable for the nanoscale device modeling [1]. P.J.Werbos first depicted the back-propagation algorithm in his Ph.D thesis [2]. It became widely used after it was rediscovered by Rumehlhart, Hinton, Williams [3], David Parker and Yann Le Cun [4]. Some research results proven that MLP feed forward networks with arbitrary squashing functions can be approximated as a bore integrable function from one finite dimensional space to another finite dimensional space. Fig.1 is a three-layer forward neural network, there are R neuron inputs, S1, S2, and S3 neurons in the first, second and third layer, respectively. The output of one layer becomes the input to the following layer, the equation that describe this operation is as follows:

a3

f 3 ( w3 f 2 ( w2 f 1 ( w1 p b1 ) b 2 ) b3 ) (1)

wi, bi denote the weight and bias matrix of the ith layer. The work principle of the neural network shown in Fig.1 includes two different stages: training and working. In the former stage, data is sent into the input layer of the network and transmitted to the output layer. The training process needs to be repeated until the error reaching a defined value. The parameters are updated by using the

978-1-4244-2540-2/08/$25.00 2008 IEEE

steepest descent back programming algorithm [1], but some disadvantages limits its action in practice. As an improved, the Levenberg-Marquardt algorithm is a variation of Newtons method that was designed for minimizing functions that are sums of squares of other nonlinear function, this algorithm is well suited to neural network training. The Levenberg-Marquardt algorithm is written as
XK
1

TABLE Ids-Vgs TRAINING DATA measure Vds (V) Vbs (V) Vgs (V) W/L ( m) T( ) Parameters range 0.05:0.05:1.2 -1, -0.5,0,0.25 0.0:0.05:1.35 0.1/0.08, 0.24/0.08, 0.5/0.08, 0.12/0.09, 0.12/0.1,0.12/0.12,2/0.24 -55,25,125

XK

(J T ( X K )J ( X K )

I) 1JT

(2)

Where the XK is the weights or bias matrix of the Kth epoch of network, J(XK) is the Jacobian matrix that contain first derivatives of the network errors with respect to the weights and biases, V(XK) is a vector of network errors. This algorithm has a very useful feature: As K increases it approaches the steepest descent algorithm with small learning rate:
XK
1

XK

1 K

J T ( X K )V ( X K )

X K (2 X K )

F ( X ) (3)

This network can model the transistor DC and AC characterization of nanoscale MOSFETs. We firstly train the network with the measure data coming from 90nm CMOS production process. The training data is show in TABLE ) and TABLE ), the training algorithm is the Levenberg-Marquardt algorithm, after epochs to 300, the output of the network compared with the measure data, has only the relative error within 1%, the corresponding result is show in Fig.2-3 and Fig.4-5.

While as K decreases to zero the algorithm becomes Gauss-Newton algorithm:

XK
1

XK

( J T ( X K ) J ( X K )) 1 J T ( X K )V ( X K )

(4)

The algorithm begins with being set to some small value. If a step does not yield a smaller value for F(X), multiplied by some then the step is repeated with factor >1, eventually F(X) should descent; otherwise K is divided by for the next step, so that the algorithm will approach Gauss-Newton which should provide faster convergence. The algorithm provides a good compromise between the speed of Newtons method and the guaranteed convergence of steepest descent [1].

Fig. 1. Three layer forward network diagram.

9.0x10
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Trained W /L/T=2.0/0.24/125 Vbs=-0.5V

III. NEURAL NETWORK APPROACH TO MODELING NANOSCALE TRANSISTOR

Here, we select a three-layer forward network, the network has 6 inputs parameters: drain-source voltage (Vds), gate-source voltage (Vgs), bulk-source voltage (Vbs ), length (L), width (W), and temperature (T). The network has 16,8,1 neurons in the first, second and third layer and the corresponding transfer function f1, f2, and f3 is hyperbolic tangent sigmoid, log-sigmoid and linear function, the output is the drain-source current. TABLE Ids-Vds TRAINING DATA measure Vds (V) Vbs (V) Vgs (V) W/L( m) T( ) Parameters range 0.05:0.05:1.3 -0.75, -0.5, 0 0.2:0.2:1.2 0.1/0.08,0.24/0.08,0.5/0.08,1/0.08, 0.12/0.09,0.12/0.1, 0.12/0.12, 2/0.24 -55,25,125

Ids(A)

measure neural vgs=0.2 vgs=0.4 vgs=0.6 vgs=0.8 -4 vgs=1.0 6.0x10 vgs=1.2

3.0x10

-4

0.0 0.0

0.4

V ds (V)

0.8

1.2

Fig. 2. Comparison of the trained MOSFET output performance with the measured data for the transistor with W/L/T=2/0.24/125 and Vbs=-0.5V. The dot is the measure data and the line is the neural network output.
Trained W/L/T=2.0/0.24/125 Vbs=-0.5V 10
-3

log gds (A/V)

10 10 10

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measu neur Vgs=0.2 Vgs=0.4 Vgs=0.6 Vgs=0.8 Vgs=1.0 Vgs=1.2

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Vds(V)

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Fig. 3. Trans-conductance (gm) comparison obtained from above Fig.2.

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Trained W/L/T=0.12/0.12/-55 Vds=1.2V

neur measu Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

Trained W/L/T=0.12/0.12/-55 Vds=1.2V 1.5x10

-4

Ids(A)

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gm(A/V)

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shown in Fig.6-7 and Fig.8-9. It is found from these figures that the relative error between the neural network prediction and measured data is about 1%.

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measu neur Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

IV. RESULT CMPARISON BETWEEN THE NEURAL NETWORK METHOD AND BSIM MODEL
1.2

0.0

0.0

0.4

Vgs(V)

0.8

1.2

0.0

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Vgs(V)

0.8

Fig. 4

Fig. 5

Fig. 4. Comparison of the trained MOSFET transfer performance with the measured data for the transistor with W/L/T=0.12/0.12/-55 and Vds=1.2V. Fig. 5. Comparison of gm obtained from Fig. 4.
Working for W/L/T=0.5/0.08/25 Vbs=-0.75V 4.0x10 Ids(A)
-4

meas neur vgs=0.2 vgs=0.4 vgs=0.6 vgs=0.8 vgs=1.0 vgs=1.2

In order to validate the neural network method, we use the neural network method and BSIM model to fit the same measured data of the same nanosale transistor. The results and the relative errors are shown in from Fig.10 to Fig.17. It is found that the relative error between the neural network method and the measured date is about 1% while the relative error between the BSIM model and the measured data is larger than 1% in most cases. So we can conclude that the neural network method is at least as accurate as BSIM model, and can be used to model nanoscale MOSFET transistor.
5.0x10
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W/L/T=0.5/0.08/25 Vbs=-0.75V
measure neural vgs=0.2 vgs=0.4 vgs=0.6 vgs=0.8 vgs=1.0 vgs=1.2 bsim

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Ids(A)

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Fig. 6. The comparison of the neural network predicted output performance with the measured data for the transistor with W/L/T=0.5/0.08/25 and Vbs=-0.75V.
working for W/L/T=0.5/0.08/25 Vbs=-0.75V 10 10 10 10
-3

0.0 0.0

0.4

Vds(V)

0.8

1.2

Fig. 10. Comparison of output characteristics from neural network method, BSIM model, and measured data.
5
W/L/T=0.5/0.08/25 Vbs=-0.75V

log(gds)(A/V)

-4

-5

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measu neur Vgs=0.2 Vgs=0.4 Vgs=0.6 Vgs=0.8 Vgs=1.0 Vgs=1.2

Relative error

4
neural

3 2 1 0.0

bsim vgs=0.2 vgs=0.4 vgs=0.6 vgs=0.8 vgs=1.0 vgs=1.2

0.0

0.4

Vds(V)

0.8

1.2

0.4

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1.2

Fig. 7. The output-conductance comparison from Fig. 6.

Working for W/L/T=0.24/0.08/-55 Vds=1.0V
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measu neur Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

Vds(V)

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Working for W/L/T=0.24/0.08/-55 Vds=1.0V

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Ids(A)

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gm(A/V)

Fig. 11. The relative error comparison of the output characteristics from the neural network method and BSIM model compared with measured data.
W/L/T=O.5/0.08/25 Vbs=-0.75V
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measu neur Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

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Fig. 8

Fig. 9

log gds (A/V)

Vgs(V)

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1.2

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measure neural Vgs=0.2 Vgs=0.4 Vgs=0.6 Vgs=0.8 Vgs=1.0 Vgs=1.2 bsim

Fig. 8. Comparison of the neural network predicted transfer performance of the MOSFET with W/L/T=0.24/0.08/-55V and Vds=1.0V. Fig. 9. Comparison of gm from Fig.8. Based on the training results, the trained network can work now. Measured data with W/L/T=0.5/0.08/25 compared with the neural network worked results, as

10

-6

10

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0.0

0.4

0.8

1.2

Vds(V)

Fig. 12. Comparison of output-conductance from neural network method, BSIM model, and measured data.

W/L/T=0.5/0.08/25 Vbs=-0.75V
neural bsim vgs=0.2 vgs=0.4 vgs=0.6 vgs=0.8 vgs=1.0 vgs=1.2

0.3

W /L/T=0.24/0.08/-55 V ds =1.0V

Relative error

4 3 2 1 0.0 0.4 0.8

relative error

0.2

neural

0.1

bsim Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

Vds(V)

1.2

0.0

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V gs (V)

Fig. 13. The relative error comparison of outputconductance from neural network method and BSIM model compared with measured data.
W/L/T=0.24/0.08/-55 Vds=1.0V
3.0x10
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Fig. 17. The relative error comparison of gm from the Neural network method and BSIM model compared with the Measure data.

measure

neural Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

bsim

V. CONCLUSIONS
In this paper we present a neural network approach to modeling nanoscale MOSFET transistor performance. The MLP neural network application in modeling nanoscale MOSFETs is demonstrated in details via the training and working processing. It is shown that the neural network approach does not need extraction parameters while also having some other advantages: the characteristic curve can be differentiable from first order to infinite order in all transistor operation regions. Moreover, The used neural network methods accuracy is tested and is further validated by compared with BSIM model.

ids(A)

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0.0 0.0

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Vgs(V)

0.8

1.2

Fig. 14. The comparison of Ids-Vgs from the neural network method, BSIM model, and measured data.
0.15

W/L/T=0.24/0.08/-55 Vds=1.0V

relative error

0.12 0.09 0.06 0.03 0.00 0.4 0.8 1.2

neural bsim Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

ACKNOWLEDGMENT
This work is subsidized by the National natural Science Funds of China (90607017). This work is also partially supported by a NEDO grant from Japan.

REFERENCES
Vgs(V)

Fig. 15. The relative error comparison of Ids-Vgs from the neural network method and BSIM model compared with measured data.
W /L/T=0.24/0.08/-55 V ds =1.0V
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gm (A/V)

2.0x10

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m easure

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neural Vbs=-1.0 Vbs=-0.5 Vbs=-0.0 Vbs=0.25

bsim

[1] Martin.Hagan, Howard B.Demuth, Mark H.Beale, Neural network design, PWS, 1996. [2] P.J.Werbos, beyond regression: new tools for prediction and analysis in the behavioral sciences, Ph.D.Thesis, tionHarvard University, Cambridge, MA, 1974. [3] D.E.Rumelhart, G.E.Hinton and R.J.Williams, learning representations by back propagating errors, Nature, vol.323, pp.533- 536, 1986. [4] D.B.Parker, learning-logic: casting the cortex of the human brain in silicon, Technique Report TR-47, Center for computational research in economics and management science, MIT, Cambridge, MA, 1985.

0.0 0.0

0.4

V gs (V)

0.8

1.2

Fig. 16. Comparison of gm from neural network method, BSIM model, and measured data.