Introduction to VLSI Design

Typical Design Flow High Level Design g Low Level Design

S. Choomchuay, Ph.D. y,
Intro. to VLSI Design
S. Choomchuay //KMITL

Role f Chips R l of Chi

Idea Id
Applications Circuit Design g

Fabrication
Intro. to VLSI Design
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VLSI Design Challenge

productivity yield l Shorter design cycle with more product feature Reduce NRE (Non Recursive Engineering Cost) (Non-Recursive Design reuse enable Increase flexibility to design changes y g g Faster exploitation of alternative architecture Faster exploitation of alternative libraries B Better & Easier d i auditing & verification E i design di i ifi i
I Increasing

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Development History
Vacuum tube Semiconductor
Germanium Discrete Small IC Metal Base PCB
10-50 / 6"x9"

Silicon LSI VLSI

Chip
10-50 /2x2 mm 10000-100000/1x1 cm

1906

1930

1951

1961

1969

1975

Year Y
4

Intro. to VLSI Design

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IC Design & Fabrication

circuit design & simulation Layout (pattern) Design & synthesis Design Tools Sim. Sim Tools

Design Tools Sim. Tools

Mask Set

Fabrication Process
Material & Equipments Assembly & Packaging

IC Chips p

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Digital Circuit Concept

Supply Voltage S l V lt
Switch 1 Switch 2 Control Current
6

Result
Switch 3 Switch 4

Switch

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Switch & Technology

Bipolar

Speed = ? Dissipation = ?

MOS
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Mixed Mi d (BiCMOS)
7

IC Process
Wafers

Mask Set

Protective cover

Selective Patterning STEPS ?

Implant Dope

Front End

Dicing Di i

Bonding B di

Molding M ldi
Back End B kE d

Intro. to VLSI Design

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IC Fabrication
3"- 8" Silicon

Wafer
Clean Room IC PROCESS

Water Air Environment E i

Treatment T t t Machines & Tools

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CVD Implanter Stepper E-Beam Furnace

Intro. to VLSI Design

Process Keyword ( ) y (1)

Oxidation O id ti
Si Si Si

sio2 - Thermal -CVD

Implantation

Annealing A li
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Process Keyword ( ) y (2)

Photolithography Ph t lith h
UV light, Electron Beam Photoresis SiO2 Si Patterning Developed MASK

Etching & Strip off p

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Behavioural Level of Abstraction

System Concept Algorithm Architecture RTL Gate Transistor

RTL = Register Transfer Level
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VLSI Design D i D i Domain

Level of Abstraction System Design Domain Abstract Structure Physical

Structural Architecture Synthesis Design RTL Level Algorithm g Synthesis Structural Logic Level RTL Design Synthesis Verification Logic g Logic Design Verification Layout Design (Syn) g Gate Verification V ifi ti

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VLSI Low Level Design

Spec p
Design

Typical Design Flow

High Level Model

Simulation
Logic Level i l Model

Mask Sets

Logic Synthesis PLD,FPGA

Intro. to VLSI Design

Simulation

Place & Route

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Cell Library

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VLSI Low Level Design

Logic Design

Cell Library Design

DRC

Simulation
Logic Level Model

Layout Design

Extraction

Simulation Circuit Design Simulation

Device Level Device Model

Masks
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Intro. to VLSI Design

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Top Down Design

System Level

Board Level

C p eve Chip Level

RTL Synthesis S th i Layout Synthesis

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HDL Synthesis Tools

VHDL
1980 VSHIC DoD Project VSHIC, D D P j 1983 IBM and TI joint project 1987 DoD and IEEE1076 Standards 1993 Revise of IEEE1076 1996 Extend to 1076.3 and 1076.4

Verilog
1981 CAE software launched by Dateway Design Auto. (founded by Phil Mooreby) 1983 Release of Verilog HDL 1987 Extended to Verilog XL g 1989 Verylog XL is widely used 1990 Cadence bought Gateway 1995 Verilog --> IEEE1364
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Synthesis Optimisation
VHDL/Verilog

Criteria
Synthesis (Translation)
Optimisation module

Constraints

Area & Timing Analysis

Netlist
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Synthesis Constrains
Global
Library process factor Operating voltage Operating temperature

Circuit Specification
Area - max area Timing - fan-in, fan-out - I/p & o/p loading cap. p p g p - Max.clock frequency Power - max power max. Testability - Full or partial scan - Boundary scan

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Layout Design

Circuit Level Design

Static Complement MOS - Conventional Circuit Dynamic Logic - Clock CMOS - Domino Logic

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Layout Design
Conventional static gate (Complementary)
C A Y A C B B

NMOS chain implements the function PMOS chain is a complementary arrangement of N-Chain g Output is taken at the center

Y = ( A B) + C
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Layout Design

Actual MOS Devices

Gate (Control)

(N)

(N) Silicon(P)

Gate

= ? micron
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Intro. to VLSI Design

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Layout Design

MOS Parameters
W

Tox
(N) Silicon(P) L (N)

W/L defines MOS current K = Process Transconductance

Intro. to VLSI Design

I D = K (VGS VT ) 2
1 K = 2 [C OX ( W )] L

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Layout Design
S

MOS Device Model G D

W Channel Width L Channel Length AD, AS Drain,Source Area PD,PS Drain,Source Periphery

W
( ) (N) ( ) (N)

Substrate (P)

vG Cgs Cgsub iD

AS

AD

L
Cgd g vD

SubvS
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vSub

Actual MOS Device

Inverter, X-section
I/P GND O/P Vdd

n P Well

N-Type Substrate
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Actual MOS Device

Inverter, X-section
p n

Vdd

I/P

O/P

GND

Inverter Circuit
Intro. to VLSI Design

Actual X-Section
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P Well

N-Type Substrate S

Layout Design
26

L-Edit, Tricky bits

NOR 2-input (N well)

Only one active, We have to say N-active or P-active Poly Contact or Active Contact (both to metal) Substrate ties Port names need for extraction (simulation) ( ) DRC needs
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Low Level Design, DRC

What does it say?

2x2

Minimum features size (Layers & wire) Minimum spacing between 2 objects Define in base & micron base

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Low Level Design

Stick Diagram

Color stick objects represent layer and routing

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Low Level Design

Layer
Metal

Layer design guide

C
Low

R
Low

Comments
Power distribution Global Signal Long wiring g g High IR drop Moderate RC product High Capacitance Moderate IR drop

Polysilicon Diffusion

Low Moderate

Moderate High

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Low Level Design

MOS as RC

W B L
0 r ( WL ) t ( WL ) Cg = TOX C G Sub =

L L L = = s ( ) A Wt W 1 1 n = ; p = q n n q p p R AB = 1 R AB = q n n( W ) NMOS L
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Intro. to VLSI Design

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Low Level Design

Complement Logic Switch

PMOS chain NMOS chain

RP

Rn

nCg

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Low Level Design

STD Cell Style

All Cells are same height Width can be varied Power rails (left-right) Signals (top, bottom) (top Routing channels outside

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