A 77 GHz Controllable Gain Low Noise Amplifier

M. Fahimnia*, M. Mohammad-Taheri**, Y. Wang*** and S., Safavi-Naeini**** *ECE department, University of Waterloo, Waterloo, Ontario, Canada, mfahimni@uwaterloo.ca **ECE department, University of Tehran, Tehran, Iran, mtaheri@ut.ac.ir ***EE department, University of Ontario Institute of Technology, Ontario, Canada, ying.wang@uoit.ca **** ECE department, University of Waterloo, Waterloo, Ontario, Canada, safavi@maxwell.uwaterloo.ca

Abstract: A 77GHz low noise amplifier has been designed using common source topology implemented in low cost CMOS technology for various applications. A new method has been proposed for the design of the amplifier. In this method, input/output matching networks and transistor gate widths have been optimized for maximum gain and minimum noise figure. The design is flexible such that the LNA can operate in both high gain/high power and low gain/low power modes with low noise figure of less than 7dB at 77GHz. Amplifier gain is better than 18dB consuming 60mW of dc power and it is better than 14.5dB consuming 30mW of dc power. The input and output return losses are better than 10 dB in the frequency range of 72 to 82 GHz.

Keywords: CMOS; Microstrip Line (MSL); Low Noise amplifier (LNA); Millimeter-Wave (MMW); Common Source (CS). 1. Introduction Use of CMOS technology in millimeter wave communication systems is expanding due to its increasing cut off frequency and its low cost technology. It also benefits from the ability to integrate with the digital part of the system, efficient manufacturing process and reliable design and performance [1-5]. The above advantages have made CMOS as a suitable choice in various applications such as broadband communication, radiometry, radio astronomy, remote sensing and high resolution imaging. These applications which have been traditionally dominated by expensive, high performance III-V technologies now are open to CMOS designers [69]. However to successfully design a CMOS circuit in mmW, designers face many challenges such as low resistivity substrate, high sheet resistivity of poly-silicon gate and significant parasitic of CMOS circuit elements. To alleviate these disadvantages, the careful modelling of CMOS is a crucial task. Taking into account the above facts, the optimization of a CMOS amplifier is a timeconsuming process. In this paper, using the accurate models for transistor and transmission line implemented

in input/output matching circuit a low noise amplifier has been designed using 4 stage cascaded common source topology. In section II, the CMOS technology and its transistor small signal and transmission line models are presented. Section III, describes the circuit design method and optimization process. In section IV, the simulation results have been presented. The designed amplifier attains 18dB gain, noise figure better than 7dB and consumes 60mW in high power mode. It can also operate in low power mode with 14.5dB gain and same noise figure as obtained in high power mode while consumes less than 30mW. It is shown that using proposed method a common source amplifier can be designed with superior performances compared with those have been already designed using CMOS technology in the literature. 2. CMOS Technology

A 130nm RF-CMOS technology has been used for LNA design. In this technology, 8 metal layers are available in core back stack. 3 thin metal layer made of Copper are used for digital purpose. They are also very suitable for shielding the millimetre wave signal from lossy substrate. 3 thick Copper metal layers provide low resistive path for circuit biasing. 2 RF Aluminium and Copper metal layers are implemented for high performance passive elements. Relatively high Q transmission lines can be realized using these two RF metal layers. This technology provides metal-insulatormetal (MIM) capacitor using oxide inter-metal dielectric. Transmission line and transistor models at millimetre wave range of frequency are investigated. 2.1 Transmission line model Top metal layer has been used for signal and lower metal level for the ground path. This arrangement isolates the millimeter-wave signal from the lossy substrate. Due to its low loss and low dispersion characteristics, microstrip transmission line (MLS) has been implemented in this

paper to realize inductor. The simulations results for MLS predict an insertion loss of 4dB per mm and an input return loss of better than 10dB at 77GHz. The transmission line is first modeled with circuit consisting of series combination of inductor and resistor with two shunt capacitors as shown in Fig. 1 [10]. To calculate the inductor, capacitor and resistor of the transmission line model, the difference between measured S-parameter of a microstrip line and model shown in Fig. 1 was minimized. Based on this minimization, the values of the model elements are obtained as: L = 0.67 pH / m (1) C = 0.02 fF / m

formula, one can calculate the element values of the intrinsic and extrinsic parameters [11-12]. However in this paper we also obtained the element values versus transistor gate width equations and used them in our optimization algorithm to find optimum gate width and input/output matching elements.

R = 0.013 / m In this paper we ignored the capacitors of transmission line as they are small compared to the intrinsic capacitance of the transistor. Fig. 2 depicts the Sparameters of the microstrip transmission line implemented in the design of low noise amplifier.

Fig. 3: Small Signal Equivalent Circuit of a MOSFET.

3.

Low noise amplifier design

Fig. 4 shows one stage of common source topology used in this paper. The input/output matching elements and transistor gate width are obtained based on simultaneous power and noise match conditions. For these conditions to be satisfied we should have the following equations:
Re[ Z in ] = 50 Im[Z in ] = 0 Re[ Z s ] = Ropt Im[Z s ] = X opt

Fig.1:Microstrip transmission line model.

(2)

-10 -11

dB(S(1,1))

-12 -13 -14 -15 60 65 70 75 80 85 90

Where Zs is source impedance (see Fig. 5) and Zopt=Ropt+jXopt is optimized noise impedance of the transistor.

freq, GHz
-0.25

Fig. 4 One stage amplifier with input/output matching circuits.

dB(S(2,1))

-0.35

-0.45

In Fig. 5, the whole circuit is optimized at once. This ensures the output matching of each stage is implemented for the input matching of the next stage. For example, L1 and L2 are used for input matching; L4, L5 and L6 are used for output matching of the first stage and input matching of the second stage.
60 65 70 75 80 85 90

-0.55

freq, GHz

Fig. 2: S-parameters of a 100m microstrip.

2.2 Transistor model Fig. 3 shows the widely used small signal model of a MOSFET. The intrinsic elements of the model can be easily found using Y-parameters of the transistor. The measured S-parameters of the active device is first converted to the Y-parameters and using well-known

Fig. 5: Designed 4 stages cascaded amplifier.

In addition, L3 provides simultaneous power and noise match based on equation (2) and also improves the stability of the first stage. Table I shows the optimized values for the designed amplifier.
TABLE I: Optimized designed values for the amplifier.
Stage 1 Stage 2 Stage 3 Stage 4

From this figure, gain is better than 14dB in the frequency range of 74GHz to 80GHz. Input and output return losses are better than 13dB in this frequency range. The amplifier consumes 30mW of dc power. Fig. 8 depicts the noise figure and NFmin for high gain mode.

W = 65m L1 = 33 pH L2 = 40 pH L3 = 10 pH L4 = 40 pH

W=67.5 m L5 = 35 pH L6 = 29 pH L7 = 40 pH

W=67.5 m L8 = 30 pH L9 = 20 pH L10 = 40 pH

W=65 m L11 = 16 pH L12 = 30 pH L13 = 17 pH L14 = 42 pH

All inductors have been replaced by microstrip transmission lines whose lengths were calculated using (1). For example the inductor L14 was realized with a 63m microstrip line which is the longest required line. As can be seen from table 1, all inductors can be realized using short lines which is an advantage for the design amplifier. This decrease the losses and parasitic of the lines and also miniaturizes the layout of the circuit which are of great important for MMIC design. 4. Simulation results Standard Vd=1.2V supply is used to bias the amplifier. Fig. 6 shows the S-parameters of the designed amplifier for Vg=0.75 V (High gain mode). As can be seen from Fig. 6, gain is better than 18dB in the frequency range of 73GHz to 78GHz. Input and output return losses are better than 12dB in this frequency range while consumes 60mW.

Fig. 8: Noise figure and NFmin for high gain mode.

As can been seen the noise figure is quite close to NFmin which shows a very good noise match for the designed amplifier. Noise figure is 6.7dB at 78GHz in high gain mode. It should be noted that noise figure is 6.9dB at 78GHz in low power mode. Fig. 9 shows the stability factor of the designed amplifier. From this figure it is clear that the amplifier is highly stable in both modes.

Fig. 9: Stability factor of the designed amplifier. Fig. 6: S-parameters for high gain mode.

Fig. 7 also shows the S-parameters for Vg=0.6 V (Low power mode).

Table II compare the performance of the designed amplifier with those have been already reported in the literature using CMOS technology. From this table it can be seen that the designed amplifier in the low power mode has better noise figure and lower power consumption with same gain as cascode amplifier presented in [10]. It also has an acceptable gain and noise figure compared with similar amplifier designed in the millimeter-wave range of frequency. 5. Conclusion A 77 GHz controllable gain amplifier using 0.13-m CMOS technology has been analyzed and designed using 4 stages cascaded common source topology. In order to maximize gain and minimize noise figure of the LNA,

Fig 7 S-parameters for low power mode.

TABLE II: Comparison with reported performance of amplifiers in millimeter-wave frequencies.

Band width (GHz) Power Consumption (mW)

Technology

Topology

Gain (dB)

Noise figure (dB)

Reference

CMOS 90nm CMOS 90nm CMOS 0.13-m CMOS 0.13-m CMOS 0.13-m CMOS 0.13-m CMOS 0.13-m

3 stage cascode 3 stage CS 3 stage cascode 3 stage cascode 4 stage cascode 2 stage asymmetric cascode 4 stage CS

103-105 86-108 51-65 50-58 42-63 72-80 73-78 74-80

Peak 9.34 @ 103.8 GHz Peak 17.4 @ 91 GHz Peak 12 @ 60 GHz Peak 24.7 @ 56 GHz Peak 18.1 @ 45 GHz Flat 15 @ 72-80GHz Peak 18.5 @ 75GHz Peak 15 @ 78GHz

NA NA 8.8 @ 60GHz 7.1 @ 56.8GHz 8.2 @ 60GHz 7.3 @ 78GHz 6.7 @ 78GHZ 6.9 @ 78GHz

22 54 48 72 91.2 36 60 30

[1] [2] [3] [4] [5] [13] This Work

input/output matching circuit and transistor widths for each stage are optimized based on simultaneous power and noise match conditions. All inductors are realized by microstrip transmission line in order to reduce the circuit size and enhance the performance of the designed amplifier. The simulation results show a gain of better than 18dB and 14dB in high gain and low power modes respectively. Input/output return losses are better than 12dB and noise figure is better than 6.9dB in both cases. The amplifier is highly stable for the frequency range of 73GHz to 80GHz. Acknowledgement This work was supported by NSERC (Natural Science and Engineering Council) of Canada and Research in Motion (RIM). References
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