ERS 220 DIGITAL SYSTEMS

HDL/VHDL

HDL

What is HDL?
Hardware Description Languages
3o years ago the primary tools of a digital designer included a logic-drawing template, a ruler and a pencil, all for drawing block diagrams and schematics. In the 1980s, schematics were still the primary means of describing digital circuits and systems. However schematic creation and maintenance had been simplified by the introduction of schematic editor tools. That decade also saw the limited uses of HDLs, mainly to describe logic equations to be realised in Programmable Logic Devices (PLD)s. The use of HDLs together with very-large-scale ASIC technology in the 1990s resulted in radical changes to typical digital design.

What is HDL?
Why HDLs? HDLs?
In traditional software design, high-level programming languages like C, C++ and Java have raised the level and complexity of designing systems over traditional hand-tuned assembly-language programs. Similarly, more complex digital systems design, for FPGA and ASIC technologies, can be aided by using synthesis tools like VHDL, ABEL or Verilog, hence taking advantage of the millions of gates on offer.

What is HDL?
HDL Tool Suites
There are several HDL Tool Suites, or EDA (Electronic Design Automation) Tools, available for circuit synthesis, implementation, and simulation using VHDL. A typical EDA Tool, like Alteras Quartus II Software, is made up of several different components:
Text Editor
Allows you to write, edit and save an HDL program.

Compiler
Responsible for parsing the HDL program, finding syntax errors, and figures out what the program really says.

Synthesiser
Targets the design to a specific hardware technology, such as a PLD, FPGA or ASIC.

Simulator
Timed sequence of inputs for the hardware that describes it. The input sequence can be in the form another HDL program, called a Test Bench, Editor. Bench or can be described graphically, via a Waveform Editor

VHDL

What is VHDL?
Introduction
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. Circuit It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

A Brief History of VHDL

The Requirement
The development of VHDL was initiated in 1981 by the United States Department of Defence (DoD) to address the hardware life cycle crisis. The cost of re-procuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology.

A Brief History of VHDL

Standardization
The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version 7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the DoD to the IEEE in order to encourage industry acceptance and investment.

A Brief History of VHDL

life1981 - Initiated by US DoD to address hardware life-cycle crisis 1983Intermetrics, 1983-85 - Development of baseline language by Intermetrics, IBM and TI 1986 - All rights transferred to IEEE 1987 - Publication of IEEE Standard 1987 - Mil Std 454 requires comprehensive VHDL descriptions to be delivered with ASICs 10761994 - Revised standard (named VHDL 1076-1993) 2000 - Revised standard (named VHDL 1076 2000, Edition) 10762002 - Revised standard (named VHDL 1076-2002) 2007 - VHDL Procedural Language Application Interface standard 1076c(VHDL 1076c-2007) 10762009 - Revised Standard (named VHDL 1076-2008)

Summary
VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary. VHDL is intended for circuit synthesis as well as simulation. However, though VHDL is fully simulatable, not all constructs are synthesisable. Simulation and synthesis are the two main kinds of tools which operate on the VHDL language.

Summary
VHDL does not constrain the user to one style of description, and allows designs to be described using any methodology - top down, bottom up or middle out! VHDL can be used to describe hardware at the gate level or in a more abstract way. Successful high level design requires a language, a tool set and a suitable methodology. VHDL is the language, you choose the tools, and the methodology. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

Summary
Contrary to regular computer programs which are sequential, VHDL statements are inherently concurrent (parallel). For that reason, VHDL is usually referred to as a code rather than a program. In VHDL, only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.

Levels of Abstraction
VHDL can be used to describe electronic hardware at many different levels of abstraction. When considering the application of VHDL to FPGA design, it is helpful to identify and understand the 3 levels of abstraction:
Algorithm, Register Transfer Level (RTL), and Gate Level.

Algorithms are unsynthesisable, RTL is the input to synthesis, Gate Level is the output from synthesis.

Levels of Abstraction
Register Level Transfer (RTL)
RTL is a level of abstraction used in describing the operation of a synchronous digital circuit. In RTL design, a circuit's behaviour is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals. This is the ideal level of abstraction at which to design hardware given the state of the art of today's synthesis tools. The Gate level is too low a level for describing hardware - remember we're trying to move away from the implementation concerns of hardware design, we want to abstract to the specification level - what the hardware does, not how it does it. Conversely, the Algorithmic level is too high a level, most commercially available synthesis tools cannot produce hardware from a description at this level.

Design Flow
We start the design by writing the VHDL code, which is saved in a file with the extension .vhd and the same name as its ENTITYs name. The first step in the synthesis process is compilation. Compilation is the conversion of the high-level VHDL language, which describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level. The second step is optimization, which is performed on the gate-level netlist for speed or for area. At this stage, the design can be simulated. Finally, a place-and-route (fitter) software will generate the physical layout for a FPGA. "netlist" describes the connectivity of an electronic design and either netlist" contain or refer to descriptions of the parts or devices used.

Circuit Translation
Translation of VHDL Code into a Circuit
A full-adder unit is depicted in the figure. In it, a and b represent the input bits to be added, cin is the carry-in bit, s is the sum bit, and cout the carry-out bit. As can be seen from the truth table, s must be high whenever the number of inputs that are high is odd, while cout must be high when two or more inputs are high. From this the outputs can be computed:

Circuit Translation
Translation of VHDL Code into a Circuit Using these computations, and , we create a VHDL code.

From the VHDL code shown on the left-hand side, a physical circuit is inferred, as indicated on the right-hand side.

Circuit Translation
Translation of VHDL Code into a Circuit

There are several ways of implementing the equations described in the ARCHITECTURE so ARCHITECTURE, the actual circuit will depend on the compiler/optimizer being used and, more importantly, on the target technology.

Circuit Translation
Translation of VHDL Code into a Circuit

Whatever the final circuit inferred from the code is, its operation should always be verified still at the design level (after synthesis). Of course, it must also be tested at the physical level, but then changes in the design might be too costly.

Circuit Translation
Translation of VHDL Code into a Circuit
When testing, waveforms similar to those depicted below will be displayed by the simulator

As can be seen, the input pins (characterized by an inward arrow with an I marked inside) and the output pins (characterized by an outward arrow with an O marked inside) are those listed in the ENTITY of the VHDL code. We can freely establish the values of the input signals (a, b, and cin in this case), and the simulator will compute and plot the output signals (s and cout). As can be observed, the outputs do behave as expected.

Code Structure
Fundamental VHDL Units
As depicted in the following figure, a standalone piece of VHDL code is composed of at least 3 fundamental sections:

declarations: LIBRARY declarations Contains a list of all libraries to be used in the design. For example: ieee, std, work, etc. ENTITY: ENTITY Specifies the I/O pins of the circuit. ARCHITECTURE: Contains the ARCHITECTURE VHDL code proper, which describes how the circuit should behave (function).

Code Structure
Library
A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows them to be reused or shared by other designs. The code is usually written in the form of FUNCTIONS, PROCEDURES, or COMPONENTS, which are placed inside PACKAGES, and then compiled into the destination library.

Code Structure
Library Declarations
To declare a LIBRARY (that is, to make it visible to the design) two lines of code are needed:
one containing the name of the library, and the other a use clause, as shown in the syntax below.

At least three packages, from three different libraries, are usually needed in a design:
ieee.std_logic_1164 (from the ieee library), standard (from the std library), and work (work library).

Code Structure
Library Declarations Their declarations are as follows:

Code Structure
Library Declarations
The libraries std and work shown above are made visible by default, so there is no need to declare them; only the ieee library must be explicitly written. However, the latter is only necessary when the STD_LOGIC (or STD_ULOGIC) data type is employed in the design.

The purpose of the three packages/libraries mentioned above is the following:

the std_logic_1164 package of the ieee library specifies a multi-level logic system; std is a resource library (data types, text i/o, etc.) for the VHDL design environment; and the work library is where we save our design (the .vhd file, plus all files created by the compiler, simulator, etc.).

Code Structure
Library Declarations
The ieee library contains several packages, including the following:
std_logic_1164: Specifies the STD_LOGIC (8 levels) and STD_ULOGIC (9 levels) multi-valued logic systems. std_logic_arith: Specifies the SIGNED and UNSIGNED data types and related arithmetic and comparison operations. It also contains several data conversion functions, which allow one type to be converted into another: conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), conv_std_logic_vector(p, b). std_logic_signed: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED. std_logic_unsigned: Contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED.

Code Structure
Entity An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit. Its syntax is shown below:

Code Structure
Entity

The mode of the signal can be IN, OUT, INOUT, or BUFFER. IN and OUT are truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when the output signal must be used (read) internally. The type of the signal can be BIT, STD_LOGIC, INTEGER, etc. (Data types will be discussed later). Finally, the name of the entity can be basically any name, except VHDL reserved words.

Code Structure
Entity

The meaning of the ENTITY above is the following:

the circuit has three I/O pins,being two inputs (a and b, mode IN) and one output (x, mode OUT). All three signalsare of type BIT. The name chosen for the entity was nand_gate.

Code Structure
Architecture
The ARCHITECTURE is a description of how the circuit should behave (function). Its syntax is the following:

As shown above, an architecture has two parts: a declarative part (optional), where signals and constants (among others) are declared, and the code part (from BEGIN down). Like in the case of an entity, the name of an architecture can be basically any name (except VHDL reserved words), including the same name as the entitys.

Code Structure
Architecture

The meaning of the ARCHITECTURE above is the following: the circuit must perform the NAND operation between the two input signals (a, b and a, b) assign (<= the result to the output pin (x). <=) <= x The name chosen for this architecture was myarch. myarch In this example, there is no declarative part, and the code contains just a single assignment.

Data Types
Data Types
VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164 standards. More specifically, such data type definitions can be found in the following packages / libraries: std: Package standard of library std Defines BIT, BOOLEAN, INTEGER, and REAL data types. ieee: Package std_logic_1164 of library ieee Defines STD_LOGIC and STD_ULOGIC data types. ieee: Package std_logic_arith of library ieee Defines SIGNED and UNSIGNED data types, plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b). Packages std_logic_signed and std_logic_unsigned of library ieee:
Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.

Data Types
Data Types
Most pre-defined data types (specified in the packages/libraries listed above) are described below:
BIT (and BIT_VECTOR): 2-level logic (0, 1). STD_LOGIC (and STD_LOGIC_VECTOR): 8-valued logic system introduced in the IEEE 1164 standard.
X Forcing Unknown (synthesizable unknown) 0 Forcing Low (synthesizable logic 1) 1 Forcing High (synthesizable logic 0) Z High impedance (synthesizable tri-state buer) W Weak unknown L Weak low H Weak high Dont care

STD_ULOGIC (STD_ULOGIC_VECTOR): 9-level logic system introduced in the IEEE 1164 standard (U, X, 0, 1, Z, W, L, H, ). STD_LOGIC system described above is a subtype of STD_ULOGIC. The latter includes an extra logic value, U, which stands for unresolved.

Data Types
Data Types (Continued)
Most pre-defined data types (specified in the packages/libraries listed above) are described below:
BOOLEAN: True, False. INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647). NATURAL: Non-negative integers (from 0 to 2,147,483,647). REAL: Real numbers ranging from 1.0E38 to 1.0E38. Not synthesizable. Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful in simulations. Not synthesizable. Character literals: Single ASCII character or a string of such characters. Not synthesizable. SIGNED and UNSIGNED: data types defined in the std_logic_arith package of the ieee library. They have the appea rance of STD_LOGIC_VECTOR, but accept arithmetic operations, which are typical of INTEGER data type. In addition there are various TYPES, SUB TYPES and ARRAYS.

References
Digital Design Principles and Practices, 4th Edition, John F. Wakerly, 2007, Pages 237-243, 256-290 Circuit Design with VHDL, Volnei A. Pedroni, 2004, Pages 3-8, 13-17, 25-28. http://www.doulos.com/knowhow/vhdl_designers_guide/