Pa3 DS

Revision 9
ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support Features and Benefits
High Capacity
15 k to 1 M System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os
Reprogrammable Flash Technology

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security

Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC3 devices) via JTAG (IEEE 1532compliant) FlashLock to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V Bank-Selectable I/O Voltagesup to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os Programmable Output Slew Rate and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the ProASIC3 Family Six CCC Blocks, One with an Integrated PLL Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback Wide Input Frequency Range (1.5 MHz to 350 MHz) 1 kbit of FlashROM User Nonvolatile Memory SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (1, 2, 4, 9, and 18 organizations) True Dual-Port SRAM (except 18)
Low Power
Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash Switches
Embedded Memory
High-Performance Routing Hierarchy

Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in ProASIC3 FPGAs
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
M1 ProASIC3 DevicesARMCortex-M1 Soft Processor Available with or without Debug
Table 1 ProASIC3 Product Family

ProASIC3 Devices Cortex-M1 Devices 1 System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) RAM Kbits (1,024 bits) 4,608-Bit Blocks FlashROM Kbits Secure (AES) ISP 2 Integrated PLL in CCCs VersaNet Globals 3 I/O Banks Maximum User I/Os Package Pins QFN CS VQFP TQFP PQFP FBGA A3P015 15,000 128 384 1 6 2 49 QN68 A3P030 30,000 256 768 1 6 2 81 QN48, QN68, QN132 VQ100 A3P060 60,000 512 1,536 18 4 1 Yes 1 18 2 96 QN132 CS121 VQ100 TQ144 FG144 A3P125 125,000 1,024 3,072 36 8 1 Yes 1 18 2 133 QN132 VQ100 TQ144 PQ208 FG144 A3P250 M1A3P250 250,000 2,048 6,144 36 8 1 Yes 1 18 4 157 QN132 5 VQ100 PQ208 PQ208 FG144/256 5 FG144/256/ 484 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 A3P400 M1A3P400 400,000 9,216 54 12 1 Yes 1 18 4 194 A3P600 M1A3P600 600,000 13,824 108 24 1 Yes 1 18 4 235 A3P1000 M1A3P1000 1,000,000 24,576 144 32 1 Yes 1 18 4 300
Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for Cortex-M1 ProASIC3 devices. 3. Six chip (main) and three quadrant global networks are available for A3P060 and above. 4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. 5. The M1A3P250 device does not support this package.
A3P015 and A3P030 devices do not support this feature.
October 2009 2010 Actel Corporation
Supported only by A3P015 and A3P030 devices.

I
I/Os Per Package 1

ProASIC3 Devices Cortex-M1 Devices A3P015 A3P030 A3P060 A3P125 A3P250 3 M1A3P250 3,6 I/O Type Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs 35 25 44 74 FG484 23 23 529 1.0 2.23 Single-Ended I/O2 Single-Ended I/O2 Single-Ended I/O2 Single-Ended I/O2 154 97 177 300 289 1.0 1.60 Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O A3P400 3 M1A3P400 3 A3P600 M1A3P600 A3P1000 M1A3P1000
Package QN48 QN68 QN132 CS121 VQ100 TQ144 PQ208 FG144 FG256 FG484
49
49 81 77
80 96 71 91 96
84 71 100 133 97
87 68 151 97 157
19 13 34 24 38 151 97 178 194
34 25 38 38
154 97 177 235
35 25 43 60
Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric Users Guide to ensure complying with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 FPGA Fabric Users Guide for position assignments of the 15 LVPECL pairs. 4. FG256 and FG484 are footprint-compatible packages. 5. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 Ordering Information" on page III for the location of the "G" in the part number. 6. The M1A3P250 device does not support FG256 or QN132 packages. Table 2 ProASIC3 FPGAs Package Sizes Dimensions Package Length Width (mm\mm) Nominal Area (mm2) Pitch (mm) Height (mm) QN48 66 36 0.4 0.90 CS121 66 36 0.5 0.99 QN68 88 64 0.4 0.90 QN132 88 64 0.5 0.75 VQ100 14 14 196 0.5 1.00 TQ144 20 20 400 0.5 1.40 PQ208 28 28 784 0.5 3.40 FG144 13 13 169 1.0 1.45 FG256 17 17
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ProASIC3 Ordering Information

.
A3P1000 _ 1 FG G 144 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging (some packages also halogen-free) Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) CS = Chip Scale Package (0.5 mm pitch) Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard
Part Number ProASIC3 Devices A3P015 = A3P030 = A3P060 = A3P125 = A3P250 = A3P400 = A3P600 = A3P1000 =
15,000 System Gates 30,000 System Gates 60,000 System Gates 125,000 System Gates 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates
ProASIC3 Devices with Cortex-M1 M1A3P250 = M1A3P400 = M1A3P600 = M1A3P1000 = 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates
ProASIC3 Device Status

ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Status Production Production Production Production Production Production Production Production M1A3P250 M1A3P400 M1A3P600 M1A3P1000 Production Production Production Production Cortex-M1 Devices Status
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III
Temperature Grade Offerings

Package Cortex-M1 Devices QN48 QN68 QN132 CS121 VQ100 TQ144 PQ208 FG144 FG256 FG484 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I A3P015 A3P030 A3P060 A3P125 A3P250 M1A3P250 C, I C, I C, I C, I C, I A3P400 M1A3P400 C, I C, I C, I C, I A3P600 M1A3P600 C, I C, I C, I C, I A3P1000 M1A3P1000 C, I C, I C, I C, I
Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature 2. I = Industrial temperature range: 40C to 85C ambient temperature
Speed Grade and Temperature Grade Matrix

Temperature Grade C
1
Std.
I2
Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature 2. I = Industrial temperature range: 40C to 85C ambient temperature References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.
A3P015 and A3P030

The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
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Table of Contents
ProASIC3 Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112
Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 121-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Revision 9
1 ProASIC3 Device Family Overview

General Description
ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Actel ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3 devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 device cannot be read back, although secure design verification is possible. ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
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ProASIC3 Device Family Overview and secure, making remote ISP possible. A ProASIC3 device provides the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability.
Live at Power-Up
The Actel flash-based ProASIC3 devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings.
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Advanced Flash Technology

The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and Figure 1-2 on page 1-4): FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory Extensive CCCs and PLLs Advanced I/O structure
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*
Bank 1
Bank 0
I/Os
VersaTile
Bank 1 Bank 0
ISP AES Decryption*
User Nonvolatile FlashROM Bank 1
Charge Pumps
* Not supported by A3P015 and A3P030 devices Figure 1-1 ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125)
The A3P015 and A3P030 do not support PLL or SRAM.
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ProASIC3 Device Family Overview
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 3
Bank 1
I/Os
VersaTile
Bank 3 Bank 1
ISP AES Decryption
User Nonvolatile FlashROM Bank 2
Charge Pumps
RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000)
Figure 1-2
ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3 devices via an IEEE 1532 JTAG interface.
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS core tiles. The ProASIC3 VersaTile supports the following: All 3-input logic functionsLUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set
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ProASIC3 Flash Family FPGAs Refer to Figure 1-3 for VersaTile configurations.
LUT-3 Equivalent X1 X2 X3
D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF
Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y
LUT-3
Figure 1-3
VersaTile Configurations
User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management
The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel ProASIC3 development software solutions, Libero Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO

ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices).
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ProASIC3 Device Family Overview In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC

ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz Clock delay adjustment via programmable and fixed delays from 7.56 ns to +11.12 ns 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time = 300 s (for PLL only) Low power consumption of 5 mW Exceptional tolerance to input period jitter allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps (350 MHz / fOUT_CCC) (for PLL only)
Additional CCC specifications:
Global Clocking
ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.
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I/Os with Advanced I/O Standards

The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standardssingle-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Table 1-1 I/O Standards Supported I/O Standards Supported I/O Bank Type Advanced Standard Plus Device and Bank Location East and west Banks of A3P250 and larger devices North and south banks of A3P250 and larger devices All banks of A3P060 and A3P125 Standard All banks of A3P015 and A3P030 LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS
Not supported
Not supported
Not supported
Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: Single-Data-Rate applications Double-Data-Rate applicationsDDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating.
Wide Range I/O Support

Actel ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications.
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2 ProASIC3 DC and Switching Characteristics

General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 Absolute Maximum Ratings Symbol VCC VJTAG VPUMP Parameter DC core supply voltage JTAG DC voltage Programming voltage Limits 0.3 to 1.65 0.3 to 3.75 0.3 to 3.75 0.3 to 1.65 0.3 to 3.75 0.3 to 3.75 0.3 V to 3.6 V (when I/O hot insertion mode is enabled) 0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 TJ 2 Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.
Units V V V V V V V
VCCPLL Analog power supply (PLL) VCCI VMV VI DC I/O output buffer supply voltage DC I/O input buffer supply voltage I/O input voltage
Storage temperature Junction temperature
65 to +150 +125
C C
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ProASIC3 DC and Switching Characteristics Table 2-2 Recommended Operating Conditions 1,2 Symbol TA TJ VCC3 VJTAG VPUMP Parameter Ambient temperature Junction temperature 1.5 V DC core supply voltage JTAG DC voltage Programming voltage Programming Mode Operation VCCPLL VCCI and VMV Analog power supply (PLL) 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage 3.3 V wide range DC supply voltage 5
4
Commercial 0 to +70 0 to 85 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6
Industrial -40 to +85 -40 to 100 1.425 to 1.575 1.4 to 3.6 3.0 to 3.6 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6
Units C
V V V V V V V V V V V V
LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actels timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-19. VMV and VCCI should be at the same voltage within a given I/O bank. 4. VPUMP can be left floating during operation (not programming mode). 5. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.
Table 2-3 Flash Programming Limits Retention, Storage and Operating Temperature1 Product Grade Commercial Industrial Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.
Programmin g Cycles 500 500
Maximum Operating Program Retention Maximum Storage (biased/unbiased) Temperature TSTG (C) 2 Junction Temperature TJ (C) 2 20 years 110 100 20 years 110 100
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ProASIC3 Flash Family FPGAs Table 2-4 Overshoot and Undershoot Limits 1 VCCI and VMV 2.7 V or less 3V 3.3 V 3.6 V Notes:
1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits.
Average VCCIGND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 10% 5% 10% 5% 10% 5% 10% 5%
Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric Users Guide for information on clock and lock recovery.
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Internal Power-Up Activation Sequence

1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V
Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc.
Region 1: I/O Buffers are OFF
VCC = 1.425 V
Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V
VCCI
Figure 2-1
I/O State as a Function of VCCI and VCC Voltage Levels
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Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation
Package Thermal Characteristics

The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) Max. ambient temp. (C) 100C 70C Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.463 W ja (C/W) 20.5C/W EQ 2 Table 2-5 Package Thermal Resistivities ja Package Type Quad Flat No Lead Device A3P030 A3P060 A3P125 A3P250 Very Thin Quad Flat Pack (VQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP) PQFP with embedded heatspreader Fine Pitch Ball Grid Array (FBGA) All devices All devices All devices All devices See note* See note* See note* A3P1000 A3P1000 A3P1000 Pin Count 132 132 132 132 100 144 208 208 144 256 484 144 256 484 jc 0.4 0.3 0.2 0.1 10.0 11.0 8.0 3.8 3.8 3.8 3.2 6.3 6.6 8.0 Still Air 200 ft./min. 21.4 21.2 21.1 21.0 35.3 33.5 26.1 16.2 26.9 26.6 20.5 31.6 28.1 23.3 16.8 16.6 16.5 16.4 29.4 28.0 22.5 13.3 22.9 22.8 17.0 26.2 24.4 19.0 500 ft./min. Units 15.3 15.0 14.9 14.8 27.1 25.7 20.8 11.9 21.5 21.5 15.9 24.2 22.7 16.7 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
* This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet.
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Temperature and Voltage Derating Factors

Table 2-6 Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) Array Voltage VCC (V) 1.425 1.500 1.575 Junction Temperature (C) 40C 0.88 0.83 0.80 0C 0.93 0.88 0.84 25C 0.95 0.90 0.87 70C 1.00 0.95 0.91 85C 1.02 0.96 0.93 100C 1.04 0.98 0.94
Calculating Power Dissipation

Quiescent Supply Current
Table 2-7 Quiescent Supply Current Characteristics A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Typical (25C) Max. (Commercial) Max. (Industrial) 2 mA 10 mA 15 mA 2 mA 10 mA 15 mA 2 mA 10 mA 15 mA 2 mA 10 mA 15 mA 3 mA 20 mA 30 mA 3 mA 20 mA 30 mA 5 mA 30 mA 45 mA 8 mA 50 mA 75 mA
Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-11 and Table 2-12 on page 2-8.
Power per I/O Pin

Table 2-8 Summary of I/O Input Buffer Power (Per Pin) Default I/O Software Settings Applicable to Advanced I/O Banks VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes:
1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
3
Static Power PDC2 (mW) 1 2.26 5.72
Dynamic Power PAC9 (W/MHz) 2 16.22 16.22 5.12 2.13 1.45 18.11 18.11 1.20 1.87
3.3 3.3 2.5 1.8 1.5 3.3 3.3 2.5 3.3
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ProASIC3 Flash Family FPGAs Table 2-9 Summary of I/O Input Buffer Power (Per Pin) Default I/O Software Settings Applicable to Standard Plus I/O Banks VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Notes:
3
Static Power PDC2 (mW) 1
Dynamic Power PAC9 (W/MHz) 2
3.3 3.3 2.5 1.8 1.5 3.3 3.3
16.23 16.23 5.14 2.13 1.48 18.13 18.13
Table 2-10 Summary of I/O Input Buffer Power (Per Pin) Default I/O Software Settings Applicable to Standard I/O Banks VMV (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) Notes:
3.3 3.3 2.5 1.8 1.5
17.24 17.24 5.19 2.18 1.52
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ProASIC3 DC and Switching Characteristics Table 2-11 Summary of I/O Output Buffer Power (per pin) Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes:
1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCC and VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
4
VCCI (V)
Static Power PDC3 (mW)2
Dynamic Power PAC10 (W/MHz)3
35 35 35 35 35 10 10
3.3 3.3 2.5 1.8 1.5 3.3 3.3
468.67 468.67 267.48 149.46 103.12 201.02 201.02
2.5 3.3
7.74 19.54
88.92 166.52
Table 2-12 Summary of I/O Output Buffer Power (Per Pin) Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range4 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Notes:
1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VMV. PAC10 is the total dynamic power measured on VCC and VMV. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
VCCI (V)
Static Power PDC3 (mW)2
Dynamic Power PAC10 (W/MHz)3
35 35 35 35 35 10 10
3.3 3.3 2.5 1.8 1.5 3.3 3.3
452.67 452.67 258.32 133.59 92.84 184.92 184.92
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ProASIC3 Flash Family FPGAs Table 2-13 Summary of I/O Output Buffer Power (Per Pin) Default I/O Software Settings 1 Applicable to Standard I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) Notes:
1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCC and VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
4
VCCI (V)
35 35 35 35 35
3.3 3.3 2.5 1.8 1.5
431.08 431.08 247.36 128.46 89.46
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Power Consumption of Various Internal Resources

Table 2-14 Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices Device Specific Dynamic Contributions (W/MHz) A3P1000 A3P600 A3P400 A3P250 A3P125 A3P060 A3P030 A3P015
Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13
Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial Module Average contribution of a routing net Contribution of an I/O input pin (standard dependent) Contribution of an I/O output pin (standard dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL
14.50 12.80 12.80 11.00 11.00 9.30 2.48 1.85 1.35 1.58 0.81 0.12 0.07 0.29 0.29 0.70 0.81 0.81
9.30 9.30 0.41 0.41
See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. 25.00 30.00 2.60
Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero Integrated Design Environment (IDE) software.
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ProASIC3 Flash Family FPGAs Table 2-15 Different Components Contributing to the Static Power Consumption in ProASIC3 Devices Definition A3P1000 Device Specific Static Power (mW) A3P600 A3P400 A3P250 A3P125 A3P060 A3P030 A3P015
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Parameter PDC1 PDC2 PDC3 PDC4 PDC5 Array static power in Active mode I/O input pin static power (standard-dependent) I/O output pin static power (standard-dependent) Static PLL contribution Bank quiescent power (VCCI -dependent)
See Table 2-7 on page 2-6. See Table 2-8 on page 2-6 through Table 2-10 on page 2-7. See Table 2-11 on page 2-8 through Table 2-13 on page 2-9. 2.55 mW See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel
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Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTilesguidelines are provided in Table 2-16 on page 2-14. Enable rates of output buffersguidelines are provided for typical applications in Table 2-17 on page 2-14. Read rate and write rate to the memoryguidelines are provided for typical applications in Table 2-17 on page 2-14. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power ConsumptionPTOTAL
PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption.
Total Static Power ConsumptionPSTAT

PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power ConsumptionPDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock ContributionPCLOCK

PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user designguidelines are provided in Table 2-16 on page 2-14. NROW is the number of VersaTile rows used in the designguidelines are provided in Table 2-16 on page 2-14. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells ContributionPS-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputsguidelines are provided in Table 2-16 on page 2-14.
FCLK is the global clock signal frequency.
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Combinatorial Cells ContributionPC-CELL

PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. FCLK is the global clock signal frequency.
Routing Net ContributionPNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
I/O Input Buffer ContributionPINPUTS

PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency.
2 is the I/O buffer toggle rateguidelines are provided in Table 2-16 on page 2-14.
I/O Output Buffer ContributionPOUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rateguidelines are provided in Table 2-16 on page 2-14. 1 is the I/O buffer enable rateguidelines are provided in Table 2-17 on page 2-14.
RAM ContributionPMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
3 is the RAM enable rate for write operationsguidelines are provided in Table 2-17 on page 2-14.
PLL ContributionPPLL
PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1
FWRITE-CLOCK is the memory write clock frequency.
1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
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Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: Bit 0 (LSB) = 100% Bit 1 Bit 2 Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25%
Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-16 Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10%
1 2
Component
Table 2-17 Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5%
1 2 3
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User I/O Characteristics

Timing Model
I/O Module (Non-Registered) Combinational Cell Y tPD = 0.56 ns Combinational Cell Y tPD = 0.49 ns tDP = 1.34 ns Combinational Cell Y tPD = 0.87 ns Combinational Cell I/O Module (Registered) tPY = 1.05 ns LVPECL (Applicable to Advanced I/O Banks only) D Q tPD = 0.47 ns Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns Input LVTTL Clock Register Cell tPY = 0.76 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.20 ns Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) D Q Combinational Cell Register Cell Y tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) D Q D tPD = 0.47 ns Y LVTTL Output drive strength = 8 mA High slew rate tDP = 3.66 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 3.97 ns (Advanced I/O Banks) I/O Module (Registered) Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate I/O Module (Non-Registered) LVTTL Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVPECL (Applicable to Advanced I/O Banks Only)L
tDP = 2.64 ns (Advanced I/O Banks) tOCLKQ = 0.59 ns tOSUD = 0.31 ns
Figure 2-2
Timing Model Operating Conditions: 2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC = 1.425 V
Revision 9
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tPY
tDIN
PAD
D Y
Q DIN To Array
CLK
tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))
I/O Interface
VIH
PAD
Vtrip
Vtrip VCC
VIL
50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R)
Figure 2-3 Input Buffer Timing Model and Delays (example)
50%
50% tDOUT (F)
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tDOUT D Q DOUT D From Array I/O Interface CLK
tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC 50% 50% VOH Vtrip Vtrip VOL tDP (R) tDP (F) (F)
tDOUT (R) 50%
0V
DOUT
0V
PAD
Figure 2-4
Output Buffer Model and Delays (example)
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tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS
CLK
EOUT D D Q DOUT CLK PAD
I/O Interface
tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC
D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI Vtrip 10% VCCI 50% tZH VCCI 50% tLZ
VCC D VCC E 50% tEOUT (R) 50% tZLS PAD Vtrip VOL Vtrip 50% VCC EOUT 50% VOH 50% tZHS tEOUT (F)
Figure 2-5
Tristate Output Buffer Timing Model and Delays (example)
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Overview of I/O Performance

Summary of I/O DC Input and Output Levels Default I/O Software Settings
Table 2-18 Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ConditionsSoftware Default Settings Applicable to Advanced I/O Banks Equiv. Software Default Drive Drive Strength Slew Min. I/O Standard Strength Option2 Rate V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes:
1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
VIL
VIH
VOL
VOH
IOL1 IOH1
Max. V 0.8
Min. V 2
Max. V 3.6
Max. V 0.4
Min. V 2.4
mA mA 12 12
12 mA
12 mA
High 0.3
100 A
12 mA
High 0.3
0.8
3.6
0.2
VCCI 0.2
0.1 0.1
12 mA 12 mA 12 mA
12 mA 12 mA 12 mA
High 0.3
0.7
1.7
2.7
0.7 0.45
1.7
12
12 12 12
High 0.3 0.35 * VCCI 0.65 * VCCI 1.9 High 0.3 0.35 * VCCI 0.65 * VCCI 1.6 Per PCI specifications Per PCI-X specifications
VCCI 0.45 12
0.25 * VCCI 0.75 * VCCI 12
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ProASIC3 DC and Switching Characteristics Table 2-19 Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ConditionsSoftware Default Settings Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Drive Strength Slew Min. I/O Standard Strength Option2 Rate V 3.3 V LVTTL / 12 mA 3.3 V LVCMOS 100 A 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes:
1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
VIL
VIH
VOL
VOH
IOL1 IOH1
Max. V 0.8
Min. V 2
Max. V 3.6
Max. V 0.4
Min. V 2.4
mA mA 12 12
12 mA
High 0.3
12 mA
High 0.3
0.8
3.6
0.2
VCCI 0.2
0.1 0.1
12 mA 8 mA 4 mA
12 mA 8 mA 4 mA
High 0.3
0.7
1.7
2.7
0.7 0.45
1.7 VCCI 0.45
12 8 4
12 8 4
High 0.3 0.35 * VCCI 0.65 * VCCI 1.9
High 0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI Per PCI specifications Per PCI-X specifications
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ProASIC3 Flash Family FPGAs Table 2-20 Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ConditionsSoftware Default Settings Applicable to Standard I/O Banks Equiv. Softwar e Default Drive Drive Strength Slew Min. I/O Standard Strength Option2 Rate V 3.3 V LVTTL / 3.3 V LVCMOS 8 mA 8 mA High 0.3 VIL VIH VOL VOH IOL1 IOH1
Max. V 0.8
Min. V 2
Max. V 3.6
Max. V 0.4
Min. V 2.4
mA mA 8 8
100 A 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 8 mA 4 mA 2 mA
8 mA
High 0.3
0.8
3.6
0.2
VCCI 0.2
0.1 0.1
8 mA 4 mA 2 mA
High 0.3
0.7
1.7
3.6 3.6 3.6
0.7 0.45 0.25 * VCCI
1.7 VCCI 0.45 0.75 * VCCI
8 4 2
8 4 2
High 0.3 0.35 * VCCI 0.65 * VCCI High 0.3 0.35 * VCCI 0.65 * VCCI
1. Currents are measured at 85C junction temperature. 2. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-21 Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL3 DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes:
1. Commercial range (0C < TA < 70C) 2. Industrial range (40C < TA < 85C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3V < VIN <VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges.
Industrial2 IIL3 A 15 15 15 15 15 15 15 IIH4 A 15 15 15 15 15 15 15 A 10 10 10 10 10 10 10
IIH4
A 10 10 10 10 10 10 10
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Summary of I/O Timing Characteristics Default I/O Software Settings

Table 2-22 Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI Measuring Trip Point (Vtrip) 1.4 V 1.4 V 1.2 V 0.90 V 0.75 V 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF) Table 2-23 I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output BufferHigh to Z Enable to Pad delay through the Output BufferZ to High Enable to Pad delay through the Output BufferLow to Z Enable to Pad delay through the Output BufferZ to Low Enable to Pad delay through the Output Buffer with delayed enableZ to High Enable to Pad delay through the Output Buffer with delayed enableZ to Low
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ProASIC3 Flash Family FPGAs Table 2-24 Summary of I/O Timing CharacteristicsSoftware Default Settings 2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Advanced I/O Banks Equiv. Software Default Drive Strength Option1 External Resistor () Capacitive Load (pF)
Drive Strength
Slew Rate
tDOUT (ns)
tEOUT (ns)
tZH (ns)
tPY (ns)
tZL (ns)
tHZ (ns)
tZHS (ns)
tDIN (ns)
tDP (ns)
tZLS (ns)
tLZ (ns)
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS
12 mA
12 mA High 35
0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 0.45 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns 0.45 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
3.3 V LVCMOS 100 A 12 mA High 35 Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 12 mA 12 mA High 35 12 mA 12 mA Per PCI spec Per PCI-X spec 24 mA 24 mA 12 mA High 35 12 mA High 35
High 10 25
3.3 V PCI-X
High 10 25 4 0.45 2.00 0.03 0.62 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
LVDS LVPECL Notes:
High High
0.45 1.37 0.03 1.20 0.45 1.34 0.03 1.05
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-66 for connectivity. This resistor is not required during normal operation.
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Units ns ns
ProASIC3 DC and Switching Characteristics Table 2-25 Summary of I/O Timing CharacteristicsSoftware Default Settings 2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard Plus I/O Banks Equiv. Software Default Drive Strength Option1 Capacitive Load (pF)
External Resistor
Drive Strength
tDOUT (ns)
tEOUT (ns)
tZH (ns)
tPY (ns)
tZL (ns)
tHZ (ns)
tZHS (ns)
tDIN (ns)
tDP (ns)
tZLS (ns)
tLZ (ns)
I/O Standard
3.3 V LVTTL / 12 mA 12 mA 3.3 V LVCMOS 3.3 V LVCMOS 100 A 12 mA Wide Range2 2.5 V LVCMOS 12 mA 12 mA 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 8 mA 4 mA Per PCI spec Per PCI-X spec 8 mA 4 mA
High High High High High High
35 35 35 35 35 10
0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 ns 0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 3.78
25
4
0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 ns 0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 ns 0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 ns 0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 ns
3.3 V PCI-X
High
10
25 4 0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 ns
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-66 for connectivity. This resistor is not required during normal operation.
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Units
ProASIC3 Flash Family FPGAs Table 2-26 Summary of I/O Timing CharacteristicsSoftware Default Settings 2 Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst-Case VCCI (per standard) Standard I/O Banks Equiv. Software Default Drive Strength Option1 Capacitive Load (pF)
External Resistor
Drive Strength
Slew Rate
tDOUT (ns)
tDIN (ns)
tDP (ns)
tEOUT (ns)
tZH (ns)
tPY (ns)
tZL (ns)
tHZ (ns)
tLZ (ns)
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS
8 mA
8 mA
High High High High High
35 35 35 35 35
0.45 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77
ns
3.3 V LVCMOS 100 A 8 mA Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 8 mA 4 mA 2 mA 8 mA 4 mA 2 mA
3.11 4.36 ns ns ns
0.45 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 0.45 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 0.45 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 9
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Detailed I/O DC Characteristics

Table 2-27 Input Capacitance Symbol CIN CINCLK Definition Input capacitance Input capacitance on the clock pin Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF
Table 2-28 I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 3.3 V LVCMOS Wide Range4 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 3.3 V PCI/PCI-X Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax VOHspec) / IOHspec 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
RPULL-DOWN ()2 100 100 50 50 25 17 11 TBD 100 100 50 50 25 20 11 200 100 50 50 20 20 200 100 67 33 33 25
RPULL-UP ()3 300 300 150 150 75 50 33 TBD 200 200 100 100 50 40 22 225 112 56 56 22 22 224 112 75 37 37 75
Per PCI/PCI-X specification
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ProASIC3 Flash Family FPGAs Table 2-29 I/O Output Buffer Maximum Resistances 1 Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS
4
RPULL-DOWN ()2 100 100 50 50 25 25 TBD 100 100 50 50 25 200 100 50 50 200 100 25
RPULL-UP ()3 300 300 150 150 75 75 TBD 200 200 100 100 50 225 112 56 56 224 112 75
100 A 2 mA 4 mA 6 mA 8 mA 12 mA
1.8 V LVCMOS
2 mA 4 mA 6 mA 8 mA
1.5 V LVCMOS
2 mA 4 mA
3.3 V PCI/PCI-X Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax VOHspec) / IO H spec 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
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ProASIC3 DC and Switching Characteristics Table 2-30 I/O Output Buffer Maximum Resistances1 Applicable to Standard I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS
4
RPULL-DOWN ()2 100 100 50 50 TBD 100 100 50 50 200 100 200
RPULL-UP ()3 300 300 150 150 TBD 200 200 100 100 225 112 224
100 A 2 mA 4 mA 6 mA 8 mA
1.8 V LVCMOS
2 mA 4 mA
1.5 V LVCMOS Notes:
2 mA
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax VOHspec) / IOHspec 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-31 I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () VCCI 3.3 V 3.3 V (wide range I/Os) 2.5 V 1.8 V 1.5 V Notes:
1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax VOHspec) / I(WEAK PULL-UP-MIN)
R(WEAK PULL-DOWN)2 () Min. 10 k 10 k 12 k 17 k 19 k Max. 45 k 45 k 74 k 110 k 140 k
Min. 10 k 10 k 11 k 18 k 19 k
Max. 45 k 45 k 55 k 70 k 90 k
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ProASIC3 Flash Family FPGAs Table 2-32 I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS
2
IOSL (mA)1 27 27 54 54 109 127 181 TBD 18 18 37 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 109
IOSH (mA)1 25 25 51 51 103 132 268 TBD 16 16 32 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 103
100 A 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
1.8 V LVCMOS
2 mA 4 mA 6 mA 8 mA 12 mA 16 mA
1.5 V LVCMOS
2 mA 4 mA 6 mA 8 mA 12 mA
3.3 V PCI/PCI-X Notes:
1. TJ = 100C 2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
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ProASIC3 DC and Switching Characteristics Table 2-33 I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 3.3 V PCI/PCI-X Notes:
1. TJ = 100C 2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
IOSL (mA)* 27 27 54 54 109 109 TBD 18 18 37 37 74 11 22 44 44 16 33 109
IOSH (mA)* 25 25 51 51 103 103 TBD 16 16 32 32 65 9 17 35 35 13 25 103
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ProASIC3 Flash Family FPGAs Table 2-34 I/O Short Currents IOSH/IOSL Applicable to Standard I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 1.5 V LVCMOS Notes:
1. TJ = 100C 2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
IOSL (mA)* 27 27 54 54 TBD 18 18 37 37 11 22 16
IOSH (mA)* 25 25 51 51 TBD 16 16 32 32 9 17 13
2 mA 4 mA 2 mA
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-35 Duration of Short Circuit Event before Failure Temperature 40C 0C 25C 70C 85C 100C 110C Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months
Table 2-36 I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/ M-LVDS/LVPEC L Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * 10 ns * Reliability 20 years (110C) 10 years (100C)
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
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Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage TransistorTransistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100C junction temperature and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.4 0.4 0.4 0.4 0.4 0.4 0.4
VOH Min. V 2.4 2.4 2.4 2.4 2.4 2.4 2.4
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 27 27 54 54 109 127 181
IOSH Max. mA3 25 25 51 51 103 132 268
IIL1 IIH2 A4 A4 10 10 10 10 10 10 10 10 10 10 10 10 10 10
12 12 16 16 24 24
Table 2-38 Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes:
VIL Min. V 0.3 0.3 0.3 0.3 0.3 0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.4 0.4 0.4 0.4 0.4 0.4
VOH Min. V 2.4 2.4 2.4 2.4 2.4 2.4
IOL mA 2 4 6 8 12 16
IOH mA 2 4 6 8 12 16
IOSL Max. mA3 27 27 54 54 109 109
IOSH Max. mA3 25 25 51 51 103 103
IIL1
IIH2
A4 A4 10 10 10 10 10 10 10 10 10 10 10 10
2- 32
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ProASIC3 Flash Family FPGAs Table 2-39 Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
VIL Min. V 0.3 0.3 0.3 0.3 Max. V 0.8 0.8 0.8 0.8 Min. V 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.4 0.4 0.4 0.4
VOH Min. V 2.4 2.4 2.4 2.4
IOL
IOH
IOSL Max. mA3 25 25 51 51
IOSH Max. mA3 27 27 54 54
IIL1 IIH2 A4 A4 10 10 10 10 10 10 10 10
mA mA 2 4 6 8 2 4 6 8
Test Point Datapath 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-6
AC Loading
Table 2-40 AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 35
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Revision 9
2- 33
Timing Characteristics
Table 2-41 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 24 mA Std. 1 2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 7.66 6.51 5.72 4.91 4.17 3.66 4.91 4.17 3.66 3.53 3.00 2.64 3.33 2.83 2.49 3.08 2.62 2.30
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.80 6.63 5.82 5.00 4.25 3.73 5.00 4.25 3.73 3.60 3.06 2.69 3.39 2.89 2.53 3.13 2.66 2.34
tZH 6.59 5.60 4.92 4.07 3.46 3.04 4.07 3.46 3.04 2.82 2.40 2.11 2.56 2.18 1.91 2.12 1.80 1.58
tLZ 2.65 2.25 1.98 2.99 2.54 2.23 2.99 2.54 2.23 3.21 2.73 2.40 3.26 2.77 2.44 3.32 2.83 2.48
tHZ 2.61 2.22 1.95 3.20 2.73 2.39 3.20 2.73 2.39 3.58 3.05 2.68 3.68 3.13 2.75 4.06 3.45 3.03
tZLS 10.03 8.54 7.49 7.23 6.15 5.40 7.23 6.15 5.40 5.83 4.96 4.36 5.63 4.79 4.20 5.37 4.57 4.01
tZHS 8.82 7.51 6.59 6.31 5.36 4.71 6.31 5.36 4.71 5.06 4.30 3.78 4.80 4.08 3.58 4.35 3.70 3.25
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2- 34
R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-42 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 24 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 10.26 8.72 7.66 7.27 6.19 5.43 7.27 6.19 5.43 5.58 4.75 4.17 5.21 4.43 3.89 4.85 4.13 3.62 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 1.02 0.86 0.76 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 10.45 8.89 7.80 7.41 6.30 5.53 7.41 6.30 5.53 5.68 4.84 4.24 5.30 4.51 3.96 4.94 4.20 3.69 tZH 8.90 7.57 6.64 6.28 5.35 4.69 6.28 5.35 4.69 4.87 4.14 3.64 4.56 3.88 3.41 4.54 3.87 3.39 tLZ 2.64 2.25 1.98 2.98 2.54 2.23 2.98 2.54 2.23 3.21 2.73 2.39 3.26 2.77 2.43 3.32 2.82 2.48 tHZ 2.46 2.09 1.83 3.04 2.59 2.27 3.04 2.59 2.27 3.42 2.91 2.55 3.51 2.99 2.62 3.88 3.30 2.90 tZLS 12.68 10.79 9.47 9.65 8.20 7.20 9.65 8.20 7.20 7.92 6.74 5.91 7.54 6.41 5.63 7.18 6.10 5.36 tZHS 11.13 9.47 8.31 8.52 7.25 6.36 8.52 7.25 6.36 7.11 6.05 5.31 6.80 5.79 5.08 6.78 5.77 5.06 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 9
2- 35
ProASIC3 DC and Switching Characteristics Table 2-43 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 7.20 6.13 5.38 4.50 3.83 3.36 4.50 3.83 3.36 3.16 2.69 2.36 3.16 2.69 2.36
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.34 6.24 5.48 4.58 3.90 3.42 4.58 3.90 3.42 3.22 2.74 2.40 3.22 2.74 2.40
tZH 6.29 5.35 4.69 3.82 3.25 2.85 3.82 3.25 2.85 2.58 2.20 1.93 2.58 2.20 1.93
tLZ 2.27 1.93 1.70 2.58 2.19 1.92 2.58 2.19 1.92 2.79 2.37 2.08 2.79 2.37 2.08
tHZ 2.34 1.99 1.75 2.88 2.45 2.15 2.88 2.45 2.15 3.22 2.74 2.41 3.22 2.74 2.41
tZLS 9.57 8.14 7.15 6.82 5.80 5.09 6.82 5.80 5.09 5.45 4.64 4.07 5.45 4.64 4.07
tZHS 8.52 7.25 6.36 6.05 5.15 4.52 6.05 5.15 4.52 4.82 4.10 3.60 4.82 4.10 3.60
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-44 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 9.68 8.23 7.23 6.70 5.70 5.00 6.70 5.70 5.00 5.05 4.29 3.77 5.05 4.29 3.77 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 9.86 8.39 7.36 6.82 5.80 5.10 6.82 5.80 5.10 5.14 4.37 3.84 5.14 4.37 3.84 tZH 8.42 7.17 6.29 5.89 5.01 4.40 5.89 5.01 4.40 4.51 3.84 3.37 4.51 3.84 3.37 tLZ 2.28 1.94 1.70 2.58 2.20 1.93 2.58 2.20 1.93 2.79 2.38 2.09 2.79 2.38 2.09 tHZ 2.21 1.88 1.65 2.74 2.33 2.05 2.74 2.33 2.05 3.08 2.62 2.30 3.08 2.62 2.30 tZLS 12.09 10.29 9.03 9.06 7.71 6.76 9.06 7.71 6.76 7.38 6.28 5.51 7.38 6.28 5.51 tZHS 10.66 9.07 7.96 8.12 6.91 6.06 8.12 6.91 6.06 6.75 5.74 5.04 6.75 5.74 5.04 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-45 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 7.07 6.01 5.28 7.07 6.01 5.28 4.41 3.75 3.29 4.41 3.75 3.29
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.20 6.12 5.37 7.20 6.12 5.37 4.49 3.82 3.36 4.49 3.82 3.36
tZH 6.23 5.30 4.65 6.23 5.30 4.65 3.75 3.19 2.80 3.75 3.19 2.80
tLZ 2.07 1.76 1.55 2.07 1.76 1.55 2.39 2.04 1.79 2.39 2.04 1.79
tHZ 2.15 1.83 1.60 2.15 1.83 1.60 2.69 2.29 2.01 2.69 2.29 2.01
Units ns ns ns ns ns ns ns ns ns ns ns ns
Revision 9
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ProASIC3 DC and Switching Characteristics Table 2-46 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 9.46 8.05 7.07 9.46 8.05 7.07 6.57 5.59 4.91 6.57 5.59 4.91 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 1.00 0.85 0.75 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 9.64 8.20 7.20 9.64 8.20 7.20 6.69 5.69 5.00 6.69 5.69 5.00 tZH 8.54 7.27 6.38 8.54 7.27 6.38 5.98 5.09 4.47 5.98 5.09 4.47 tLZ 2.07 1.76 1.55 2.07 1.76 1.55 2.40 2.04 1.79 2.40 2.04 1.79 tHZ 2.04 1.73 1.52 2.04 1.73 1.52 2.57 2.19 1.92 2.57 2.19 1.92 Units ns ns ns ns ns ns ns ns ns ns ns ns
2- 38
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3.3 V LVCMOS Wide Range

Table 2-47 Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V Equiv. LVCMOS Software Wide Range Default Drive Drive Strength Strength Option1 100 A 100 A 100 A 100 A 100 A 100 A 100 A Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 6. Software default selection highlighted in gray.
VIL Min. V 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.2 0.2 0.2 0.2 0.2 0.2 0.2
VOH Min. V
IOL IOH
IOSL Max. mA4 TBD TBD TBD TBD TBD TBD TBD
IOSH Max. mA4 TBD TBD TBD TBD TBD TBD TBD
IIL2 IIH3 A5 A5 10 10 10 10 10 10 10 10 10 10 10 10 10 10
A A
2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA
VDD 0.2 100 100 VDD 0.2 100 100 VDD 0.2 100 100 VDD 0.2 100 100 VDD 0.2 100 100 VDD 0.2 100 100 VDD 0.2 100 100
Table 2-48 Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3
Drive Strength 100 A 100 A 100 A 100 A 100 A 100 A Notes:
Min. V 0.3 0.3 0.3 0.3 0.3 0.3
Max. V 0.8 0.8 0.8 0.8 0.8 0.8
Min. Max. V V 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6
Max. V 0.2 0.2 0.2 0.2 0.2 0.2
Min. V VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2
Max. mA4 TBD TBD TBD TBD TBD TBD
Max. mA4 TBD TBD TBD TBD TBD TBD
A5 A5 10 10 10 10 10 10 10 10 10 10 10 10
100 100 100 100 100 100 100 100 100 100 100 100
Revision 9
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ProASIC3 DC and Switching Characteristics Table 2-49 Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVCMOS Wide Range Drive Strength 100 A 100 A 100 A 100 A Notes:
Equiv. Software VIL Default Drive Strength Min. Max. V V Option1 2 mA 4 mA 6 mA 8 mA 0.3 0.3 0.3 0.3 0.8 0.8 0.8 0.8
VIH Min. V 2 2 2 2 Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.2 0.2 0.2 0.2
VOH Min. V VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2
IOL IOH
IOSL Max. mA4 TBD TBD TBD TBD
IOSH Max. mA4 TBD TBD TBD TBD
IIL2 IIH3 A A
5 5
A A 100 100 100 100 100 100 100 100
10 10 10 10 10 10 10 10
2- 40
R e visio n 9
Table 2-50 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Equiv. Software Default Drive Strength Option1 4 mA
Drive Strength 100 A
Speed Grade Std. 1 2
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP
tDIN
tPY
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11.84 0.04 1.02 10.07 0.04 0.86 8.84 7.59 6.45 5.67 7.59 6.45 5.67 5.46 4.65 4.08 5.15 4.38 3.85 4.75 4.04 3.55 0.03 0.76 0.04 1.02 0.04 0.86 0.03 0.76 0.04 1.02 0.04 0.86 0.03 0.76 0.04 1.02 0.04 0.86 0.03 0.76 0.04 1.02 0.04 0.86 0.03 0.76 0.04 1.02 0.04 0.86 0.03 0.76
11.84 10.00 4.10 4.04 15.23 13.40 10.07 8.84 7.59 6.45 5.67 7.59 6.45 5.67 5.46 4.65 4.08 5.15 4.38 3.85 4.75 4.04 3.55 8.51 7.47 6.18 5.25 4.61 6.18 5.25 4.61 4.29 3.65 3.20 3.89 3.31 2.91 3.22 2.74 2.40 3.48 3.44 12.96 11.40 3.06 3.02 11.38 10.00 4.62 4.95 10.98 3.93 4.21 3.45 3.70 9.34 8.20 9.57 8.14 7.15 9.57 8.14 7.15 7.68 6.54 5.74 7.29 6.20 5.44 6.61 5.62 4.94
100 A
6 mA
Std. 1 2
100 A
8 mA
Std. 1 2
4.62 4.95 10.98 3.93 4.21 3.45 3.70 4.97 5.54 4.22 4.71 3.71 4.14 5.04 5.69 4.29 4.84 3.77 4.25 5.14 6.28 4.37 5.34 3.84 4.69 9.34 8.20 8.86 7.53 6.61 8.55 7.27 6.38 8.15 6.93 6.09
100 A
12 mA
Std. 1 2
100 A
16 mA
Std. 1 2
100 A
24 mA
Std. 1 2
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 9
2- 41
ProASIC3 DC and Switching Characteristics Table 2-51 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Equiv. Software Default Drive Strength Option1 2 mA
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP
tDIN
tPY
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15.86 0.04 1.54 13.49 0.04 1.31 11.84 0.03 1.15 11.25 0.04 1.54 9.57 8.40 0.04 1.31 0.03 1.15
15.86 13.51 4.09 3.80 19.25 16.90 13.49 11.49 3.48 3.23 16.38 14.38 11.84 10.09 3.05 2.84 14.38 12.62 11.25 9.57 8.40 11.25 9.57 8.40 8.63 7.34 6.44 8.05 6.85 6.01 7.50 6.38 5.60 9.54 8.11 7.12 9.54 8.11 7.12 7.39 6.29 5.52 6.93 5.90 5.18 6.90 5.87 5.15 4.61 4.70 14.64 12.93 3.92 4.00 12.46 11.00 3.44 3.51 10.93 9.66
100 A
4 mA
Std. 1 2
100 A
6 mA
Std. 1 2
11.25 0.04 1.54 9.57 8.40 8.63 7.34 6.44 8.05 6.85 6.01 7.50 6.38 5.60 0.04 1.31 0.03 1.15 0.04 1.54 0.04 1.31 0.03 1.15 0.04 1.54 0.04 1.31 0.03 1.15 0.04 1.54 0.04 1.31 0.03 1.15
4.61 4.70 14.64 12.93 3.92 4.00 12.46 11.00 3.44 3.51 10.93 9.66
100 A
8 mA
Std. 1 2
4.96 5.28 12.02 10.79 4.22 4.49 10.23 3.70 3.94 8.98 9.18 8.06
100 A
16 mA
Std. 1 2
5.03 5.43 11.44 10.32 4.28 4.62 3.76 4.06 9.74 8.55 8.78 7.71
100 A
24 mA
Std. 1 2
5.13 6.00 10.89 10.29 4.36 5.11 3.83 4.48 9.27 8.13 8.76 7.69
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for normal ranges ONLY. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2- 42
R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-52 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Strength Option1 2 mA
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP
tDIN
tPY
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 11.14 9.48 8.32 6.96 5.92 5.20 6.96 5.92 5.20 4.89 4.16 3.65 4.89 4.16 3.65
tZH 9.54 8.12 7.13 5.79 4.93 4.33 5.79 4.93 4.33 3.92 3.34 2.93 3.92 3.34 2.93
tLZ
tHZ
tZLS
tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11.14 0.04 1.52 9.48 8.32 6.96 5.92 5.20 6.96 5.92 5.20 4.89 4.16 3.65 4.89 4.16 3.65 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14
3.51 3.61 14.53 12.94 2.99 3.07 12.36 11.00 2.62 2.70 10.85 3.99 4.45 10.35 3.39 3.78 2.98 3.32 8.81 7.73 9.66 9.19 7.82 6.86 9.19 7.82 6.86 7.32 6.22 5.46 7.32 6.22 5.46
100 A
4 mA
Std. 1 2
100 A
6 mA
Std. 1 2
3.99 4.45 10.35 3.39 3.78 2.98 3.32 4.31 4.98 3.67 4.24 3.22 3.72 4.31 4.98 3.67 4.24 3.22 3.72 8.81 7.73 8.28 7.04 6.18 8.28 7.04 6.18
100 A
8 mA
Std. 1 2
100 A
16 mA
Std. 1 2
Notes:
Revision 9
2- 43
ProASIC3 DC and Switching Characteristics Table 2-53 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Strength Option1 2 mA
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP
tDIN
tPY
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL
tZH
tLZ
tHZ
tZLS
tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
14.97 0.04 1.52 12.73 0.04 1.29 11.18 0.03 1.14 10.36 0.04 1.52 8.81 7.74 0.04 1.29 0.03 1.14
14.97 12.79 3.52 3.41 18.36 16.18 12.73 10.88 2.99 2.90 15.62 13.77 11.18 10.36 8.81 7.74 10.36 8.81 7.74 7.81 6.64 5.83 7.81 6.64 5.83 9.55 8.93 7.60 6.67 8.93 7.60 6.67 6.85 5.82 5.11 6.85 5.82 5.11 2.63 2.55 13.71 12.08 3.99 4.24 13.75 12.33 3.39 3.60 11.70 10.49 2.98 3.16 10.27 9.21
100 A
4 mA
Std. 1 2
100 A
6 mA
Std. 1 2
10.36 0.04 1.52 8.81 7.74 7.81 6.64 5.83 7.81 6.64 5.83 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14 0.04 1.52 0.04 1.29 0.03 1.14
3.99 4.24 13.75 12.33 3.39 3.60 11.70 10.49 2.98 3.16 10.27 9.21
100 A
8 mA
Std. 1 2
4.32 4.76 11.20 10.24 3.67 4.05 3.22 3.56 9.53 8.36 8.71 7.65
100 A
16 mA
Std. 1 2
4.32 4.76 11.20 10.24 3.67 4.05 3.22 3.56 9.53 8.36 8.71 7.65
Notes:
2- 44
R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-54 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Equiv. Software Default Drive Strength Option1 2 mA
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 10.93 9.29 8.16 10.93 9.29 8.16 6.82 5.80 5.09 6.82 5.80 5.09
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 10.93 9.29 8.16 10.93 9.29 8.16 6.82 5.80 5.09 6.82 5.80 5.09
tZH 9.46 8.04 7.06 9.46 8.04 7.06 5.70 4.85 4.25 5.70 4.85 4.25
tLZ 3.20 2.72 2.39 3.20 2.72 2.39 3.70 3.15 2.77 3.70 3.15 2.77
tHZ 3.32 2.82 2.48 3.32 2.82 2.48 4.16 3.54 3.11 4.16 3.54 3.11
100 A
4 mA
Std. 1 2
100 A
6 mA
Std. 1 2
100 A
8 mA
Std. 1 2
Notes:
Revision 9
2- 45
ProASIC3 DC and Switching Characteristics Table 2-55 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Equiv. Software Default Drive Strength Option1 2 mA
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 14.64 12.45 10.93 14.64 12.45 10.93 10.16 8.64 7.58 10.16 8.64 7.58
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 14.64 12.45 10.93 14.64 12.45 10.93 10.16 8.64 7.58 10.16 8.64 7.58
tZH 12.97 11.04 9.69 12.97 11.04 9.69 9.08 7.73 6.78 9.08 7.73 6.78
tLZ 3.21 2.73 2.39 3.21 2.73 2.39 3.71 3.15 2.77 3.71 3.15 2.77
tHZ 3.15 2.68 2.35 3.15 2.68 2.35 3.98 3.39 2.97 3.98 3.39 2.97
100 A
4 mA
Std. 1 2
100 A
6 mA
Std. 1 2
100 A
8 mA
Std. 1 2
Notes:
2- 46
R e visio n 9
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 Vtolerant input buffer and push-pull output buffer. Table 2-56 Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Max. V 0.7 0.7 0.7 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7 1.7 1.7 1.7
VIH Max. V 2.7 2.7 2.7 2.7 2.7 2.7 2.7
VOL Max. V 0.7 0.7 0.7 0.7 0.7 0.7 0.7
VOH Min. V 1.7 1.7 1.7 1.7 1.7 1.7 1.7
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 18 18 37 37 74 87 124
IOSH Max. mA3 16 16 32 32 65 83 169
IIL1 IIH2 A4 A4 10 10 10 10 10 10 10 10 10 10 10 10 10 10
12 12 16 16 24 24
Table 2-57 Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes:
VIL 0.3 0.3 0.3 0.3 0.3 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7
VIH 2.7 2.7 2.7 2.7 2.7
VOL 0.7 0.7 0.7 0.7 0.7
VOH 1.7 1.7 1.7 1.7 1.7
IOL IOH 2 4 6 8 2 4 6 8
IOSL 18 18 37 37 74
IOSH 16 16 32 32 65
IIL1 IIH2 10 10 10 10 10 10 10 10 10 10
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA3 Max., mA3 A4 A4
12 12
Revision 9
2- 47
ProASIC3 DC and Switching Characteristics Table 2-58 Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V 0.3 0.3 0.3 0.3 Max., V 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7
VIH Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.7 0.7 0.7 0.7
VOH Min. V 1.7 1.7 1.7 1.7
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 16 16 32 32
IOSH Max. mA3 18 18 37 37
IIL1 IIH2 A4 A4 10 10 10 10 10 10 10 10
Figure 2-7
AC Loading
2- 48
R e visio n 9
Table 2-60 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 24 mA Std. 1 2 Notes:
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 8.66 7.37 6.47 5.17 4.39 3.86 5.17 4.39 3.86 3.56 3.03 2.66 3.35 2.85 2.50 3.09 2.63 2.31
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.83 6.66 5.85 5.04 4.28 3.76 5.04 4.28 3.76 3.63 3.08 2.71 3.41 2.90 2.55 3.15 2.68 2.35
tZH 8.66 7.37 6.47 5.17 4.39 3.86 5.17 4.39 3.86 3.43 2.92 2.56 3.06 2.60 2.29 2.44 2.08 1.82
tLZ 2.68 2.28 2.00 3.05 2.59 2.28 3.05 2.59 2.28 3.30 2.81 2.47 3.36 2.86 2.51 3.44 2.92 2.57
tHZ 2.30 1.96 1.72 3.00 2.55 2.24 3.00 2.55 2.24 3.44 2.92 2.57 3.55 3.02 2.65 4.00 3.40 2.98
tZLS 10.07 8.56 7.52 7.27 6.19 5.43 7.27 6.19 5.43 5.86 4.99 4.38 5.65 4.81 4.22 5.38 4.58 4.02
tZHS 10.90 9.27 8.14 7.40 6.30 5.53 7.40 6.30 5.53 5.67 4.82 4.23 5.30 4.51 3.96 4.68 3.98 3.49
Revision 9
2- 49
ProASIC3 DC and Switching Characteristics Table 2-61 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 24 mA Std. 1 2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 tDP 11.40 9.69 8.51 7.96 6.77 5.94 7.96 6.77 5.94 6.18 5.26 4.61 5.76 4.90 4.30 5.51 4.68 4.11 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 1.31 1.11 0.98 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 11.22 9.54 8.38 8.11 6.90 6.05 8.11 6.90 6.05 6.29 5.35 4.70 5.87 4.99 4.38 5.50 4.68 4.11 tZH 11.40 9.69 8.51 7.81 6.65 5.84 7.81 6.65 5.84 5.92 5.03 4.42 5.53 4.70 4.13 5.51 4.68 4.11 tLZ 2.68 2.28 2.00 3.05 2.59 2.28 3.05 2.59 2.28 3.30 2.81 2.47 3.36 2.86 2.51 3.43 2.92 2.56 tHZ 2.20 1.88 1.65 2.89 2.46 2.16 2.89 2.46 2.16 3.32 2.83 2.48 3.44 2.92 2.57 3.87 3.29 2.89 tZLS 13.45 11.44 10.05 10.34 8.80 7.72 10.34 8.80 7.72 8.53 7.26 6.37 8.11 6.90 6.05 7.74 6.58 5.78 tZHS 13.63 11.60 10.18 10.05 8.55 7.50 10.05 8.55 7.50 8.15 6.94 6.09 7.76 6.60 5.80 7.74 6.59 5.78 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2- 50
R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-62 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 8.28 7.04 6.18 4.85 4.13 3.62 4.85 4.13 3.62 3.21 2.73 2.39
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.30 1.10 0.97 1.30 1.10 0.97 1.30 1.10 0.97 1.30 1.10 0.97
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.41 6.30 5.53 4.65 3.95 3.47 4.65 3.95 3.47 3.27 2.78 2.44
tZH 8.28 7.04 6.18 4.85 4.13 3.62 4.85 4.13 3.62 3.14 2.67 2.35
tLZ 2.25 1.92 1.68 2.59 2.20 1.93 2.59 2.20 1.93 2.82 2.40 2.11
tHZ 2.07 1.76 1.55 2.71 2.31 2.02 2.71 2.31 2.02 3.11 2.65 2.32
tZLS 9.64 8.20 7.20 6.88 5.85 5.14 6.88 5.85 5.14 5.50 4.68 4.11
tZHS 10.51 8.94 7.85 7.09 6.03 5.29 7.09 6.03 5.29 5.38 4.57 4.02
Table 2-63 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA Speed Grade Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 10.84 9.22 8.10 7.37 6.27 5.50 7.37 6.27 5.50 5.63 4.79 4.20 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.30 1.10 0.97 1.30 1.10 0.97 1.30 1.10 0.97 1.30 1.10 0.97 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 10.64 9.05 7.94 7.50 6.38 5.60 7.50 6.38 5.60 5.73 4.88 4.28 tZH 10.84 9.22 8.10 7.36 6.26 5.50 7.36 6.26 5.50 5.51 4.68 4.11 tLZ 2.26 1.92 1.68 2.59 2.20 1.93 2.59 2.20 1.93 2.83 2.41 2.11 tHZ 1.99 1.69 1.49 2.61 2.22 1.95 2.61 2.22 1.95 3.01 2.56 2.25 tZLS 12.87 10.95 9.61 9.74 8.29 7.27 9.74 8.29 7.27 7.97 6.78 5.95 tZHS 13.08 11.12 9.77 9.60 8.16 7.17 9.60 8.16 7.17 7.74 6.59 5.78 Units ns ns ns ns ns ns ns ns ns ns ns ns
Revision 9
2- 51
ProASIC3 DC and Switching Characteristics Table 2-64 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 8.20 6.98 6.13 8.20 6.98 6.13 4.77 4.05 3.56 4.77 4.05 3.56
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.29 1.10 0.96 1.29 1.10 0.96 1.29 1.10 0.96 1.29 1.10 0.96
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.24 6.16 5.41 7.24 6.16 5.41 4.55 3.87 3.40 4.55 3.87 3.40
tZH 8.20 6.98 6.13 8.20 6.98 6.13 4.77 4.05 3.56 4.77 4.05 3.56
tLZ 2.03 1.73 1.52 2.03 1.73 1.52 2.38 2.03 1.78 2.38 2.03 1.78
tHZ 1.91 1.62 1.43 1.91 1.62 1.43 2.55 2.17 1.91 2.55 2.17 1.91
Table 2-65 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 11.00 9.35 8.21 11.00 9.35 8.21 7.50 6.38 5.60 7.50 6.38 5.60 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.29 1.10 0.96 1.29 1.10 0.96 1.29 1.10 0.96 1.29 1.10 0.96 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 10.37 8.83 7.75 10.37 8.83 7.75 7.36 6.26 5.49 7.36 6.26 5.49 tZH 11.00 9.35 8.21 11.00 9.35 8.21 7.50 6.38 5.60 7.50 6.38 5.60 tLZ 2.03 1.73 1.52 2.03 1.73 1.52 2.39 2.03 1.78 2.39 2.03 1.78 tHZ 1.83 1.56 1.37 1.83 1.56 1.37 2.46 2.10 1.84 2.46 2.10 1.84 Units ns ns ns ns ns ns ns ns ns ns ns ns
2- 52
R e visio n 9
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-66 Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes:
VIL Min. V 0.3 0.3 0.3 0.3 0.3 0.3 Max., V 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI Min. V
VIH Max. V 1.9 1.9 1.9 1.9 1.9 1.9
VOL Max. V 0.45 0.45 0.45 0.45 0.45 0.45
VOH Min. V VCCI 0.45 VCCI 0.45 VCCI 0.45 VCCI 0.45
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 11 22 44 51 74 74
IOSH
IIL1 IIH2
Max. mA3 A4 A4 9 17 35 45 91 91 10 10 10 10 10 10 10 10 10 10 10 10
0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI
VCCI 0.45 12 12 VCCI 0.45 16 16
Table 2-67 Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN <V CCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V 0.3 0.3 0.3 0.3 Max. V 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI Min. V
VIH Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.45 0.45 0.45 0.45
VOH Min. V VCCI 0.45 VCCI 0.45 VCCI 0.45 VCCI 0.45
IOL IOH
IOSL
IOSH Max. mA3 9 17 35 35
IIL1
IIH2
Max. mA mA mA3 2 4 6 8 2 4 6 8 11 22 44 44
A4 A4 10 10 10 10 10 10 10 10
0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI
Revision 9
2- 53
ProASIC3 DC and Switching Characteristics Table 2-68 Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA Notes:
VIL Min. V 0.3 0.3 Max. V 0.35 * VCCI 0.35 * VCCI
VIH Min. V 0.65 * VCCI 0.65 * VCCI Max. V 3.6 3.6
VOL Max. V 0.45 0.45
VOH Min. V VCCI 0.45 VCCI 0.45
IOL IOH mA mA 2 4 2 4
IOSL Max. mA3 9 17
IOSH Max. mA3 11 22
IIL1
IIH2
A4 A4 10 10 10 10
Figure 2-8
AC Loading
2- 54
R e visio n 9
Table 2-70 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 11.86 10.09 8.86 6.91 5.88 5.16 4.45 3.78 3.32 3.92 3.34 2.93 3.53 3.01 2.64 3.53 3.01 2.64
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 9.14 7.77 6.82 5.86 4.99 4.38 4.18 3.56 3.12 3.93 3.34 2.93 3.60 3.06 2.69 3.60 3.06 2.69
tZH 11.86 10.09 8.86 6.91 5.88 5.16 4.45 3.78 3.32 3.92 3.34 2.93 3.04 2.59 2.27 3.04 2.59 2.27
tLZ 2.77 2.36 2.07 3.22 2.74 2.41 3.53 3.00 2.64 3.60 3.06 2.69 3.70 3.15 2.76 3.70 3.15 2.76
tHZ 1.66 1.41 1.24 2.84 2.41 2.12 3.38 2.88 2.53 3.52 3.00 2.63 4.08 3.47 3.05 4.08 3.47 3.05
tZLS 11.37 9.67 8.49 8.10 6.89 6.05 6.42 5.46 4.79 6.16 5.24 4.60 5.84 4.96 4.36 5.84 4.96 4.36
tZHS 14.10 11.99 10.53 9.15 7.78 6.83 6.68 5.69 4.99 6.16 5.24 4.60 5.28 4.49 3.94 5.28 4.49 3.94
Revision 9
2- 55
ProASIC3 DC and Switching Characteristics Table 2-71 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 16 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 15.53 13.21 11.60 10.48 8.91 7.82 8.05 6.85 6.01 7.50 6.38 5.60 7.29 6.20 5.45 7.29 6.20 5.45 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 1.22 1.04 0.91 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 14.11 12.01 10.54 10.41 8.86 7.77 8.20 6.97 6.12 7.64 6.50 5.71 7.23 6.15 5.40 7.23 6.15 5.40 tZH 15.53 13.21 11.60 10.48 8.91 7.82 7.84 6.67 5.86 7.30 6.21 5.45 7.29 6.20 5.45 7.29 6.20 5.45 tLZ 2.78 2.36 2.07 3.23 2.75 2.41 3.54 3.01 2.64 3.61 3.07 2.69 3.71 3.15 2.77 3.71 3.15 2.77 tHZ 1.60 1.36 1.19 2.73 2.33 2.04 3.27 2.78 2.44 3.41 2.90 2.55 3.95 3.36 2.95 3.95 3.36 2.95 tZLS 16.35 13.91 12.21 12.65 10.76 9.44 10.43 8.88 7.79 9.88 8.40 7.38 9.47 8.06 7.07 9.47 8.06 7.07 tZHS 17.77 15.11 13.27 12.71 10.81 9.49 10.08 8.57 7.53 9.53 8.11 7.12 9.53 8.11 7.12 9.53 8.11 7.12 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 Flash Family FPGAs Table 2-72 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 11.33 9.64 8.46 6.48 5.51 4.84 4.06 3.45 3.03 4.06 3.45 3.03
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.20 1.02 0.90 1.20 1.02 0.90 1.20 1.02 0.90 1.20 1.02 0.90
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 8.72 7.42 6.51 5.48 4.66 4.09 3.84 3.27 2.87 3.84 3.27 2.87
tZH 11.33 9.64 8.46 6.48 5.51 4.84 4.06 3.45 3.03 4.06 3.45 3.03
tLZ 2.24 1.91 1.68 2.65 2.25 1.98 2.93 2.49 2.19 2.93 2.49 2.19
tHZ 1.52 1.29 1.14 2.60 2.21 1.94 3.10 2.64 2.32 3.10 2.64 2.32
tZLS 10.96 9.32 8.18 7.72 6.56 5.76 6.07 5.17 4.54 6.07 5.17 4.54
tZHS 13.57 11.54 10.13 8.72 7.42 6.51 6.30 5.36 4.70 6.30 5.36 4.70
Revision 9
2- 57
ProASIC3 DC and Switching Characteristics Table 2-73 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 14.80 12.59 11.05 9.90 8.42 7.39 7.44 6.33 5.55 7.44 6.33 5.55 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.20 1.02 0.90 1.20 1.02 0.90 1.20 1.02 0.90 1.20 1.02 0.90 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL tZH tLZ 2.25 1.91 1.68 2.65 2.26 1.98 2.94 2.50 2.19 2.94 2.50 2.19 tHZ 1.46 1.25 1.09 2.50 2.12 1.86 2.99 2.54 2.23 2.99 2.54 2.23 tZLS 15.73 13.38 11.75 11.97 10.18 8.94 9.81 8.35 7.33 9.81 8.35 7.33 tZHS 17.04 14.49 12.72 12.13 10.32 9.06 9.56 8.13 7.14 9.56 8.13 7.14 Units ns ns ns ns ns ns ns ns ns ns ns ns
13.49 14.80 11.48 10.08 9.73 8.28 7.27 7.58 6.44 5.66 7.58 6.44 5.66 12.59 11.05 9.90 8.42 7.39 7.32 6.23 5.47 7.32 6.23 5.47
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-74 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49
tDP 11.21 9.54 8.37 6.34 5.40 4.74
tDIN 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.20 1.02 0.90 1.20 1.02 0.90
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32
tZL 8.53 7.26 6.37 5.38 4.58 4.02
tZH 11.21 9.54 8.37 6.34 5.40 4.74
tLZ 1.99 1.69 1.49 2.41 2.05 1.80
tHZ 1.21 1.03 0.90 2.48 2.11 1.85
Units ns ns ns ns ns ns
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ProASIC3 Flash Family FPGAs Table 2-75 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 tDP 15.01 12.77 11.21 10.10 8.59 7.54 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.20 1.02 0.90 1.20 1.02 0.90 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 tZL 13.15 11.19 9.82 9.55 8.13 7.13 tZH 15.01 12.77 11.21 10.10 8.59 7.54 tLZ 1.99 1.70 1.49 2.41 2.05 1.80 tHZ 1.99 1.70 1.49 2.37 2.02 1.77 Units ns ns ns ns ns ns
Revision 9
2- 59
1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-76 Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes:
VIL Min. V 0.3 0.3 0.3 0.3 0.3 Max. V 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI 0.35 * VCCI
VIH Min. V 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI 0.65 * VCCI Max., V 1.575 1.575 1.575 1.575 1.575
VOL Max. V 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI
VOH Min. V 0.75 * VCCI 0.75 * VCCI 0.75 * VCCI 0.75 * VCCI
IOL IOH IOSL Max. mA mA mA3 2 4 6 8 2 4 6 8 16 33 39 55 55
IOSH IIL1 IIH2 Max. mA3 A4 A4 13 25 32 66 66 10 10 10 10 10 10 10 10 10 10
0.75 * VCCI 12 12
Table 2-77 Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS Drive Min. Strength V 2 mA 4 mA Notes:
VIL Max. V
VIH Min. V Max. V
VOL Max. V
VOH Min. V
IOL IOH mA mA 2 4 2 4
IOSL Max. mA3 16 33
IOSH Max. mA3 13 25
IIL1 IIH2 A4 A4 10 10 10 10
0.3 0.35 * VCCI 0.3 0.35 * VCCI
0.65 * VCCI 1.575 0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI
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ProASIC3 Flash Family FPGAs Table 2-78 Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS Drive Strength 2 mA Notes:
VIL Min. V 0.3 Max. V
VIH Min. V Max. V 3.6
VOL Max. V
VOH Min. V
IOL IOH
IOSL
IOSH
IIL1 IIH2
Max. Max. mA mA mA3 mA3 A4 A4 2 2 13 16 10 10
0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI
Figure 2-9
AC Loading
Revision 9
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Table 2-80 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49
tDP 8.36 7.11 6.24 5.31 4.52 3.97 4.67 3.97 3.49 4.08 3.47 3.05 4.08 3.47 3.05
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 6.82 5.80 5.10 4.85 4.13 3.62 4.55 3.87 3.40 4.15 3.53 3.10 4.15 3.53 3.10
tZH 8.36 7.11 6.24 5.31 4.52 3.97 4.67 3.97 3.49 3.58 3.04 2.67 3.58 3.04 2.67
tLZ 3.39 2.88 2.53 3.74 3.18 2.79 3.82 3.25 2.85 3.94 3.36 2.95 3.94 3.36 2.95
tHZ 2.77 2.35 2.06 3.40 2.89 2.54 3.56 3.03 2.66 4.20 3.58 3.14 4.20 3.58 3.14
tZLS 9.06 7.71 6.76 7.09 6.03 5.29 6.78 5.77 5.07 6.39 5.44 4.77 6.39 5.44 4.77
tZHS 10.60 9.02 7.91 7.55 6.42 5.64 6.90 5.87 5.16 5.81 4.95 4.34 5.81 4.95 4.34
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 Flash Family FPGAs Table 2-81 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 6 mA Std. 1 2 8 mA Std. 1 2 12 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 0.66 0.56 0.49 tDP 12.78 10.87 9.55 10.01 8.51 7.47 9.33 7.94 6.97 8.91 7.58 6.65 8.91 7.58 6.65 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07 1.44 1.22 1.07 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL tZH tLZ 3.40 2.89 2.54 3.75 3.19 2.80 3.83 3.26 2.86 3.95 3.36 2.95 3.95 3.36 2.95 tHZ 2.64 2.25 1.97 3.27 2.78 2.44 3.43 2.92 2.56 4.05 3.44 3.02 4.05 3.44 3.02 tZLS tZHS Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12.81 12.78 10.90 10.87 9.57 10.19 8.67 7.61 9.51 8.09 7.10 9.07 7.72 6.78 9.07 7.72 6.78 9.55 9.55 8.12 7.13 8.89 7.56 6.64 8.89 7.57 6.64 8.89 7.57 6.64
15.05 15.02 12.80 12.78 11.24 11.22
12.43 11.78 10.57 10.02 9.28 11.74 9.99 8.77 11.31 9.62 8.45 11.31 9.62 8.45 8.80 11.13 9.47 8.31 11.13 9.47 8.31 11.13 9.47 8.31
Revision 9
2- 63
ProASIC3 DC and Switching Characteristics Table 2-82 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49 0.66 0.56 0.49
tDP 7.83 6.66 5.85 4.84 4.12 3.61
tDIN 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.42 1.21 1.06 1.42 1.21 1.06
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32
tZL 6.42 5.46 4.79 4.49 3.82 3.35
tZH 7.83 6.66 5.85 4.84 4.12 3.61
tLZ 2.71 2.31 2.02 3.03 2.58 2.26
tHZ 2.55 2.17 1.90 3.13 2.66 2.34
tZLS 8.65 7.36 6.46 6.72 5.72 5.02
tZHS 10.07 8.56 7.52 7.08 6.02 5.28
Units ns ns ns ns ns ns
Table 2-83 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 4 mA Std. 1 2 tDOUT 0.66 0.56 0.49 0.66 0.56 0.49 tDP 12.08 10.27 9.02 9.28 7.89 6.93 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.42 1.21 1.06 1.42 1.21 1.06 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns
12.01 12.08 2.72 10.21 10.27 2.31 8.97 9.45 8.04 7.06 9.02 8.91 7.58 6.66 2.03 3.04 2.58 2.27
2.43 14.24 14.31 2.06 12.12 12.18 1.81 10.64 10.69 3.00 11.69 11.15 2.55 2.24 9.94 8.73 9.49 8.33
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-84 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 Notes:
tDOUT 0.66 0.56 0.49
tDP 7.65 6.50 5.71
tDIN 0.04 0.04 0.03
tPY 1.42 1.21 1.06
tEOUT 0.43 0.36 0.32
tZL 6.31 5.37 4.71
tZH 7.65 6.50 5.71
tLZ 2.45 2.08 1.83
tHZ 2.45 2.08 1.83
Units ns ns ns
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ProASIC3 Flash Family FPGAs Table 2-85 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA Speed Grade Std. 1 2 tDOUT 0.66 0.56 0.49 tDP 12.33 10.49 9.21 tDIN 0.04 0.04 0.03 tPY 1.42 1.21 1.06 tEOUT 0.43 0.36 0.32 tZL 11.79 10.03 8.81 tZH 12.33 10.49 9.21 tLZ 2.45 2.08 1.83 tHZ 2.32 1.98 1.73 Units ns ns ns
Revision 9
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3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-86 Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength Per PCI specification Notes:
1. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 2. Currents are measured at 85C junction temperature.
VIL Min. V Max. V Min. V
VIH Max. V
VOL Max,. V
VOH Min. V
IOL IOH mA mA
IOSL Max. mA1
IOSH Max. mA1
IIL
IIH
A2 A2 10 10
Per PCI curves
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-10.
R = 25 Test Point Datapath
R to VCCI for tDP (F) R to GND for tDP (R)
Figure 2-10 AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-87. Table 2-87 AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) CLOAD (pF) 10
Table 2-88 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade Std. 1 2 tDOUT 0.66 0.56 0.49 tDP 2.68 2.28 2.00 tDIN 0.04 0.04 0.03 tPY 0.86 0.73 0.65 tEOUT 0.43 0.36 0.32 tZL 2.73 2.32 2.04 tZH 1.95 1.66 1.46 tLZ 3.21 2.73 2.40 tHZ 3.58 3.05 2.68 tZLS 4.97 4.22 3.71 tZHS 4.19 3.56 3.13 Units ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-89 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade Std. 1 2 tDOUT 0.66 0.56 0.49 tDP 2.31 1.96 1.72 tDIN 0.04 0.04 0.03 tPY 0.85 0.72 0.64 tEOUT 0.43 0.36 0.32 tZL 2.35 2.00 1.76 tZH 1.70 1.45 1.27 tLZ 2.79 2.37 2.08 tHZ 3.22 2.74 2.41 tZLS 4.59 3.90 3.42 tZHS 3.94 3.35 2.94 Units ns ns ns
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Differential I/O Characteristics

Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Z0 = 50 140 N 165 Z0 = 50 100 N P FPGA + INBUF_LVDS
Figure 2-11 LVDS Circuit Diagram and Board-Level Implementation
Revision 9
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ProASIC3 DC and Switching Characteristics Table 2-90 LVDS Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH IOL IOH VI IIH IIL
3 3 4 4
Description Supply Voltage

1
Min. 2.375 0.9 1.25 0.65 0.65 0
Typ. 2.5 1.075 1.425 0.91 0.91
Max. 2.625 1.25 1.6 1.16 1.16 2.925 10 10
Units V V V mA mA V A A mV V V mV
Output Low Voltage Output High Voltage Output Lower Current Output High Current Input Voltage Input High Leakage Current Input Low Leakage Current Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Input Differential Voltage
2
VODIFF VOCM VICM VIDIFF Notes:

1. 2. 3. 4.
250 1.125 0.05 100
350 1.25 1.25 350
450 1.375 2.35
5% Differential input voltage = 350 mV. Currents are measured at 85C junction temperature. IOL / IOH defined by VODIFF /(Resistor Network).
Table 2-91 AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.075 Input High (V) 1.325 Measuring Point* (V) Cross point
Table 2-92 LVDS Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade Std. 1 2 tDOUT 0.66 0.56 0.49 tDP 1.83 1.56 1.37 tDIN 0.04 0.04 0.03 tPY 1.60 1.36 1.20 Units ns ns ns
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B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available in the LVDS section in Table 2-92. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 and RT = 70 , given Z0 = 50 (2") and Zstub = 50 (~1.5").
Receiver
EN
Transceiver
EN
Driver
Receiver
EN EN
Transceiver
EN
D
+
R
+
T
+
R
+
T
+
BIBUF_LVDS
RS RS Zstub Z0 RT Z
0
RS RS Zstub Z0 Z0 Zstub Zstub Z0 Z0
RS RS Zstub Zstub Z0 Z0
RS RS Zstub ... Z0 Z0
R S RS Z0 Z0 RT
Zstub
Figure 2-12 B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
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LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different.
Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Z0 = 50 187 W N 100 Z0 = 50 100 N P FPGA
INBUF_LVPECL
Figure 2-13 LVPECL Circuit Diagram and Board-Level Implementation Table 2-93 Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output Low Voltage Output High Voltage Input Low, Input High Voltages Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Max. Min. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Max. Min. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Max. Units V V V V V V V mV
Table 2-94 AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.64 Input High (V) 1.94 Measuring Point* (V) Cross point
Table 2-95 LVPECL Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade Std. 1 2 tDOUT 0.66 0.56 0.49 tDP 1.80 1.53 1.34 tDIN 0.04 0.04 0.03 tPY 1.40 1.19 1.05 Units ns ns ns
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I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
Preset
Pad Out
D DOUT Data_out
TRIBUF
Data
PRE D Q C DFN1E1P1 E B
Y Core Array
F G
PRE D Q DFN1E1P1 E
INBUF INBUF
Enable
EOUT H I
CLKBUF
CLK
A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E
CLKBUF
INBUF
INBUF
Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered
CLK
Figure 2-14 Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
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D_Enable
Enable
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ProASIC3 DC and Switching Characteristics Table 2-96 Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A
* See Figure 2-14 on page 2-71 for more information.
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Pad Out
DOUT Y D CC Q EE
DFN1E1C1
Data
Core Array
Data_out FF
TRIBUF
INBUF INBUF
DFN1E1C1
GG E BB CLR LL
CLKBUF
E CLR
EOUT
Enable
CLK
HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered
INBUF
CLR
DFN1E1C1
E CLR
INBUF
INBUF
CLKBUF
Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered
Figure 2-15 Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
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D_Enable
Enable
CLK
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ProASIC3 DC and Switching Characteristics Table 2-97 Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA
* See Figure 2-15 on page 2-73 for more information.
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Input Register
tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tIHE 50%
tIWPRE tISUE
tIRECPRE 50% tIWCLR tIRECCLR 50%
tIREMPRE 50% tIREMCLR 50%
Preset
Clear tIPRE2Q Out_1 50% tICLKQ 50%
50%
tICLR2Q
50%
Figure 2-16 Input Register Timing Diagram
Table 2-98 Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width High for the Input Data Register Clock Minimum Pulse Width Low for the Input Data Register 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.24 0.27 0.32 0.26 0.30 0.35 0.00 0.00 0.00 0.37 0.42 0.50 0.00 0.00 0.00 0.45 0.52 0.61 0.45 0.52 0.61 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
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Output Register
tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tOHE 50%
tOWPRE
tORECPRE 50%
tOREMPRE 50% tOREMCLR 50%
Preset
tOSUE
tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50%
tORECCLR
50%
Figure 2-17 Output Register Timing Diagram
Table 2-99 Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width High for the Output Data Register Clock Minimum Pulse Width Low for the Output Data Register 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.59 0.67 0.79 0.31 0.36 0.42 0.00 0.00 0.00 0.44 0.50 0.59 0.00 0.00 0.00 0.80 0.91 1.07 0.80 0.91 1.07 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
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Output Enable Register

tOECKMPWH tOECKMPWL
50% CLK
50% tOESUD tOEHD
50%
50%
50%
50%
50%
D_Enable
50%
0 50%
Enable
50%
tOEWPRE 50%
tOERECPRE 50%
tOEREMPRE 50%
Preset
tOESUEOEHE t
tOEWCLR 50% Clear tOEPRE2Q 50% EOUT tOECLKQ 50% tOECLR2Q 50%
tOERECCLR 50%
tOEREMCLR 50%
Figure 2-18 Output Enable Register Timing Diagram
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Table 2-100 Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width High for the Output Enable Register Clock Minimum Pulse Width Low for the Output Enable Register 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.59 0.67 0.79 0.31 0.36 0.42 0.00 0.00 0.00 0.44 0.50 0.58 0.00 0.00 0.00 0.67 0.76 0.89 0.67 0.76 0.89 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
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DDR Module Specifications

Input DDR Module
Input DDR
INBUF Data
A FF1
Out_QF (to core)
B CLK CLKBUF FF2
Out_QR (to core)
CLR INBUF
DDR_IN
Figure 2-19 Input DDR Timing Model Table 2-101 Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR input Data Hold Time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B
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CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9
Figure 2-20 Input DDR Timing Diagram
Table 2-102 Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (Fall) Data Setup for Input DDR (Rise) tDDRIHD Data Hold for Input DDR (Fall) Data Hold for Input DDR (Rise) tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal time for Input DDR Asynchronous Clear Recovery time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width High for Input DDR Clock Minimum Pulse Width Low for Input DDR Maximum Frequency for Input DDR 2 0.27 0.39 0.25 0.25 0.00 0.00 0.46 0.57 0.00 0.22 0.22 0.36 0.32 TBD 1 0.31 0.44 0.28 0.28 0.00 0.00 0.53 0.65 0.00 0.25 0.25 0.41 0.37 TBD Std. 0.37 0.52 0.33 0.33 0.00 0.00 0.62 0.76 0.00 0.30 0.30 0.48 0.43 TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
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Output DDR Module

Output DDR
Data_F (from core)
A X FF1 B Out X CLKBUF C X D X FF2 1 0 E X OUTBUF
CLK
Data_R (from core)
CLR INBUF
B X C X DDR_OUT
Figure 2-21 Output DDR Timing Model Table 2-103 Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Parameter Definition Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B
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CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5
Figure 2-22 Output DDR Timing Diagram
Table 2-104 Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width High for the Output DDR Clock Minimum Pulse Width Low for the Output DDR Maximum Frequency for the Output DDR 2 0.70 0.38 0.38 0.00 0.00 0.80 0.00 0.22 0.22 0.36 0.32 1 0.80 0.43 0.43 0.00 0.00 0.91 0.00 0.25 0.25 0.41 0.37 Std. 0.94 0.51 0.51 0.00 0.00 1.07 0.00 0.30 0.30 0.48 0.43 Units ns ns ns ns ns ns ns ns ns ns ns MHz
TBD TBD TBD
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VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide.
INV
A OR2 B A AND2 B Y Y
A NOR2 B Y
A NAND2 B A B C Y
A B XOR2 Y
XOR3
A A B C B C
MAJ3 Y
A 0 MUX2 B 1 Y
NAND3
S
Figure 2-23 Sample of Combinatorial Cells
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tPD
A NAND2 or Any Combinatorial Logic Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC
50% A, B, C
50% GND VCC
50% OUT GND VCC OUT 50% tPD (RF)

Figure 2-24 Timing Model and Waveforms
50%
tPD (RR)
tPD (FF) tPD (FR) GND 50%
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Table 2-105 Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=AB Y = !(A B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A, B, C) Y=ABC Y = A !S + B S Y=ABC Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD 2 0.40 0.47 0.47 0.49 0.49 0.74 0.70 0.87 0.51 0.56 1 0.46 0.54 0.54 0.55 0.55 0.84 0.79 1.00 0.58 0.64 Std. 0.54 0.63 0.63 0.65 0.65 0.99 0.93 1.17 0.68 0.75 Units ns ns ns ns ns ns ns ns ns ns
VersaTile Specifications as a Sequential Module

The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide.
Data
D DFN1
Out
Data D En CLK Q
Out
DFN1E1
CLK
PRE
Data
Q DFN1C1
Out
Data En CLK
Out
DFI1E1P1
CLK CLR
Figure 2-25 Sample of Sequential Cells
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tCKMPWH tCKMPWL 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50%
CLK
50%
EN 50% tHE PRE tSUE 50% tWPRE tRECPRE 50% tREMPRE 50% tREMCLR 50%
tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50%
tRECCLR 50%
tCLR2Q 50%
Figure 2-26 Timing Model and Waveforms
Table 2-106 Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Description Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width High for the Core Register Clock Minimum Pulse Width Low for the Core Register 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.55 0.63 0.74 0.43 0.49 0.57 0.00 0.00 0.00 0.45 0.52 0.61 0.00 0.00 0.00 0.40 0.45 0.53 0.40 0.45 0.53 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.32 0.37 0.43 0.36 0.41 0.48
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Global Resource Characteristics

A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It is used to drive all D-flip-flops in the device.
Central Global Rib

CCC
VersaTile Rows
Global Spine
Figure 2-27 Example of Global Tree Use in an A3P250 Device for Clock Routing
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Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standarddependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-92. Table 2-108 to Table 2-114 on page 2-91 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Table 2-107 A3P015 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V 2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
1
2
Std.
2
Min.
Max.
Min.
Max.
Min.
Max.2 Units 1.08 1.13 ns ns ns ns
Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
0.66 0.67
0.81 0.84
0.75 0.76
0.92 0.96
0.88 0.89
0.18
0.21
0.25
ns MHz
Table 2-108 A3P030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V 2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Std.
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units 0.67 0.68 0.81 0.85 0.76 0.77 0.92 0.97 0.89 0.91 1.09 1.14 ns ns ns ns 0.18 0.21 0.24 ns MHz
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ProASIC3 Flash Family FPGAs Table 2-109 A3P060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V 2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1
2
Std.
2
Min.
Max.
Min.
Max.
Min.1 Max.2 Units 0.95 0.94 1.24 1.28 ns ns ns ns
0.71 0.70
0.93 0.96
0.81 0.80
1.05 1.09
0.26
0.29
0.34
ns MHz
Std.
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ProASIC3 DC and Switching Characteristics Table 2-111 A3P250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V 2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1
2
Std.
2
Min.
Max.
Min.
Max.
0.80 0.78
1.01 1.04
0.91 0.89
1.15 1.18
0.26
0.29
0.34
ns MHz
Std.
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R e visio n 9
ProASIC3 Flash Family FPGAs Table 2-113 A3P600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V 2 Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1
2
Std.
2
Min.
Max.
Min.
Max.
0.87 0.86
1.09 1.11
0.99 0.98
1.24 1.27
0.26
0.29
0.34
ns MHz
Std.
Revision 9
2- 91
Clock Conditioning Circuits

CCC Electrical Specifications
Table 2-115 ProASIC3 CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Serial Clock (SCLK) for Dynamic PLL1 Delay Increments in Programmable Delay Blocks
2, 3
Minimum 1.5 0.75
Typical
Maximum 350 350 125
Units MHz MHz MHz ps
200 32 1.5 Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.70% 1.20% 2.00% 5.60% 300 300 300 6.0 1.6 1.6 1.6 0.8 48.5 51.5 5.56 5.56 2.2 0.6 0.225
Number of Programmable Values in Each Programmable Delay Block Input Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT
ns
0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz 250 MHz to 350 MHz Acquisition Time (A3P250 and A3P1000 only) (all other dies) Tracking Jitter 5 (A3P250 and A3P1000 only) (all other dies) Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay2, 3 Notes:
2, 3 2, 3
0.50% 1.00% 1.75% 2.50% LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1 LockControl = 0 LockControl = 1
s s s ms ns ns ns ns % ns ns ns
1. Maximum value obtained for a 2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings. 3. TJ = 25C, VCC = 1.5 V 4. The A3P030 device does not contain a PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
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Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max Tperiod_min. Figure 2-28 Peak-to-Peak Jitter Definition
Revision 9
2- 93
Embedded SRAM and FIFO Characteristics

SRAM
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0
DINA0
RW1 RW0
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
REN RCLK WADDR8 WADDR7
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0
WEN WCLK RESET
Figure 2-29 RAM Models
2- 94
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Timing Waveforms
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1
Figure 2-30 RAM Read for Pass-Through Output
tCKL
tAH A1 A2 tBKH tENH
D1
D2
tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2
Figure 2-31 RAM Read for Pipelined Output
AS
tCKL
tAH A0 A1 A2 tBKH tENH
D1
Revision 9
2- 95
tCYC tCKH CLK tAS ADD A0 tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH tAH A1 A2 tCKL
DO
Dn
D2
Figure 2-32 RAM Write, Output Retained (WMODE = 0)
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH tAH A1 A2 tCKL
Dn
DI0
DI1
Dn
DI0
DI1
Figure 2-33 RAM Write, Output as Write Data (WMODE = 1)
2- 96
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CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D1 tCCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) A0 D0 tCKQ1 Dn D0 tCKQ2 Dn D0 A1 A3
D2
D3
tAS
tAH A0 A4 D4
Figure 2-34 Write Access after Write onto Same Address
Revision 9
2- 97
CLK1 tAS tAH ADD1 DI1 CLK2 WEN_B1 WEN_B2 tAS tAH ADD2 DO2 (pass-through) DO2 (pipelined) A0 tCKQ1 Dn Dn D0 tCKQ2 D0 D1 A1 A4 A0 tDS tDH D0 tWRO A2 D2 A3 D3
Figure 2-35 Read Access after Write onto Same Address
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CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0
DI2 WEN_B2
Figure 2-36 Write Access after Read onto Same Address
tCYC tCKH CLK tCKL
RESET_B tRSTBQ DO Dm Dn
Figure 2-37 RAM Reset
Revision 9
2- 99
Table 2-116 RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (flow-through, WMODE = 1) tCKQ2 tC2CWWL tC2CWWH tC2CRWH tC2CWRH tRSTBQ Clock High to new data valid on DO (pipelined) Description 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
0.25 0.28 0.33 0.00 0.00 0.00 0.14 0.16 0.19 0.10 0.11 0.13 0.23 0.27 0.31 0.02 0.02 0.02 0.18 0.21 0.25 0.00 0.00 0.00 2.36 2.68 3.15 1.79 2.03 2.39 0.89 1.02 1.20
Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25 addressApplicable to Closing Edge Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23 addressApplicable to Rising Edge Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34 addressApplicable to Opening Edge Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37 address Applicable to Opening Edge RESET_B Low to data out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 0.92 1.05 1.23 0.29 0.33 0.38 1.50 1.71 2.01 0.21 0.24 0.29 3.23 3.68 4.32 310 272 231
tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX
RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency
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ProASIC3 Flash Family FPGAs Table 2-117 RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tC2CRWH tC2CWRH tRSTBQ Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (pipelined) Description 2 1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
0.25 0.28 0.33 0.00 0.00 0.00 0.13 0.15 0.17 0.10 0.11 0.13 0.18 0.21 0.25 0.00 0.00 0.00 2.16 2.46 2.89 0.90 1.02 1.20
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38 addressApplicable to Opening Edge Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44 address Applicable to Opening Edge RESET_B Low to data out Low on DO (flow-through) RESET_B Low to data out Low on DO (pipelined) 0.92 1.05 1.23 0.92 1.05 1.23 0.29 0.33 0.38 1.50 1.71 2.01 0.21 0.24 0.29 3.23 3.68 4.32 310 272 231
tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX
RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency
Revision 9
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FIFO
FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
AEVAL0 AFVAL11 AFVAL10
AFVAL0 REN RBLK RCLK WD17 WD16
WD0 WEN WBLK WCLK RPIPE
RESET
Figure 2-38 FIFO Model
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Timing Waveforms
RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter)
Figure 2-39 FIFO Reset
tRSTCK
MATCH (A0)
tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-40 FIFO EMPTY Flag and AEMPTY Flag Assertion
Revision 9
2- 103
tCYC WCLK tWCKFF FULL tCKAF AFULL
WA/RA NO MATCH (Address Counter)
NO MATCH
Dist = AFF_TH
MATCH (FULL)
Figure 2-41 FIFO FULL Flag and AFULL Flag Assertion
WCLK
WA/RA MATCH (Address Counter) (EMPTY)
NO MATCH
NO MATCH 2nd Rising Edge After 1st Write tRCKEF
NO MATCH
NO MATCH
Dist = AEF_TH + 1
RCLK
1st Rising Edge After 1st Write
EMPTY tCKAF AEMPTY
Figure 2-42 FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK WA/RA (Address Counter)

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH Dist = AFF_TH 1
WCLK
1st Rising Edge After 1st Read
1st Rising Edge After 2nd Read tWCKF
FULL tCKAF AFULL
Figure 2-43 FIFO FULL Flag and AFULL Flag Deassertion
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Table 2-118 FIFO (for all dies except A3P250) Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO 2 1.34 0.00 0.19 0.00 0.18 0.00 2.17 0.94 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 1.52 0.00 0.22 0.00 0.21 0.00 2.47 1.07 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 1.79 0.00 0.26 0.00 0.25 0.00 2.90 1.26 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Revision 9
2- 105
ProASIC3 DC and Switching Characteristics Table 2-119 FIFO (for A3P250 only, aspect-ratio-dependent) Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO 2 3.26 0.00 0.19 0.00 0.18 0.00 2.17 0.94 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 3.71 0.00 0.22 0.00 0.21 0.00 2.47 1.07 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 4.36 0.00 0.26 0.00 0.25 0.00 2.90 1.26 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
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ProASIC3 Flash Family FPGAs Table 2-120 A3P250 FIFO 5128 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO 2 3.75 0.00 0.19 0.00 0.18 0.00 2.17 0.94 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 4.27 0.00 0.22 0.00 0.21 0.00 2.47 1.07 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 5.02 0.00 0.26 0.00 0.25 0.00 2.90 1.26 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Revision 9
2- 107
ProASIC3 DC and Switching Characteristics Table 2-121 A3P250 FIFO 1k4 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO 2 4.05 0.00 0.19 0.00 0.18 0.00 2.36 0.89 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 4.61 0.00 0.22 0.00 0.21 0.00 2.68 1.02 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 5.42 0.00 0.26 0.00 0.25 0.00 3.15 1.20 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
2- 10 8
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ProASIC3 Flash Family FPGAs Table 2-122 A3P250 FIFO 2k2 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO 2 4.39 0.00 0.19 0.00 0.18 0.00 2.36 0.89 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 5.00 0.00 0.22 0.00 0.21 0.00 2.68 1.02 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 5.88 0.00 0.26 0.00 0.25 0.00 3.15 1.20 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Revision 9
2- 109
ProASIC3 DC and Switching Characteristics Table 2-123 A3P250 FIFO 4k1 Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (pass-through) RESET_B Low to Data Out Low on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency 2 4.86 0.00 0.19 0.00 0.18 0.00 2.36 0.89 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 1 5.53 0.00 0.22 0.00 0.21 0.00 2.68 1.02 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 6.50 0.00 0.26 0.00 0.25 0.00 3.15 1.20 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
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Embedded FlashROM Characteristics

tSU CLK tHOLD tSU tHOLD tSU tHOLD
Address
A0 tCKQ2
A1 tCKQ2 D0 tCKQ2 D1
Data
D0
Figure 2-44 Timing Diagram
Table 2-124 Embedded FlashROM Access Time Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency 2 0.53 0.00 21.42 15 1 0.61 0.00 24.40 15 Std. 0.71 0.00 28.68 15 Units ns ns ns MHz
Revision 9
2- 111
JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details. Timing Characteristics Table 2-125 JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse 2 0.50 1.00 0.50 1.00 6.00 20.00 25.00 0.00 0.20 TBD 1 0.57 1.13 0.57 1.13 6.80 22.67 22.00 0.00 0.23 TBD Std. 0.67 1.33 0.67 1.33 8.00 26.67 19.00 0.00 0.27 TBD Units ns ns ns ns ns ns MHz ns ns ns
Actel Safety Critical, Life Support, and High-Reliability Applications Policy

The Actel products described in this advance status datasheet may not have completed Actels qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actels Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actels products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
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3 Package Pin Assignments

48-Pin QFN
Pin 1 48 1
Notes:
1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
Revision 9
3 -1
48-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P030 Function IO82RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO62RSB1 IO61RSB1 IO60RSB1 IO57RSB1 IO55RSB1 IO53RSB1 VCC VCCIB1 IO46RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO TRST VJTAG IO38RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO25RSB0
48-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 A3P030 Function IO24RSB0 IO22RSB0 IO20RSB0 IO18RSB0 IO16RSB0 IO14RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
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R e vi s i o n 9
68-Pin QFN
Pin A1 Mark
68 1
Notes:
Note
Revision 9
3 -3
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P015 Function IO82RSB1 IO80RSB1 IO78RSB1 IO76RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 VCC GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO60RSB1 IO58RSB1 IO56RSB1 IO54RSB1 IO52RSB1 IO51RSB1 VCC GND VCCIB1 IO50RSB1 IO48RSB1 IO46RSB1 IO44RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3P015 Function TRST VJTAG IO40RSB0 IO37RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO24RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
3-4
R e vi s i o n 9
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P030 Function IO82RSB1 IO80RSB1 IO78RSB1 IO76RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 VCC GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO60RSB1 IO58RSB1 IO56RSB1 IO54RSB1 IO52RSB1 IO51RSB1 VCC GND VCCIB1 IO50RSB1 IO48RSB1 IO46RSB1 IO44RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3P030 Function TRST VJTAG IO40RSB0 IO37RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO24RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
Revision 9
3 -5
132-Pin QFN
A37 B34 C31 A48 B44 C40
Pin A1Mark
D4 A36 B33 C30 D1 A1 C1 B1
C21 B23 A25 D3
C10 B11 A12 D2 Optional Corner Pad (4x) C20 B22 A24 C11 B12 A13
Notes:
Note
3-6
R e vi s i o n 9
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A3P030 Function IO01RSB1 IO81RSB1 NC IO80RSB1 GEC0/IO77RSB1 NC GEB0/IO75RSB1 IO73RSB1 NC VCC IO71RSB1 IO68RSB1 IO63RSB1 IO60RSB1 NC IO59RSB1 IO57RSB1 VCC IO54RSB1 IO52RSB1 IO49RSB1 IO48RSB1 IO47RSB1 TDI TRST IO44RSB0 NC IO43RSB0 IO42RSB0 IO40RSB0 IO39RSB0 GDC0/IO36RSB0 NC VCC IO34RSB0 IO31RSB0
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 A3P030 Function IO26RSB0 IO23RSB0 NC IO22RSB0 IO20RSB0 IO18RSB0 VCC IO15RSB0 IO12RSB0 IO10RSB0 IO09RSB0 IO06RSB0 IO02RSB1 IO82RSB1 GND IO79RSB1 NC GND IO74RSB1 NC GND IO70RSB1 IO67RSB1 IO64RSB1 IO61RSB1 GND IO58RSB1 IO56RSB1 GND IO53RSB1 IO50RSB1 GND IO46RSB1 TMS TDO IO45RSB0
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 A3P030 Function GND NC IO41RSB0 GND GDA0/IO37RSB0 NC GND IO33RSB0 IO30RSB0 IO27RSB0 IO24RSB0 GND IO21RSB0 IO19RSB0 GND IO16RSB0 IO13RSB0 GND IO08RSB0 IO05RSB0 IO03RSB1 IO00RSB1 NC IO78RSB1 GEA0/IO76RSB1 NC NC VCCIB1 IO69RSB1 IO66RSB1 IO65RSB1 IO62RSB1 NC NC IO55RSB1 VCCIB1
Revision 9
3 -7
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 A3P030 Function IO51RSB1 NC TCK NC VPUMP VJTAG NC NC NC GDB0/IO38RSB0 NC VCCIB0 IO32RSB0 IO29RSB0 IO28RSB0 IO25RSB0 NC NC VCCIB0 IO17RSB0 IO14RSB0 IO11RSB0 IO07RSB0 IO04RSB0 GND GND GND GND
3-8
R e vi s i o n 9
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A3P060 Function GAB2/IO00RSB1 IO93RSB1 VCCIB1 GFC1/IO89RSB1 GFB0/IO86RSB1 VCCPLF GFA1/IO84RSB1 GFC2/IO81RSB1 IO78RSB1 VCC GEB1/IO75RSB1 GEA0/IO72RSB1 GEC2/IO69RSB1 IO65RSB1 VCC IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1 IO58RSB1 GDB2/IO55RSB1 NC GDA2/IO54RSB1 TDI TRST GDC1/IO48RSB0 VCC IO47RSB0 GCC2/IO46RSB0 GCA2/IO44RSB0 GCA0/IO43RSB0 GCB1/IO40RSB0 IO36RSB0 VCC IO31RSB0 GBA2/IO28RSB0
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 A3P060 Function GBB1/IO25RSB0 GBC0/IO22RSB0 VCCIB0 IO21RSB0 IO18RSB0 IO15RSB0 IO14RSB0 IO11RSB0 GAB1/IO08RSB0 NC GAB0/IO07RSB0 IO04RSB0 IO01RSB1 GAC2/IO94RSB1 GND GFC0/IO88RSB1 VCOMPLF GND GFB2/IO82RSB1 IO79RSB1 GND GEB0/IO74RSB1 VMV1 GEB2/IO70RSB1 IO67RSB1 GND NC NC GND IO59RSB1 GDC2/IO56RSB1 GND GNDQ TMS TDO GDC0/IO49RSB0
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 A3P060 Function GND NC GCB2/IO45RSB0 GND GCB0/IO41RSB0 GCC1/IO38RSB0 GND GBB2/IO30RSB0 VMV0 GBA0/IO26RSB0 GBC1/IO23RSB0 GND IO20RSB0 IO17RSB0 GND IO12RSB0 GAC0/IO09RSB0 GND GAA1/IO06RSB0 GNDQ GAA2/IO02RSB1 IO95RSB1 VCC GFB1/IO87RSB1 GFA0/IO85RSB1 GFA2/IO83RSB1 IO80RSB1 VCCIB1 GEA1/IO73RSB1 GNDQ GEA2/IO71RSB1 IO68RSB1 VCCIB1 NC NC IO60RSB1
Revision 9
3 -9
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 A3P060 Function IO57RSB1 NC TCK VMV1 VPUMP VJTAG VCCIB0 NC NC GCA1/IO42RSB0 GCC0/IO39RSB0 VCCIB0 IO29RSB0 GNDQ GBA1/IO27RSB0 GBB0/IO24RSB0 VCC IO19RSB0 IO16RSB0 IO13RSB0 GAC1/IO10RSB0 NC GAA0/IO05RSB0 VMV0 GND GND GND GND
3- 10
R e visio n 9
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A3P125 Function GAB2/IO69RSB1 IO130RSB1 VCCIB1 GFC1/IO126RSB1 GFB0/IO123RSB1 VCCPLF GFA1/IO121RSB1 GFC2/IO118RSB1 IO115RSB1 VCC GEB1/IO110RSB1 GEA0/IO107RSB1 GEC2/IO104RSB1 IO100RSB1 VCC IO99RSB1 IO96RSB1 IO94RSB1 IO91RSB1 IO85RSB1 IO79RSB1 VCC GDB2/IO71RSB1 TDI TRST GDC1/IO61RSB0 VCC IO60RSB0 GCC2/IO59RSB0 GCA2/IO57RSB0 GCA0/IO56RSB0 GCB1/IO53RSB0 IO49RSB0 VCC IO44RSB0 GBA2/IO41RSB0
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 A3P125 Function GBB1/IO38RSB0 GBC0/IO35RSB0 VCCIB0 IO28RSB0 IO22RSB0 IO18RSB0 IO14RSB0 IO11RSB0 IO07RSB0 VCC GAC1/IO05RSB0 GAB0/IO02RSB0 IO68RSB1 GAC2/IO131RSB1 GND GFC0/IO125RSB1 VCOMPLF GND GFB2/IO119RSB1 IO116RSB1 GND GEB0/IO109RSB1 VMV1 GEB2/IO105RSB1 IO101RSB1 GND IO98RSB1 IO95RSB1 GND IO87RSB1 IO81RSB1 GND GNDQ TMS TDO GDC0/IO62RSB0
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 A3P125 Function GND NC GCB2/IO58RSB0 GND GCB0/IO54RSB0 GCC1/IO51RSB0 GND GBB2/IO43RSB0 VMV0 GBA0/IO39RSB0 GBC1/IO36RSB0 GND IO26RSB0 IO21RSB0 GND IO13RSB0 IO08RSB0 GND GAC0/IO04RSB0 GNDQ GAA2/IO67RSB1 IO132RSB1 VCC GFB1/IO124RSB1 GFA0/IO122RSB1 GFA2/IO120RSB1 IO117RSB1 VCCIB1 GEA1/IO108RSB1 GNDQ GEA2/IO106RSB1 IO103RSB1 VCCIB1 IO97RSB1 IO93RSB1 IO89RSB1
Revision 9
3- 11
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 A3P125 Function IO83RSB1 VCCIB1 TCK VMV1 VPUMP VJTAG VCCIB0 NC NC GCA1/IO55RSB0 GCC0/IO52RSB0 VCCIB0 IO42RSB0 GNDQ GBA1/IO40RSB0 GBB0/IO37RSB0 VCC IO24RSB0 IO19RSB0 IO16RSB0 IO10RSB0 VCCIB0 GAB1/IO03RSB0 VMV0 GND GND GND GND
3- 12
R e visio n 9
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A3P250 Function GAB2/IO117UPB3 IO117VPB3 VCCIB3 GFC1/IO110PDB3 GFB0/IO109NPB3 VCCPLF GFA1/IO108PPB3 GFC2/IO105PPB3 IO103NDB3 VCC GEA1/IO98PPB3 GEA0/IO98NPB3 GEC2/IO95RSB2 IO91RSB2 VCC IO90RSB2 IO87RSB2 IO85RSB2 IO82RSB2 IO76RSB2 IO70RSB2 VCC GDB2/IO62RSB2 TDI TRST GDC1/IO58UDB1 VCC IO54NDB1 IO52NDB1 GCA2/IO51PPB1 GCA0/IO50NPB1 GCB1/IO49PDB1 IO47NSB1 VCC IO41NPB1 GBA2/IO41PPB1
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 A3P250 Function GBB1/IO38RSB0 GBC0/IO35RSB0 VCCIB0 IO28RSB0 IO22RSB0 IO18RSB0 IO14RSB0 IO11RSB0 IO07RSB0 VCC GAC1/IO05RSB0 GAB0/IO02RSB0 IO118VDB3 GAC2/IO116UDB3 GND GFC0/IO110NDB3 VCOMPLF GND GFB2/IO106PSB3 IO103PDB3 GND GEB0/IO99NDB3 VMV3 GEB2/IO96RSB2 IO92RSB2 GND IO89RSB2 IO86RSB2 GND IO78RSB2 IO72RSB2 GND GNDQ TMS TDO GDC0/IO58VDB1
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 A3P250 Function GND IO54PDB1 GCB2/IO52PDB1 GND GCB0/IO49NDB1 GCC1/IO48PDB1 GND GBB2/IO42PDB1 VMV1 GBA0/IO39RSB0 GBC1/IO36RSB0 GND IO26RSB0 IO21RSB0 GND IO13RSB0 IO08RSB0 GND GAC0/IO04RSB0 GNDQ GAA2/IO118UDB3 IO116VDB3 VCC GFB1/IO109PPB3 GFA0/IO108NPB3 GFA2/IO107PSB3 IO105NPB3 VCCIB3 GEB1/IO99PDB3 GNDQ GEA2/IO97RSB2 IO94RSB2 VCCIB2 IO88RSB2 IO84RSB2 IO80RSB2
Revision 9
3- 13
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 A3P250 Function IO74RSB2 VCCIB2 TCK VMV2 VPUMP VJTAG VCCIB1 IO53NSB1 IO51NPB1 GCA1/IO50PPB1 GCC0/IO48NDB1 VCCIB1 IO42NDB1 GNDQ GBA1/IO40RSB0 GBB0/IO37RSB0 VCC IO24RSB0 IO19RSB0 IO16RSB0 IO10RSB0 VCCIB0 GAB1/IO03RSB0 VMV0 GND GND GND GND
3- 14
R e visio n 9
121-Pin CSP
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L
Notes:
Note
Revision 9
3- 15
121-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 A3P060 Function GNDQ IO01RSB0 GAA1/IO03RSB0 GAC1/IO07RSB0 IO15RSB0 IO13RSB0 IO17RSB0 GBB1/IO22RSB0 GBA1/IO24RSB0 GNDQ VMV0 GAA2/IO95RSB1 IO00RSB0 GAA0/IO02RSB0 GAC0/IO06RSB0 IO08RSB0 IO12RSB0 IO16RSB0 GBC1/IO20RSB0 GBB0/IO21RSB0 GBB2/IO27RSB0 GBA2/IO25RSB0 IO89RSB1 GAC2/IO91RSB1 GAB1/IO05RSB0 GAB0/IO04RSB0 IO09RSB0 IO14RSB0 GBA0/IO23RSB0 GBC0/IO19RSB0 IO26RSB0 IO28RSB0 GBC2/IO29RSB0 IO88RSB1 IO90RSB1 GAB2/IO93RSB1
121-Pin CSP Pin Number D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 A3P060 Function IO10RSB0 IO11RSB0 IO18RSB0 IO32RSB0 IO31RSB0 GCA2/IO41RSB0 IO30RSB0 IO33RSB0 IO87RSB1 GFC0/IO85RSB1 IO92RSB1 IO94RSB1 VCC VCCIB0 GND GCC0/IO36RSB0 IO34RSB0 GCB1/IO37RSB0 GCC1/IO35RSB0 VCOMPLF GFB0/IO83RSB1 GFA0/IO82RSB1 GFC1/IO86RSB1 VCCIB1 VCC VCCIB0 GCB2/IO42RSB0 GCC2/IO43RSB0 GCB0/IO38RSB0 GCA1/IO39RSB0 VCCPLF GFB2/IO79RSB1 GFA1/IO81RSB1 GFB1/IO84RSB1 GND VCCIB1
121-Pin CSP Pin Number G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 A3P060 Function VCC GDC0/IO46RSB0 GDA1/IO49RSB0 GDB0/IO48RSB0 GCA0/IO40RSB0 IO75RSB1 IO76RSB1 GFC2/IO78RSB1 GFA2/IO80RSB1 IO77RSB1 GEC2/IO66RSB1 IO54RSB1 GDC2/IO53RSB1 VJTAG TRST IO44RSB0 GEC1/IO74RSB1 GEC0/IO73RSB1 GEB1/IO72RSB1 GEA0/IO69RSB1 GEB2/IO67RSB1 IO62RSB1 GDA2/IO51RSB1 GDB2/IO52RSB1 TDI TDO GDC1/IO45RSB0 GEB0/IO71RSB1 GEA1/IO70RSB1 GEA2/IO68RSB1 IO64RSB1 IO60RSB1 IO59RSB1 IO56RSB1 TCK TMS
3- 16
R e visio n 9
121-Pin CSP Pin Number K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 A3P060 Function VPUMP GDB1/IO47RSB0 VMV1 GNDQ IO65RSB1 IO63RSB1 IO61RSB1 IO58RSB1 IO57RSB1 IO55RSB1 GNDQ GDA0/IO50RSB0 VMV1
Revision 9
3- 17
100-Pin VQFP
100
Note: This is the top view of the package.
Note
3- 18
R e visio n 9
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P030 Function GND IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 IO78RSB1 IO77RSB1 IO76RSB1 GND IO75RSB1 IO74RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 IO70RSB1 IO69RSB1 VCC VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 IO56RSB1 IO55RSB1 IO54RSB1 IO53RSB1 IO52RSB1 IO51RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P030 Function VCC GND VCCIB1 IO49RSB1 IO47RSB1 IO46RSB1 IO45RSB1 IO44RSB1 IO43RSB1 IO42RSB1 TCK TDI TMS NC GND VPUMP NC TDO TRST VJTAG IO41RSB0 IO40RSB0 IO39RSB0 IO38RSB0 IO37RSB0 IO36RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO30RSB0 IO29RSB0 IO28RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P030 Function IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 IO23RSB0 IO22RSB0 IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO07RSB0 IO06RSB0 IO05RSB0 IO04RSB0 IO03RSB0 IO02RSB0 IO01RSB0 IO00RSB0
Revision 9
3- 19
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P060 Function GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P060 Function VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC IO31RSB0 GBC2/IO29RSB0 GBB2/IO27RSB0 IO26RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P060 Function GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0
3- 20
R e visio n 9
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 GND GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 VCC VCCIB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO102RSB1 IO100RSB1 IO99RSB1 IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1 IO93RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P125 Function VCC GND VCCIB1 IO87RSB1 IO84RSB1 IO81RSB1 IO75RSB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO65RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0 GBB2/IO43RSB0 IO42RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P125 Function GBA2/IO41RSB0 VMV0 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO32RSB0 IO28RSB0 IO25RSB0 IO22RSB0 IO19RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 IO09RSB0 IO07RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0
Revision 9
3- 21
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO112PSB3 GND GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GFA2/IO107PSB3 VCC VCCIB3 GFC2/IO105PSB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GEA2/IO97RSB2 GEB2/IO96RSB2 GEC2/IO95RSB2 IO93RSB2 IO92RSB2 IO91RSB2 IO90RSB2 IO88RSB2 IO86RSB2 IO85RSB2 IO84RSB2
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P250 Function VCC GND VCCIB2 IO77RSB2 IO74RSB2 IO71RSB2 GDC2/IO63RSB2 GDB2/IO62RSB2 GDA2/IO61RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO60USB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO52NDB1 GCB2/IO52PDB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 VCCIB1 GND VCC IO43NDB1 GBC2/IO43PDB1 GBB2/IO42PSB1 IO41NDB1
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3P250 Function GBA2/IO41PDB1 VMV1 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO29RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
3- 22
R e visio n 9
144-Pin TQFP
144 1
144-Pin TQFP
Note
Revision 9
3- 23
144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P060 Function GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 IO91RSB1 VCC GND VCCIB1 IO90RSB1 GFC1/IO89RSB1 GFC0/IO88RSB1 GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 GFB2/IO82RSB1 GFC2/IO81RSB1 IO80RSB1 IO79RSB1 IO78RSB1 GND VCCIB1 GEC1/IO77RSB1 GEC0/IO76RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ
144-Pin TQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P060 Function NC GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 VCC GND VCCIB1 NC IO64RSB1 NC IO63RSB1 NC IO62RSB1 NC IO61RSB1 NC NC IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 NC GND NC GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 GNDQ TCK TDI TMS VMV1
144-Pin TQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P060 Function VPUMP NC TDO TRST VJTAG GDA0/IO50RSB0 GDB0/IO48RSB0 GDB1/IO47RSB0 VCCIB0 GND IO44RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA2/IO41RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCB0/IO38RSB0 GCB1/IO37RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 IO34RSB0 IO33RSB0 NC NC NC VCCIB0 GND VCC IO30RSB0 GBC2/IO29RSB0 IO28RSB0 GBB2/IO27RSB0 IO26RSB0 GBA2/IO25RSB0 VMV0 GNDQ
3- 24
R e visio n 9
144-Pin TQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P060 Function NC NC GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 VCCIB0 GND VCC IO18RSB0 IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 NC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 NC GND NC GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0 GNDQ VMV0
Revision 9
3- 25
144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P125 Function GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 IO128RSB1 VCC GND VCCIB1 IO127RSB1 GFC1/IO126RSB1 GFC0/IO125RSB1 GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 GFB2/IO119RSB1 GFC2/IO118RSB1 IO117RSB1 IO116RSB1 IO115RSB1 GND VCCIB1 GEC1/IO112RSB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ
144-Pin TQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P125 Function NC GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO103RSB1 IO102RSB1 IO101RSB1 IO100RSB1 VCC GND VCCIB1 IO99RSB1 IO97RSB1 IO95RSB1 IO93RSB1 IO92RSB1 IO90RSB1 IO88RSB1 IO86RSB1 IO84RSB1 IO83RSB1 IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 VCC GND VCCIB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 GNDQ TCK TDI TMS VMV1
144-Pin TQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P125 Function VPUMP NC TDO TRST VJTAG GDA0/IO66RSB0 GDB0/IO64RSB0 GDB1/IO63RSB0 VCCIB0 GND IO60RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA2/IO57RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCB0/IO54RSB0 GCB1/IO53RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 IO50RSB0 IO49RSB0 NC NC NC VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0 IO44RSB0 GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ
3- 26
R e visio n 9
144-Pin TQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P125 Function GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 VCCIB0 GND VCC IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO16RSB0 IO14RSB0 IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 VCCIB0 GND VCC GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Revision 9
3- 27
208-Pin PQFP
208
208-Pin PQFP
Note
3- 28
R e visio n 9
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 NC NC IO130RSB1 IO129RSB1 NC IO128RSB1 NC NC NC VCC GND VCCIB1 IO127RSB1 NC GFC1/IO126RSB1 GFC0/IO125RSB1 GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GND GFA2/IO120RSB1 NC GFB2/IO119RSB1 NC GFC2/IO118RSB1 IO117RSB1 NC
208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P125 Function IO116RSB1 IO115RSB1 NC VCCIB1 GND IO114RSB1 IO113RSB1 GEC1/IO112RSB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GND NC NC GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO103RSB1 IO102RSB1 IO101RSB1 IO100RSB1 VCCIB1 IO99RSB1 IO98RSB1 GND IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1 IO93RSB1 VCC VCCIB1
208-Pin PQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P125 Function IO92RSB1 IO91RSB1 IO90RSB1 IO89RSB1 IO88RSB1 IO87RSB1 IO86RSB1 IO85RSB1 GND IO84RSB1 IO83RSB1 IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 VCC VCCIB1 IO78RSB1 IO77RSB1 IO76RSB1 IO75RSB1 IO74RSB1 IO73RSB1 GDC2/IO72RSB1 GND GDB2/IO71RSB1 GDA2/IO70RSB1 GNDQ TCK TDI TMS VMV1 GND VPUMP NC TDO
Revision 9
3- 29
208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P125 Function TRST VJTAG GDA0/IO66RSB0 GDA1/IO65RSB0 GDB0/IO64RSB0 GDB1/IO63RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 NC NC NC NC NC GND VCCIB0 NC NC VCC IO60RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GND GCA2/IO57RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCB0/IO54RSB0 GCB1/IO53RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 IO50RSB0 IO49RSB0 VCCIB0 GND VCC IO48RSB0 IO47RSB0
208-Pin PQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3P125 Function IO46RSB0 NC NC NC GBC2/IO45RSB0 IO44RSB0 GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ GND NC GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GND GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 IO30RSB0 VCCIB0 VCC IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 GND IO23RSB0 IO22RSB0
208-Pin PQFP Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3P125 Function IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 VCCIB0 VCC IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 GND IO09RSB0 IO08RSB0 IO07RSB0 IO06RSB0 VCCIB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
3- 30
R e visio n 9
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO115UDB3 IO115VDB3 IO114UDB3 IO114VDB3 IO113PDB3 IO113NDB3 IO112PDB3 IO112NDB3 VCC GND VCCIB3 IO111PDB3 IO111NDB3 GFC1/IO110PDB3 GFC0/IO110NDB3 GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GND GFA2/IO107PDB3 IO107NDB3 GFB2/IO106PDB3 IO106NDB3 GFC2/IO105PDB3 IO105NDB3 NC
208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P250 Function IO104PDB3 IO104NDB3 IO103PSB3 VCCIB3 GND IO101PDB3 IO101NDB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEB1/IO99PDB3 GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GND NC NC GEA2/IO97RSB2 GEB2/IO96RSB2 GEC2/IO95RSB2 IO94RSB2 IO93RSB2 IO92RSB2 IO91RSB2 VCCIB2 IO90RSB2 IO89RSB2 GND IO88RSB2 IO87RSB2 IO86RSB2 IO85RSB2 IO84RSB2 VCC VCCIB2
Revision 9
3- 31
208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P250 Function TRST VJTAG GDA0/IO60VDB1 GDA1/IO60UDB1 GDB0/IO59VDB1 GDB1/IO59UDB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO57VDB1 IO57UDB1 IO56NDB1 IO56PDB1 IO55RSB1 GND VCCIB1 NC NC VCC IO53NDB1 GCC2/IO53PDB1 GCB2/IO52PSB1 GND GCA2/IO51PSB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCB0/IO49NDB1 GCB1/IO49PDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 IO47NDB1 IO47PDB1 VCCIB1 GND VCC IO46RSB1 IO45NDB1
208-Pin PQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3P250 Function IO45PDB1 IO44NDB1 IO44PDB1 IO43NDB1 GBC2/IO43PDB1 IO42NDB1 GBB2/IO42PDB1 IO41NDB1 GBA2/IO41PDB1 VMV1 GNDQ GND NC GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GND GBC1/IO36RSB0 GBC0/IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 IO30RSB0 VCCIB0 VCC IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 GND IO23RSB0 IO22RSB0
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R e visio n 9
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P400 Function GND GAA2/IO155UDB3 IO155VDB3 GAB2/IO154UDB3 IO154VDB3 GAC2/IO153UDB3 IO153VDB3 IO152UDB3 IO152VDB3 IO151UDB3 IO151VDB3 IO150PDB3 IO150NDB3 IO149PDB3 IO149NDB3 VCC GND VCCIB3 IO148PDB3 IO148NDB3 GFC1/IO147PDB3 GFC0/IO147NDB3 GFB1/IO146PDB3 GFB0/IO146NDB3 VCOMPLF GFA0/IO145NPB3 VCCPLF GFA1/IO145PPB3 GND GFA2/IO144PDB3 IO144NDB3 GFB2/IO143PDB3 IO143NDB3 GFC2/IO142PDB3 IO142NDB3 NC
208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P400 Function IO141PSB3 IO140PDB3 IO140NDB3 VCCIB3 GND IO138PDB3 IO138NDB3 GEC1/IO137PDB3 GEC0/IO137NDB3 GEB1/IO136PDB3 GEB0/IO136NDB3 GEA1/IO135PDB3 GEA0/IO135NDB3 VMV3 GNDQ GND VMV2 NC GEA2/IO134RSB2 GEB2/IO133RSB2 GEC2/IO132RSB2 IO131RSB2 IO130RSB2 IO129RSB2 IO128RSB2 VCCIB2 IO125RSB2 IO123RSB2 GND IO121RSB2 IO119RSB2 IO117RSB2 IO115RSB2 IO113RSB2 VCC VCCIB2
Revision 9
3- 33
208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P400 Function TRST VJTAG GDA0/IO79VDB1 GDA1/IO79UDB1 GDB0/IO78VDB1 GDB1/IO78UDB1 GDC0/IO77VDB1 GDC1/IO77UDB1 IO76VDB1 IO76UDB1 IO75NDB1 IO75PDB1 IO74RSB1 GND VCCIB1 NC NC VCC IO72NDB1 GCC2/IO72PDB1 GCB2/IO71PSB1 GND GCA2/IO70PSB1 GCA1/IO69PDB1 GCA0/IO69NDB1 GCB0/IO68NDB1 GCB1/IO68PDB1 GCC0/IO67NDB1 GCC1/IO67PDB1 IO66NDB1 IO66PDB1 VCCIB1 GND VCC IO65RSB1 IO64NDB1
208-Pin PQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3P400 Function IO64PDB1 IO63NDB1 IO63PDB1 IO62NDB1 GBC2/IO62PDB1 IO61NDB1 GBB2/IO61PDB1 IO60NDB1 GBA2/IO60PDB1 VMV1 GNDQ GND VMV0 GBA1/IO59RSB0 GBA0/IO58RSB0 GBB1/IO57RSB0 GBB0/IO56RSB0 GND GBC1/IO55RSB0 GBC0/IO54RSB0 IO52RSB0 IO49RSB0 IO46RSB0 IO43RSB0 IO40RSB0 VCCIB0 VCC IO36RSB0 IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO31RSB0 GND IO29RSB0 IO28RSB0
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R e visio n 9
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P600 Function GND GAA2/IO174PDB3 IO174NDB3 GAB2/IO173PDB3 IO173NDB3 GAC2/IO172PDB3 IO172NDB3 IO171PDB3 IO171NDB3 IO170PDB3 IO170NDB3 IO169PDB3 IO169NDB3 IO168PDB3 IO168NDB3 VCC GND VCCIB3 IO166PDB3 IO166NDB3 GFC1/IO164PDB3 GFC0/IO164NDB3 GFB1/IO163PDB3 GFB0/IO163NDB3 VCOMPLF GFA0/IO162NPB3 VCCPLF GFA1/IO162PPB3 GND GFA2/IO161PDB3 IO161NDB3 GFB2/IO160PDB3 IO160NDB3 GFC2/IO159PDB3 IO159NDB3 VCC
208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P600 Function IO152PDB3 IO152NDB3 IO150PSB3 VCCIB3 GND IO147PDB3 IO147NDB3 GEC1/IO146PDB3 GEC0/IO146NDB3 GEB1/IO145PDB3 GEB0/IO145NDB3 GEA1/IO144PDB3 GEA0/IO144NDB3 VMV3 GNDQ GND VMV2 GEA2/IO143RSB2 GEB2/IO142RSB2 GEC2/IO141RSB2 IO140RSB2 IO139RSB2 IO138RSB2 IO137RSB2 IO136RSB2 VCCIB2 IO135RSB2 IO133RSB2 GND IO131RSB2 IO129RSB2 IO127RSB2 IO125RSB2 IO123RSB2 VCC VCCIB2
208-Pin PQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P600 Function IO120RSB2 IO119RSB2 IO118RSB2 IO117RSB2 IO116RSB2 IO115RSB2 IO114RSB2 IO112RSB2 GND IO111RSB2 IO110RSB2 IO109RSB2 IO108RSB2 IO107RSB2 IO106RSB2 VCC VCCIB2 IO104RSB2 IO102RSB2 IO100RSB2 IO98RSB2 IO96RSB2 IO92RSB2 GDC2/IO91RSB2 GND GDB2/IO90RSB2 GDA2/IO89RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP GNDQ TDO
Revision 9
3- 35
208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P600 Function TRST VJTAG GDA0/IO88NDB1 GDA1/IO88PDB1 GDB0/IO87NDB1 GDB1/IO87PDB1 GDC0/IO86NDB1 GDC1/IO86PDB1 IO84NDB1 IO84PDB1 IO82NDB1 IO82PDB1 IO81PSB1 GND VCCIB1 IO77NDB1 IO77PDB1 NC IO74NDB1 GCC2/IO74PDB1 GCB2/IO73PSB1 GND GCA2/IO72PSB1 GCA1/IO71PDB1 GCA0/IO71NDB1 GCB0/IO70NDB1 GCB1/IO70PDB1 GCC0/IO69NDB1 GCC1/IO69PDB1 IO67NDB1 IO67PDB1 VCCIB1 GND VCC IO65PSB1 IO64NDB1
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R e visio n 9
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3P1000 Function GND GAA2/IO225PDB3 IO225NDB3 GAB2/IO224PDB3 IO224NDB3 GAC2/IO223PDB3 IO223NDB3 IO222PDB3 IO222NDB3 IO220PDB3 IO220NDB3 IO218PDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCC GND VCCIB3 IO212PDB3 IO212NDB3 GFC1/IO209PDB3 GFC0/IO209NDB3 GFB1/IO208PDB3 GFB0/IO208NDB3 VCOMPLF GFA0/IO207NPB3 VCCPLF GFA1/IO207PPB3 GND GFA2/IO206PDB3 IO206NDB3 GFB2/IO205PDB3 IO205NDB3 GFC2/IO204PDB3 IO204NDB3 VCC
208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3P1000 Function IO199PDB3 IO199NDB3 IO197PSB3 VCCIB3 GND IO191PDB3 IO191NDB3 GEC1/IO190PDB3 GEC0/IO190NDB3 GEB1/IO189PDB3 GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 VMV3 GNDQ GND VMV2 GEA2/IO187RSB2 GEB2/IO186RSB2 GEC2/IO185RSB2 IO184RSB2 IO183RSB2 IO182RSB2 IO181RSB2 IO180RSB2 VCCIB2 IO178RSB2 IO176RSB2 GND IO174RSB2 IO172RSB2 IO170RSB2 IO168RSB2 IO166RSB2 VCC VCCIB2
208-Pin PQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3P1000 Function IO162RSB2 IO160RSB2 IO158RSB2 IO156RSB2 IO154RSB2 IO152RSB2 IO150RSB2 IO148RSB2 GND IO143RSB2 IO141RSB2 IO139RSB2 IO137RSB2 IO135RSB2 IO133RSB2 VCC VCCIB2 IO128RSB2 IO126RSB2 IO124RSB2 IO122RSB2 IO120RSB2 IO118RSB2 GDC2/IO116RSB2 GND GDB2/IO115RSB2 GDA2/IO114RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP GNDQ TDO
Revision 9
3- 37
208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3P1000 Function TRST VJTAG GDA0/IO113NDB1 GDA1/IO113PDB1 GDB0/IO112NDB1 GDB1/IO112PDB1 GDC0/IO111NDB1 GDC1/IO111PDB1 IO109NDB1 IO109PDB1 IO106NDB1 IO106PDB1 IO104PSB1 GND VCCIB1 IO99NDB1 IO99PDB1 NC IO96NDB1 GCC2/IO96PDB1 GCB2/IO95PSB1 GND GCA2/IO94PSB1 GCA1/IO93PDB1 GCA0/IO93NDB1 GCB0/IO92NDB1 GCB1/IO92PDB1 GCC0/IO91NDB1 GCC1/IO91PDB1 IO88NDB1 IO88PDB1 VCCIB1 GND VCC IO86PSB1 IO84NDB1
3- 38
R e visio n 9
144-Pin FBGA
A1 Ball Pad Corner
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
Note: This is the bottom view of the package.
Note
Revision 9
3- 39
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P060 Function GNDQ VMV0 GAB0/IO04RSB0 GAB1/IO05RSB0 IO08RSB0 GND IO11RSB0 VCC IO16RSB0 GBA0/IO23RSB0 GBA1/IO24RSB0 GNDQ GAB2/IO53RSB1 GND GAA0/IO02RSB0 GAA1/IO03RSB0 IO00RSB0 IO10RSB0 IO12RSB0 IO14RSB0 GBB0/IO21RSB0 GBB1/IO22RSB0 GND VMV0 IO95RSB1 GFA2/IO83RSB1 GAC2/IO94RSB1 VCC IO01RSB0 IO09RSB0 IO13RSB0 IO15RSB0 IO17RSB0 GBA2/IO25RSB0 IO26RSB0 GBC2/IO29RSB0
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P060 Function IO91RSB1 IO92RSB1 IO93RSB1 GAA2/IO51RSB1 GAC0/IO06RSB0 GAC1/IO07RSB0 GBC0/IO19RSB0 GBC1/IO20RSB0 GBB2/IO27RSB0 IO18RSB0 IO28RSB0 GCB1/IO37RSB0 VCC GFC0/IO88RSB1 GFC1/IO89RSB1 VCCIB1 IO52RSB1 VCCIB0 VCCIB0 GCC1/IO35RSB0 VCCIB0 VCC GCA0/IO40RSB0 IO30RSB0 GFB0/IO86RSB1 VCOMPLF GFB1/IO87RSB1 IO90RSB1 GND GND GND GCC0/IO36RSB0 GCB0/IO38RSB0 GND GCA1/IO39RSB0 GCA2/IO41RSB0
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P060 Function GFA1/IO84RSB1 GND VCCPLF GFA0/IO85RSB1 GND GND GND GDC1/IO45RSB0 IO32RSB0 GCC2/IO43RSB0 IO31RSB0 GCB2/IO42RSB0 VCC GFB2/IO82RSB1 GFC2/IO81RSB1 GEC1/IO77RSB1 VCC IO34RSB0 IO44RSB0 GDB2/IO55RSB1 GDC0/IO46RSB0 VCCIB0 IO33RSB0 VCC GEB1/IO75RSB1 IO78RSB1 VCCIB1 GEC0/IO76RSB1 IO79RSB1 IO80RSB1 VCC TCK GDA2/IO54RSB1 TDO GDA1/IO49RSB0 GDB1/IO47RSB0
3- 40
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P060 Function GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 GEA2/IO71RSB1 IO65RSB1 IO64RSB1 GND IO57RSB1 GDC2/IO56RSB1 GND GDA0/IO50RSB0 GDB0/IO48RSB0 GND VMV1 GEB2/IO70RSB1 IO67RSB1 VCCIB1 IO62RSB1 IO59RSB1 IO58RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO69RSB1 IO68RSB1 IO66RSB1 IO63RSB1 IO61RSB1 IO60RSB1 NC TDI VCCIB1 VPUMP GNDQ
Revision 9
3- 41
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P125 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO11RSB0 GND IO18RSB0 VCC IO25RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO69RSB1 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO08RSB0 IO14RSB0 IO19RSB0 IO22RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV0 IO132RSB1 GFA2/IO120RSB1 GAC2/IO131RSB1 VCC IO10RSB0 IO12RSB0 IO21RSB0 IO24RSB0 IO27RSB0 GBA2/IO41RSB0 IO42RSB0 GBC2/IO45RSB0
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P125 Function IO128RSB1 IO129RSB1 IO130RSB1 GAA2/IO67RSB1 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO43RSB0 IO28RSB0 IO44RSB0 GCB1/IO53RSB0 VCC GFC0/IO125RSB1 GFC1/IO126RSB1 VCCIB1 IO68RSB1 VCCIB0 VCCIB0 GCC1/IO51RSB0 VCCIB0 VCC GCA0/IO56RSB0 IO46RSB0 GFB0/IO123RSB1 VCOMPLF GFB1/IO124RSB1 IO127RSB1 GND GND GND GCC0/IO52RSB0 GCB0/IO54RSB0 GND GCA1/IO55RSB0 GCA2/IO57RSB0
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P125 Function GFA1/IO121RSB1 GND VCCPLF GFA0/IO122RSB1 GND GND GND GDC1/IO61RSB0 IO48RSB0 GCC2/IO59RSB0 IO47RSB0 GCB2/IO58RSB0 VCC GFB2/IO119RSB1 GFC2/IO118RSB1 GEC1/IO112RSB1 VCC IO50RSB0 IO60RSB0 GDB2/IO71RSB1 GDC0/IO62RSB0 VCCIB0 IO49RSB0 VCC GEB1/IO110RSB1 IO115RSB1 VCCIB1 GEC0/IO111RSB1 IO116RSB1 IO117RSB1 VCC TCK GDA2/IO70RSB1 TDO GDA1/IO65RSB0 GDB1/IO63RSB0
3- 42
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P125 Function GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 GEA2/IO106RSB1 IO100RSB1 IO98RSB1 GND IO73RSB1 GDC2/IO72RSB1 GND GDA0/IO66RSB0 GDB0/IO64RSB0 GND VMV1 GEB2/IO105RSB1 IO102RSB1 VCCIB1 IO95RSB1 IO85RSB1 IO74RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO104RSB1 IO103RSB1 IO101RSB1 IO97RSB1 IO94RSB1 IO86RSB1 IO75RSB1 TDI VCCIB1 VPUMP GNDQ
Revision 9
3- 43
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P250 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO29RSB0 VCC IO33RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO117UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO22RSB0 IO30RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV1 IO117VDB3 GFA2/IO107PPB3 GAC2/IO116UDB3 VCC IO12RSB0 IO17RSB0 IO24RSB0 IO31RSB0 IO34RSB0 GBA2/IO41PDB1 IO41NDB1 GBC2/IO43PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P250 Function IO112NDB3 IO112PDB3 IO116VDB3 GAA2/IO118UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO42PDB1 IO42NDB1 IO43NPB1 GCB1/IO49PPB1 VCC GFC0/IO110NDB3 GFC1/IO110PDB3 VCCIB3 IO118VPB3 VCCIB0 VCCIB0 GCC1/IO48PDB1 VCCIB1 VCC GCA0/IO50NDB1 IO51NDB1 GFB0/IO109NPB3 VCOMPLF GFB1/IO109PPB3 IO107NPB3 GND GND GND GCC0/IO48NDB1 GCB0/IO49NPB1 GND GCA1/IO50PDB1 GCA2/IO51PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P250 Function GFA1/IO108PPB3 GND VCCPLF GFA0/IO108NPB3 GND GND GND GDC1/IO58UPB1 IO53NDB1 GCC2/IO53PDB1 IO52NDB1 GCB2/IO52PDB1 VCC GFB2/IO106PDB3 GFC2/IO105PSB3 GEC1/IO100PDB3 VCC IO79RSB2 IO65RSB2 GDB2/IO62RSB2 GDC0/IO58VPB1 VCCIB1 IO54PSB1 VCC GEB1/IO99PDB3 IO106NDB3 VCCIB3 GEC0/IO100NDB3 IO88RSB2 IO81RSB2 VCC TCK GDA2/IO61RSB2 TDO GDA1/IO60UDB1 GDB1/IO59UDB1
3- 44
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P250 Function GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 GEA2/IO97RSB2 IO90RSB2 IO84RSB2 GND IO66RSB2 GDC2/IO63RSB2 GND GDA0/IO60VDB1 GDB0/IO59VDB1 GND VMV3 GEB2/IO96RSB2 IO91RSB2 VCCIB2 IO82RSB2 IO80RSB2 IO72RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO95RSB2 IO92RSB2 IO89RSB2 IO87RSB2 IO85RSB2 IO78RSB2 IO76RSB2 TDI VCCIB2 VPUMP GNDQ
Revision 9
3- 45
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P400 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO30RSB0 VCC IO34RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GNDQ GAB2/IO154UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO23RSB0 IO31RSB0 GBB0/IO56RSB0 GBB1/IO57RSB0 GND VMV1 IO154VDB3 GFA2/IO144PPB3 GAC2/IO153UDB3 VCC IO12RSB0 IO17RSB0 IO25RSB0 IO32RSB0 IO53RSB0 GBA2/IO60PDB1 IO60NDB1 GBC2/IO62PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P400 Function IO149NDB3 IO149PDB3 IO153VDB3 GAA2/IO155UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO54RSB0 GBC1/IO55RSB0 GBB2/IO61PDB1 IO61NDB1 IO62NPB1 GCB1/IO68PPB1 VCC GFC0/IO147NDB3 GFC1/IO147PDB3 VCCIB3 IO155VPB3 VCCIB0 VCCIB0 GCC1/IO67PDB1 VCCIB1 VCC GCA0/IO69NDB1 IO70NDB1 GFB0/IO146NPB3 VCOMPLF GFB1/IO146PPB3 IO144NPB3 GND GND GND GCC0/IO67NDB1 GCB0/IO68NPB1 GND GCA1/IO69PDB1 GCA2/IO70PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P400 Function GFA1/IO145PPB3 GND VCCPLF GFA0/IO145NPB3 GND GND GND GDC1/IO77UPB1 IO72NDB1 GCC2/IO72PDB1 IO71NDB1 GCB2/IO71PDB1 VCC GFB2/IO143PDB3 GFC2/IO142PSB3 GEC1/IO137PDB3 VCC IO75PDB1 IO75NDB1 GDB2/IO81RSB2 GDC0/IO77VPB1 VCCIB1 IO73PSB1 VCC GEB1/IO136PDB3 IO143NDB3 VCCIB3 GEC0/IO137NDB3 IO125RSB2 IO116RSB2 VCC TCK GDA2/IO80RSB2 TDO GDA1/IO79UDB1 GDB1/IO78UDB1
3- 46
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P400 Function GEB0/IO136NDB3 GEA1/IO135PDB3 GEA0/IO135NDB3 GEA2/IO134RSB2 IO127RSB2 IO121RSB2 GND IO104RSB2 GDC2/IO82RSB2 GND GDA0/IO79VDB1 GDB0/IO78VDB1 GND VMV3 GEB2/IO133RSB2 IO128RSB2 VCCIB2 IO119RSB2 IO114RSB2 IO110RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO132RSB2 IO129RSB2 IO126RSB2 IO124RSB2 IO122RSB2 IO117RSB2 IO115RSB2 TDI VCCIB2 VPUMP GNDQ
Revision 9
3- 47
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P600 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO34RSB0 VCC IO50RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GNDQ GAB2/IO173PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO19RSB0 IO31RSB0 IO39RSB0 GBB0/IO56RSB0 GBB1/IO57RSB0 GND VMV1 IO173NDB3 GFA2/IO161PPB3 GAC2/IO172PDB3 VCC IO16RSB0 IO25RSB0 IO28RSB0 IO42RSB0 IO45RSB0 GBA2/IO60PDB1 IO60NDB1 GBC2/IO62PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P600 Function IO169PDB3 IO169NDB3 IO172NDB3 GAA2/IO174PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO54RSB0 GBC1/IO55RSB0 GBB2/IO61PDB1 IO61NDB1 IO62NPB1 GCB1/IO70PPB1 VCC GFC0/IO164NDB3 GFC1/IO164PDB3 VCCIB3 IO174NPB3 VCCIB0 VCCIB0 GCC1/IO69PDB1 VCCIB1 VCC GCA0/IO71NDB1 IO72NDB1 GFB0/IO163NPB3 VCOMPLF GFB1/IO163PPB3 IO161NPB3 GND GND GND GCC0/IO69NDB1 GCB0/IO70NPB1 GND GCA1/IO71PDB1 GCA2/IO72PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P600 Function GFA1/IO162PPB3 GND VCCPLF GFA0/IO162NPB3 GND GND GND GDC1/IO86PPB1 IO74NDB1 GCC2/IO74PDB1 IO73NDB1 GCB2/IO73PDB1 VCC GFB2/IO160PDB3 GFC2/IO159PSB3 GEC1/IO146PDB3 VCC IO80PDB1 IO80NDB1 GDB2/IO90RSB2 GDC0/IO86NPB1 VCCIB1 IO84PSB1 VCC GEB1/IO145PDB3 IO160NDB3 VCCIB3 GEC0/IO146NDB3 IO129RSB2 IO131RSB2 VCC TCK GDA2/IO89RSB2 TDO GDA1/IO88PDB1 GDB1/IO87PDB1
3- 48
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P600 Function GEB0/IO145NDB3 GEA1/IO144PDB3 GEA0/IO144NDB3 GEA2/IO143RSB2 IO119RSB2 IO111RSB2 GND IO94RSB2 GDC2/IO91RSB2 GND GDA0/IO88NDB1 GDB0/IO87NDB1 GND VMV3 GEB2/IO142RSB2 IO136RSB2 VCCIB2 IO115RSB2 IO103RSB2 IO97RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO141RSB2 IO138RSB2 IO123RSB2 IO126RSB2 IO134RSB2 IO108RSB2 IO99RSB2 TDI VCCIB2 VPUMP GNDQ
Revision 9
3- 49
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A3P1000 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO44RSB0 VCC IO69RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GNDQ GAB2/IO224PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO26RSB0 IO35RSB0 IO60RSB0 GBB0/IO74RSB0 GBB1/IO75RSB0 GND VMV1 IO224NDB3 GFA2/IO206PPB3 GAC2/IO223PDB3 VCC IO16RSB0 IO29RSB0 IO32RSB0 IO63RSB0 IO66RSB0 GBA2/IO78PDB1 IO78NDB1 GBC2/IO80PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 A3P1000 Function IO213PDB3 IO213NDB3 IO223NDB3 GAA2/IO225PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO72RSB0 GBC1/IO73RSB0 GBB2/IO79PDB1 IO79NDB1 IO80NPB1 GCB1/IO92PPB1 VCC GFC0/IO209NDB3 GFC1/IO209PDB3 VCCIB3 IO225NPB3 VCCIB0 VCCIB0 GCC1/IO91PDB1 VCCIB1 VCC GCA0/IO93NDB1 IO94NDB1 GFB0/IO208NPB3 VCOMPLF GFB1/IO208PPB3 IO206NPB3 GND GND GND GCC0/IO91NDB1 GCB0/IO92NPB1 GND GCA1/IO93PDB1 GCA2/IO94PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A3P1000 Function GFA1/IO207PPB3 GND VCCPLF GFA0/IO207NPB3 GND GND GND GDC1/IO111PPB1 IO96NDB1 GCC2/IO96PDB1 IO95NDB1 GCB2/IO95PDB1 VCC GFB2/IO205PDB3 GFC2/IO204PSB3 GEC1/IO190PDB3 VCC IO105PDB1 IO105NDB1 GDB2/IO115RSB2 GDC0/IO111NPB1 VCCIB1 IO101PSB1 VCC GEB1/IO189PDB3 IO205NDB3 VCCIB3 GEC0/IO190NDB3 IO160RSB2 IO157RSB2 VCC TCK GDA2/IO114RSB2 TDO GDA1/IO113PDB1 GDB1/IO112PDB1
3- 50
R e visio n 9
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 A3P1000 Function GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 GEA2/IO187RSB2 IO169RSB2 IO152RSB2 GND IO117RSB2 GDC2/IO116RSB2 GND GDA0/IO113NDB1 GDB0/IO112NDB1 GND VMV3 GEB2/IO186RSB2 IO172RSB2 VCCIB2 IO153RSB2 IO144RSB2 IO140RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO185RSB2 IO173RSB2 IO168RSB2 IO161RSB2 IO156RSB2 IO145RSB2 IO141RSB2 TDI VCCIB2 VPUMP GNDQ
Revision 9
3- 51
256-Pin FBGA
A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T
Note
3- 52
R e visio n 9
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3P250 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO07RSB0 IO10RSB0 IO11RSB0 IO15RSB0 IO20RSB0 IO25RSB0 IO29RSB0 IO33RSB0 GBB1/IO38RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GND GAB2/IO117UDB3 GAA2/IO118UDB3 NC GAB1/IO03RSB0 IO06RSB0 IO09RSB0 IO12RSB0 IO16RSB0 IO21RSB0 IO26RSB0 IO30RSB0 GBC1/IO36RSB0 GBB0/IO37RSB0 NC GBA2/IO41PDB1 IO41NDB1 IO117VDB3 IO118VDB3 NC NC
256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3P250 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO13RSB0 IO17RSB0 IO22RSB0 IO27RSB0 IO31RSB0 GBC0/IO35RSB0 IO34RSB0 NC IO42NPB1 IO44PDB1 IO114VDB3 IO114UDB3 GAC2/IO116UDB3 NC GNDQ IO08RSB0 IO14RSB0 IO18RSB0 IO23RSB0 IO28RSB0 IO32RSB0 GNDQ NC GBB2/IO42PPB1 NC IO44NDB1 IO113PDB3 NC IO116VDB3 IO115UDB3 VMV0 VCCIB0 VCCIB0 IO19RSB0
256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P250 Function IO24RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO43PDB1 IO46RSB1 NC IO45PDB1 IO113NDB3 IO112PPB3 NC IO115VDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO43NDB1 NC IO47PPB1 IO45NDB1 IO111NDB3 IO111PDB3 IO112NPB3 GFC1/IO110PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1
Revision 9
3- 53
256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3P250 Function GCC1/IO48PPB1 IO47NPB1 IO54PDB1 IO54NDB1 GFB0/IO109NPB3 GFA0/IO108NDB3 GFB1/IO109PPB3 VCOMPLF GFC0/IO110NPB3 VCC GND GND GND GND VCC GCC0/IO48NPB1 GCB1/IO49PPB1 GCA0/IO50NPB1 NC GCB0/IO49NPB1 GFA2/IO107PPB3 GFA1/IO108PDB3 VCCPLF IO106NDB3 GFB2/IO106PDB3 VCC GND GND GND GND VCC GCB2/IO52PPB1 GCA1/IO50PPB1 GCC2/IO53PPB1 NC GCA2/IO51PDB1
256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3P250 Function GFC2/IO105PDB3 IO107NPB3 IO104PPB3 NC VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO52NPB1 IO55RSB1 IO53NPB1 IO51NDB1 IO105NDB3 IO104NPB3 NC IO102RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO59VPB1 IO57VDB1 IO57UDB1 IO56PDB1 IO103PDB3 NC IO101NPB3 GEC0/IO100NPB3
256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3P250 Function VMV3 VCCIB2 VCCIB2 NC IO74RSB2 VCCIB2 VCCIB2 VMV2 NC GDB1/IO59UPB1 GDC1/IO58UDB1 IO56NDB1 IO103NDB3 IO101PPB3 GEC1/IO100PPB3 NC GNDQ GEA2/IO97RSB2 IO86RSB2 IO82RSB2 IO75RSB2 IO69RSB2 IO64RSB2 GNDQ NC VJTAG GDC0/IO58VDB1 GDA1/IO60UDB1 GEB1/IO99PDB3 GEB0/IO99NDB3 NC NC IO92RSB2 IO89RSB2 IO85RSB2 IO81RSB2
3- 54
R e visio n 9
256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3P250 Function IO76RSB2 IO71RSB2 IO66RSB2 NC TCK VPUMP TRST GDA0/IO60VDB1 GEA1/IO98PDB3 GEA0/IO98NDB3 NC GEC2/IO95RSB2 IO91RSB2 IO88RSB2 IO84RSB2 IO80RSB2 IO77RSB2 IO72RSB2 IO68RSB2 IO65RSB2 GDB2/IO62RSB2 TDI NC TDO GND IO94RSB2 GEB2/IO96RSB2 IO93RSB2 IO90RSB2 IO87RSB2 IO83RSB2 IO79RSB2 IO78RSB2 IO73RSB2 IO70RSB2 GDC2/IO63RSB2
256-Pin FBGA Pin Number T13 T14 T15 T16 A3P250 Function IO67RSB2 GDA2/IO61RSB2 TMS GND
Revision 9
3- 55
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3P400 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO17RSB0 IO22RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO154UDB3 GAA2/IO155UDB3 IO12RSB0 GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO44RSB0 GBA2/IO60PDB1 IO60NDB1 IO154VDB3 IO155VDB3 IO11RSB0 IO07RSB0
256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3P400 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO45RSB0 GBC0/IO54RSB0 IO48RSB0 VMV0 IO61NPB1 IO63PDB1 IO151VDB3 IO151UDB3 GAC2/IO153UDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO46RSB0 GNDQ IO47RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 IO150PDB3 IO08RSB0 IO153VDB3 IO152VDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0
256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P400 Function IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO65RSB1 IO52RSB0 IO66PDB1 IO150NDB3 IO149NPB3 IO09RSB0 IO152UDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO49RSB0 IO64PPB1 IO66NDB1 IO148NDB3 IO148PDB3 IO149PPB3 GFC1/IO147PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1
3- 56
R e visio n 9
256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3P400 Function GCC1/IO67PPB1 IO64NPB1 IO73PDB1 IO73NDB1 GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO143NDB3 GFB2/IO143PDB3 VCC GND GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PPB1 NC GCA2/IO70PDB1
256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3P400 Function GFC2/IO142PDB3 IO144NPB3 IO141PPB3 IO120RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1 IO74RSB1 IO72NPB1 IO70NDB1 IO142NDB3 IO141NPB3 IO125RSB2 IO139RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO78VPB1 IO76VDB1 IO76UDB1 IO75PDB1 IO140PDB3 IO130RSB2 IO138NPB3 GEC0/IO137NPB3
256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3P400 Function VMV3 VCCIB2 VCCIB2 IO108RSB2 IO101RSB2 VCCIB2 VCCIB2 VMV2 IO83RSB2 GDB1/IO78UPB1 GDC1/IO77UDB1 IO75NDB1 IO140NDB3 IO138PPB3 GEC1/IO137PPB3 IO131RSB2 GNDQ GEA2/IO134RSB2 IO117RSB2 IO111RSB2 IO99RSB2 IO94RSB2 IO87RSB2 GNDQ IO93RSB2 VJTAG GDC0/IO77VDB1 GDA1/IO79UDB1 GEB1/IO136PDB3 GEB0/IO136NDB3 VMV2 IO129RSB2 IO128RSB2 IO122RSB2 IO115RSB2 IO110RSB2
Revision 9
3- 57
256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3P400 Function IO98RSB2 IO95RSB2 IO88RSB2 IO84RSB2 TCK VPUMP TRST GDA0/IO79VDB1 GEA1/IO135PDB3 GEA0/IO135NDB3 IO127RSB2 GEC2/IO132RSB2 IO123RSB2 IO118RSB2 IO112RSB2 IO106RSB2 IO100RSB2 IO96RSB2 IO89RSB2 IO85RSB2 GDB2/IO81RSB2 TDI NC TDO GND IO126RSB2 GEB2/IO133RSB2 IO124RSB2 IO116RSB2 IO113RSB2 IO107RSB2 IO105RSB2 IO102RSB2 IO97RSB2 IO92RSB2 GDC2/IO82RSB2
3- 58
R e visio n 9
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3P600 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO11RSB0 IO16RSB0 IO18RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO173PDB3 GAA2/IO174PDB3 GNDQ GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO52RSB0 GBA2/IO60PDB1 IO60NDB1 IO173NDB3 IO174NDB3 VMV3 IO07RSB0
256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3P600 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 VMV0 IO61NPB1 IO63PDB1 IO171NDB3 IO171PDB3 GAC2/IO172PDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO45RSB0 GNDQ IO50RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 IO166PDB3 IO167NPB3 IO172NDB3 IO169NDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0
256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P600 Function IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO67PPB1 IO64PPB1 IO66PDB1 IO166NDB3 IO168NPB3 IO167PPB3 IO169PDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO65PPB1 IO66NDB1 IO165NDB3 IO165PDB3 IO168PPB3 GFC1/IO164PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1
Revision 9
3- 59
256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3P600 Function GCC1/IO69PPB1 IO65NPB1 IO75PDB1 IO75NDB1 GFB0/IO163NPB3 GFA0/IO162NDB3 GFB1/IO163PPB3 VCOMPLF GFC0/IO164NPB3 VCC GND GND GND GND VCC GCC0/IO69NPB1 GCB1/IO70PPB1 GCA0/IO71NPB1 IO67NPB1 GCB0/IO70NPB1 GFA2/IO161PPB3 GFA1/IO162PDB3 VCCPLF IO160NDB3 GFB2/IO160PDB3 VCC GND GND GND GND VCC GCB2/IO73PPB1 GCA1/IO71PPB1 GCC2/IO74PPB1 IO80PPB1 GCA2/IO72PDB1
256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3P600 Function GFC2/IO159PDB3 IO161NPB3 IO156PPB3 IO129RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO73NPB1 IO80NPB1 IO74NPB1 IO72NDB1 IO159NDB3 IO156NPB3 IO151PPB3 IO158PSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO87NPB1 IO85NDB1 IO85PDB1 IO84PDB1 IO150PDB3 IO151NPB3 IO147NPB3 GEC0/IO146NPB3
256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3P600 Function VMV3 VCCIB2 VCCIB2 IO117RSB2 IO110RSB2 VCCIB2 VCCIB2 VMV2 IO94RSB2 GDB1/IO87PPB1 GDC1/IO86PDB1 IO84NDB1 IO150NDB3 IO147PPB3 GEC1/IO146PPB3 IO140RSB2 GNDQ GEA2/IO143RSB2 IO126RSB2 IO120RSB2 IO108RSB2 IO103RSB2 IO99RSB2 GNDQ IO92RSB2 VJTAG GDC0/IO86NDB1 GDA1/IO88PDB1 GEB1/IO145PDB3 GEB0/IO145NDB3 VMV2 IO138RSB2 IO136RSB2 IO131RSB2 IO124RSB2 IO119RSB2
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R e visio n 9
256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3P600 Function IO107RSB2 IO104RSB2 IO97RSB2 VMV1 TCK VPUMP TRST GDA0/IO88NDB1 GEA1/IO144PDB3 GEA0/IO144NDB3 IO139RSB2 GEC2/IO141RSB2 IO132RSB2 IO127RSB2 IO121RSB2 IO114RSB2 IO109RSB2 IO105RSB2 IO98RSB2 IO96RSB2 GDB2/IO90RSB2 TDI GNDQ TDO GND IO137RSB2 GEB2/IO142RSB2 IO134RSB2 IO125RSB2 IO123RSB2 IO118RSB2 IO115RSB2 IO111RSB2 IO106RSB2 IO102RSB2 GDC2/IO91RSB2
Revision 9
3- 61
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 A3P1000 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0
256-Pin FBGA Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 A3P1000 Function IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NSB1 IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1
256-Pin FBGA Pin Number E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 A3P1000 Function GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 IO210PSB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 GFB0/IO208NPB3 GFA0/IO207NDB3
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R e visio n 9
256-Pin FBGA Pin Number H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 A3P1000 Function GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 GFA2/IO206PSB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PSB1 GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND
256-Pin FBGA Pin Number K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 A3P1000 Function GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 IO197NSB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1
256-Pin FBGA Pin Number M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 A3P1000 Function GDC1/IO111PDB1 IO107NDB1 IO194PSB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2
Revision 9
3- 63
256-Pin FBGA Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 A3P1000 Function IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND
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R e visio n 9
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R T U V W Y AA AB
Note
Revision 9
3- 65
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P400 Function GND GND VCCIB0 NC NC IO15RSB0 IO18RSB0 NC NC IO23RSB0 IO29RSB0 IO35RSB0 IO36RSB0 NC NC IO50RSB0 IO51RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC NC NC NC NC NC NC NC NC NC
484-Pin FBGA Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P400 Function NC NC NC NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0
484-Pin FBGA Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P400 Function GAB0/IO02RSB0 IO16RSB0 IO17RSB0 IO22RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO154UDB3 GAA2/IO155UDB3 IO12RSB0 GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO44RSB0 GBA2/IO60PDB1 IO60NDB1 GND
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R e visio n 9
484-Pin FBGA Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P400 Function NC NC NC NC NC IO154VDB3 IO155VDB3 IO11RSB0 IO07RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO45RSB0 GBC0/IO54RSB0 IO48RSB0 VMV0 IO61NPB1 IO63PDB1 NC NC NC NC NC NC IO151VDB3 IO151UDB3 GAC2/IO153UDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0
484-Pin FBGA Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P400 Function IO40RSB0 IO46RSB0 GNDQ IO47RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 NC NC NC NC NC VCC IO150PDB3 IO08RSB0 IO153VDB3 IO152VDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0 IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO65RSB1 IO52RSB0 IO66PDB1 VCC NC NC NC NC NC IO150NDB3
484-Pin FBGA Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P400 Function IO149NPB3 IO09RSB0 IO152UDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO49RSB0 IO64PPB1 IO66NDB1 NC NC NC NC NC NC IO148NDB3 IO148PDB3 IO149PPB3 GFC1/IO147PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO67PPB1 IO64NPB1 IO73PDB1
Revision 9
3- 67
484-Pin FBGA Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P400 Function IO73NDB1 NC NC NC NC NC NC GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 NC NC NC NC NC NC GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO143NDB3 GFB2/IO143PDB3 VCC GND
484-Pin FBGA Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P400 Function GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PPB1 NC GCA2/IO70PDB1 NC NC NC NC NC NC GFC2/IO142PDB3 IO144NPB3 IO141PPB3 IO120RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1 IO74RSB1 IO72NPB1 IO70NDB1 NC NC NC NC NC
484-Pin FBGA Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P400 Function NC IO142NDB3 IO141NPB3 IO125RSB2 IO139RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO78VPB1 IO76VDB1 IO76UDB1 IO75PDB1 NC NC NC NC NC VCC IO140PDB3 IO130RSB2 IO138NPB3 GEC0/IO137NPB3 VMV3 VCCIB2 VCCIB2 IO108RSB2 IO101RSB2 VCCIB2 VCCIB2 VMV2 IO83RSB2
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484-Pin FBGA Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P400 Function GDB1/IO78UPB1 GDC1/IO77UDB1 IO75NDB1 VCC NC NC NC NC NC IO140NDB3 IO138PPB3 GEC1/IO137PPB3 IO131RSB2 GNDQ GEA2/IO134RSB2 IO117RSB2 IO111RSB2 IO99RSB2 IO94RSB2 IO87RSB2 GNDQ IO93RSB2 VJTAG GDC0/IO77VDB1 GDA1/IO79UDB1 NC NC NC NC NC NC GEB1/IO136PDB3 GEB0/IO136NDB3 VMV2 IO129RSB2 IO128RSB2
484-Pin FBGA Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P400 Function IO122RSB2 IO115RSB2 IO110RSB2 IO98RSB2 IO95RSB2 IO88RSB2 IO84RSB2 TCK VPUMP TRST GDA0/IO79VDB1 NC NC NC NC NC GND GEA1/IO135PDB3 GEA0/IO135NDB3 IO127RSB2 GEC2/IO132RSB2 IO123RSB2 IO118RSB2 IO112RSB2 IO106RSB2 IO100RSB2 IO96RSB2 IO89RSB2 IO85RSB2 GDB2/IO81RSB2 TDI NC TDO GND NC NC
484-Pin FBGA Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P400 Function NC NC NC GND IO126RSB2 GEB2/IO133RSB2 IO124RSB2 IO116RSB2 IO113RSB2 IO107RSB2 IO105RSB2 IO102RSB2 IO97RSB2 IO92RSB2 GDC2/IO82RSB2 IO86RSB2 GDA2/IO80RSB2 TMS GND NC NC NC VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC
Revision 9
3- 69
484-Pin FBGA Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P400 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO121RSB2
484-Pin FBGA Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P400 Function IO119RSB2 IO114RSB2 IO109RSB2 NC NC IO104RSB2 IO103RSB2 NC NC IO91RSB2 IO90RSB2 NC NC VCCIB2 GND GND
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R e visio n 9
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P600 Function GND GND VCCIB0 NC NC IO09RSB0 IO15RSB0 NC NC IO22RSB0 IO23RSB0 IO29RSB0 IO35RSB0 NC NC IO46RSB0 IO48RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC IO08RSB0 IO12RSB0 NC NC IO17RSB0 NC NC IO36RSB0 NC
484-Pin FBGA Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P600 Function NC IO47RSB0 IO49RSB0 NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0
484-Pin FBGA Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P600 Function GAB0/IO02RSB0 IO11RSB0 IO16RSB0 IO18RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO173PDB3 GAA2/IO174PDB3 GNDQ GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO52RSB0 GBA2/IO60PDB1 IO60NDB1 GND
Revision 9
3- 71
484-Pin FBGA Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P600 Function NC NC NC NC NC IO173NDB3 IO174NDB3 VMV3 IO07RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 VMV0 IO61NPB1 IO63PDB1 NC NC NC IO170NDB3 IO170PDB3 NC IO171NDB3 IO171PDB3 GAC2/IO172PDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0
484-Pin FBGA Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P600 Function IO40RSB0 IO45RSB0 GNDQ IO50RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 NC NC NC NC NC VCC IO166PDB3 IO167NPB3 IO172NDB3 IO169NDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0 IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO67PPB1 IO64PPB1 IO66PDB1 VCC NC NC NC NC NC IO166NDB3
484-Pin FBGA Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P600 Function IO168NPB3 IO167PPB3 IO169PDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO65PPB1 IO66NDB1 NC IO68PDB1 IO68NDB1 IO157PDB3 IO157NDB3 NC IO165NDB3 IO165PDB3 IO168PPB3 GFC1/IO164PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO69PPB1 IO65NPB1 IO75PDB1
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484-Pin FBGA Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P600 Function IO75NDB1 NC IO76NDB1 IO76PDB1 NC IO155PDB3 NC GFB0/IO163NPB3 GFA0/IO162NDB3 GFB1/IO163PPB3 VCOMPLF GFC0/IO164NPB3 VCC GND GND GND GND VCC GCC0/IO69NPB1 GCB1/IO70PPB1 GCA0/IO71NPB1 IO67NPB1 GCB0/IO70NPB1 IO77PDB1 IO77NDB1 IO78NPB1 NC IO155NDB3 IO158NPB3 GFA2/IO161PPB3 GFA1/IO162PDB3 VCCPLF IO160NDB3 GFB2/IO160PDB3 VCC GND
484-Pin FBGA Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P600 Function GND GND GND VCC GCB2/IO73PPB1 GCA1/IO71PPB1 GCC2/IO74PPB1 IO80PPB1 GCA2/IO72PDB1 IO79PPB1 IO78PPB1 NC IO154NDB3 IO154PDB3 NC GFC2/IO159PDB3 IO161NPB3 IO156PPB3 IO129RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO73NPB1 IO80NPB1 IO74NPB1 IO72NDB1 NC IO79NPB1 NC NC IO153PDB3
484-Pin FBGA Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P600 Function IO153NDB3 IO159NDB3 IO156NPB3 IO151PPB3 IO158PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO87NPB1 IO85NDB1 IO85PDB1 IO84PDB1 NC IO81PDB1 NC NC NC VCC IO150PDB3 IO151NPB3 IO147NPB3 GEC0/IO146NPB3 VMV3 VCCIB2 VCCIB2 IO117RSB2 IO110RSB2 VCCIB2 VCCIB2 VMV2 IO94RSB2
Revision 9
3- 73
484-Pin FBGA Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P600 Function GDB1/IO87PPB1 GDC1/IO86PDB1 IO84NDB1 VCC IO81NDB1 IO82PDB1 IO152PDB3 IO152NDB3 NC IO150NDB3 IO147PPB3 GEC1/IO146PPB3 IO140RSB2 GNDQ GEA2/IO143RSB2 IO126RSB2 IO120RSB2 IO108RSB2 IO103RSB2 IO99RSB2 GNDQ IO92RSB2 VJTAG GDC0/IO86NDB1 GDA1/IO88PDB1 NC IO83PDB1 IO82NDB1 IO149PDB3 IO149NDB3 NC GEB1/IO145PDB3 GEB0/IO145NDB3 VMV2 IO138RSB2 IO136RSB2
484-Pin FBGA Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P600 Function IO131RSB2 IO124RSB2 IO119RSB2 IO107RSB2 IO104RSB2 IO97RSB2 VMV1 TCK VPUMP TRST GDA0/IO88NDB1 NC IO83NDB1 NC NC NC GND GEA1/IO144PDB3 GEA0/IO144NDB3 IO139RSB2 GEC2/IO141RSB2 IO132RSB2 IO127RSB2 IO121RSB2 IO114RSB2 IO109RSB2 IO105RSB2 IO98RSB2 IO96RSB2 GDB2/IO90RSB2 TDI GNDQ TDO GND NC NC
484-Pin FBGA Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P600 Function NC IO148PDB3 NC GND IO137RSB2 GEB2/IO142RSB2 IO134RSB2 IO125RSB2 IO123RSB2 IO118RSB2 IO115RSB2 IO111RSB2 IO106RSB2 IO102RSB2 GDC2/IO91RSB2 IO93RSB2 GDA2/IO89RSB2 TMS GND NC NC NC VCCIB3 IO148NDB3 NC NC GND NC NC VCC VCC NC NC NC NC VCC
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484-Pin FBGA Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P600 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC NC NC IO135RSB2 IO133RSB2 NC NC NC NC NC NC NC NC IO101RSB2 NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO130RSB2
484-Pin FBGA Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P600 Function IO128RSB2 IO122RSB2 IO116RSB2 NC NC IO113RSB2 IO112RSB2 NC NC IO100RSB2 IO95RSB2 NC NC VCCIB2 GND GND
Revision 9
3- 75
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 A3P1000 Function GND GND VCCIB0 IO07RSB0 IO09RSB0 IO13RSB0 IO18RSB0 IO20RSB0 IO26RSB0 IO32RSB0 IO40RSB0 IO41RSB0 IO53RSB0 IO59RSB0 IO64RSB0 IO65RSB0 IO67RSB0 IO69RSB0 NC VCCIB0 GND GND GND VCCIB3 NC IO06RSB0 IO08RSB0 IO12RSB0 IO15RSB0 IO19RSB0 IO24RSB0 IO31RSB0 IO39RSB0 IO48RSB0 IO54RSB0 IO58RSB0
484-Pin FBGA Pin Number B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 A3P1000 Function IO63RSB0 IO66RSB0 IO68RSB0 IO70RSB0 NC NC VCCIB1 GND VCCIB3 IO220PDB3 NC NC GND IO10RSB0 IO14RSB0 VCC VCC IO30RSB0 IO37RSB0 IO43RSB0 NC VCC VCC NC NC GND NC NC NC VCCIB1 IO219PDB3 IO220NDB3 NC GND GAA0/IO00RSB0 GAA1/IO01RSB0
484-Pin FBGA Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 A3P1000 Function GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND NC NC NC IO219NDB3 NC GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 GND
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484-Pin FBGA Pin Number E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3P1000 Function NC IO84PDB1 NC IO215PDB3 IO215NDB3 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO82PPB1 NC IO84NDB1 IO214NDB3 IO214PDB3 NC IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0
484-Pin FBGA Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 A3P1000 Function IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NPB1 IO85PDB1 IO85NDB1 NC NC NC VCC IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 VCC NC NC IO212NDB3 IO212PDB3 NC IO217NDB3
484-Pin FBGA Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3P1000 Function IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 NC IO89PDB1 IO89NDB1 IO211PDB3 IO211NDB3 NC IO210PPB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1
Revision 9
3- 77
484-Pin FBGA Pin Number K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 A3P1000 Function IO88NDB1 IO94NPB1 IO98NDB1 IO98PDB1 NC IO200PDB3 IO210NPB3 GFB0/IO208NPB3 GFA0/IO207NDB3 GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 IO97PDB1 IO97NDB1 IO99NPB1 NC IO200NDB3 IO206NDB3 GFA2/IO206PDB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND
484-Pin FBGA Pin Number M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 A3P1000 Function GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PPB1 IO101PPB1 IO99PPB1 NC IO201NDB3 IO201PDB3 NC GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 NC IO101NPB1 IO103PDB1 NC IO199PDB3
484-Pin FBGA Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 A3P1000 Function IO199NDB3 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 NC IO104PDB1 IO103NDB1 NC IO197PPB3 VCC IO197NPB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1
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484-Pin FBGA Pin Number R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 A3P1000 Function GDB1/IO112PPB1 GDC1/IO111PDB1 IO107NDB1 VCC IO104NDB1 IO105PDB1 IO198PDB3 IO198NDB3 NC IO194PPB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 NC IO108PDB1 IO105NDB1 IO195PDB3 IO195NDB3 IO194NPB3 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2
484-Pin FBGA Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3P1000 Function IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 NC IO108NDB1 IO109PDB1 NC NC GND GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2 IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND NC IO109NDB1
484-Pin FBGA Pin Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 A3P1000 Function NC IO191PDB3 NC GND IO183RSB2 GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND NC NC NC VCCIB3 IO191NDB3 NC IO182RSB2 GND IO177RSB2 IO174RSB2 VCC VCC IO154RSB2 IO148RSB2 IO140RSB2 NC VCC
Revision 9
3- 79
484-Pin FBGA Pin Number Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 A3P1000 Function VCC NC NC GND NC NC NC VCCIB1 GND VCCIB3 NC IO181RSB2 IO178RSB2 IO175RSB2 IO169RSB2 IO166RSB2 IO160RSB2 IO152RSB2 IO146RSB2 IO139RSB2 IO133RSB2 NC NC IO122RSB2 IO119RSB2 IO117RSB2 NC NC VCCIB1 GND GND GND VCCIB2 IO180RSB2 IO176RSB2 IO173RSB2
484-Pin FBGA Pin Number AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 A3P1000 Function IO167RSB2 IO162RSB2 IO156RSB2 IO150RSB2 IO145RSB2 IO144RSB2 IO132RSB2 IO127RSB2 IO126RSB2 IO123RSB2 IO121RSB2 IO118RSB2 NC VCCIB2 GND GND
3- 80
R e visio n 9
4 Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the ProASIC3 datasheet. Revision July 2010 Changes The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "ProASIC3 Device Status" table on page III indicates the status for each device in the device family. Page N/A
Revision 9 (Oct 2009) The CS121 package was added to Table 1 ProASIC3 Product Family, the "I/Os Per Package 1" table, Table 2 ProASIC3 FPGAs Package Sizes Dimensions, Product Brief v1.3 "ProASIC3 Ordering Information", and the "Temperature Grade Offerings" table. "ProASIC3 Ordering Information" was revised to include the fact that some RoHS compliant packages are halogen-free. Packaging v1.5 The "121-Pin CSP" figure and pin table for A3P060 are new.
I IV
III 3-15 N/A 1-7 1-7 N/A
Revision 8 (Aug 2009) All references to M7 devices (CoreMP7) and speed grade F were removed from this document. Product Brief v1.2 Table 1-1 I/O Standards Supported is new. The "I/Os with Advanced I/O Standards" section was revised to add definitions of hot-swap and cold-sparing. DC and Switching 3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the Characteristics v1.4 datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V LVCMOS data. IIL and IIH input leakage current information was added to all "Minimum and Maximum DC Input and Output Levels" tables. F was removed from the datasheet. The speed grade is no longer supported. The notes in Table 2-2 Recommended Operating
1
N/A N/A 2-2 2-3 2-6 2-100
Conditions 1,2
were updated.
Table 2-4 Overshoot and Undershoot Limits was updated. Table 2-6 Temperature and Voltage Derating Factors for Timing Delays was updated. In Table 2-116 RAM4K9, the following specifications were removed: tWRO tCCKH In Table 2-117 RAM512X18, the following specifications were removed: tWRO tCCKH In the title of Table 2-74 1.8 V LVCMOS High Slew, VCCI had a typo. It was changed from 3.0 V to 1.7 V. Revision 7 (Feb 2009) The "Advanced I/O" section was revised to add a bullet regarding wide range power supply voltage support. Product Brief v1.1 Table 1 ProASIC3 Product Family was updated to include a value for typical equivalent macrocells for A3P250.
2-101
2-58 I
Revision 9
4 -1
Revision Revision 7 (contd)
Changes The QN48 package was added to the following tables: "ProASIC3 Product Family" "I/Os Per Package 1" "ProASIC3 FPGAs Package Sizes Dimensions" "Temperature Grade Offerings" The number of singled-ended I/Os for QN68 was added to the "I/Os Per Package 1" table. The "Wide Range I/O Support" section is new.
Page N/A
1-7 3-1 3-5 2-5
Revision 6 (Dec 2008) The "48-Pin QFN" section is new. Packaging v1.4 The "68-Pin QFN" pin table for A3P030 is new.
Revision 5 (Aug 2008) TJ, Maximum Junction Temperature, was changed to 100 from 110 in the DC and Switching "Thermal Characteristics" section and EQ 2. The calculated result of Maximum Power Allowed has thus changed to 1.463 W from 1.951 W. Characteristics v1.3 Values for the A3P015 device were added to Table 2-7 Quiescent Supply Current Characteristics.
2-6
Values for the A3P015 device were added to Table 2-14 Different Components 2-10, 2-11 Contributing to Dynamic Power Consumption in ProASIC3 Devices. PAC14 was removed. Table 2-15 Different Components Contributing to the Static Power Consumption in ProASIC3 Devices is new. The "PLL ContributionPPLL" section was updated to change the PPLL formula from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT. Both fall and rise values were included for tDDRISUD and tDDRIHD in Table 2-102 Input DDR Propagation Delays. Table 2-107 A3P015 Global Resource is new. The typical value for Delay Increments in Programmable Delay Blocks was changed from 160 to 200 in Table 2-115 ProASIC3 CCC/PLL Specification. Revision 4 (Jun 2008) Table note references were added to Table 2-2 Recommended Operating 1,2 DC and Switching Conditions , and the order of the table notes was changed. Characteristics v1.2 The title for Table 2-4 Overshoot and Undershoot Limits 1 was modified to remove "as measured on quiet I/Os." Table note 1 was revised to remove "estimated SSO density over cycles." Table note 2 was revised to remove "refers only to overshoot/undershoot limits for simultaneous switching I/Os." The "Power per I/O Pin" section was updated to include 3 additional tables pertaining to input buffer power and output buffer power. Table 2-29 I/O Output Buffer Maximum Resistances 1 was revised to include values for 3.3 V PCI/PCI-X. Table 2-90 LVDS Minimum and Maximum DC Input and Output Levels was updated. Revision 3 (Jun 2008) Pin numbers were added to the "68-Pin QFN" package diagram. Note 2 was added below the diagram. Packaging v1.3 The "132-Pin QFN" package diagram was updated to include D1 to D4. In addition, note 1 was changed from top view to bottom view, and note 2 is new. 2-3 2-13 2-80 2-88 2-92 2-2
2-6 2-27 2-68 3-3
3-6
4-2
R e vi s i o n 9
Revision
Changes
Page N/A
Revision 2 (Feb 2008) This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering Product Brief v1.0 information, and temperature and speed grade offerings. The second section is a device family overview. This document was updated to include A3P015 device information. QN68 is a new package that was added because it is offered in the A3P015. The following sections were updated: "Features and Benefits" "ProASIC3 Ordering Information" "Temperature Grade Offerings" "ProASIC3 Product Family" "A3P015 and A3P030" note "Introduction and Overview" The "ProASIC3 FPGAs Package Sizes Dimensions" table is new. In the "ProASIC3 Ordering Information", the QN package measurements were updated to include both 0.4 mm and 0.5 mm. In the "General Description" section, the number of I/Os was updated from 288 to 300. Packaging v1.2 The "68-Pin QFN" section is new. Conditions 1,2,
N/A
II III 1-1 3-3 2-2
Revision 1 (Feb 2008) In Table 2-2 Recommended Operating TJ was listed in the symbol column and was incorrect. It was corrected and changed to TA. DC and Switching Characteristics v1.1 In Table 2-3 Flash Programming Limits Retention, Storage and Operating Temperature1, Maximum Operating Junction Temperature was changed from 110C to 100C for both commercial and industrial grades. The "PLL Behavior at Brownout Condition" section is new. In the "PLL ContributionPPLL" section, the following was deleted: FCLKIN is the input clock frequency. In Table 2-21 Summary of Maximum and Minimum DC Input Levels, the note was incorrect. It previously said TJ and it was corrected and changed to TA. In Table 2-115 ProASIC3 CCC/PLL Specification, the SCLK parameter and note 1 are new. Table 2-125 JTAG 1532 was populated with the parameter data, which was not in the previous version of the document. Packaging v1.1 In the "100-Pin VQFP" A3P030 pin table, the function of pin 63 was incorrect and changed from IO39RSB0 to GDB0/IO38RSB0.
2-2
2-3 2-13
2-21 2-92 2-112 3-19 N/A i, ii, iii, iii, iv
Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the handbook format, Actel has restarted the version numbers. v2.2 (July 2007) The M7 and M1 device part numbers have been updated in Table 1 ProASIC3 Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix". The words "ambient temperature" were added to the temperature range in the "Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings", and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv
Revision 9
4 -3
Revision v2.2 (continued) v2.1 (May 2007)
Changes The TJ parameter in Table 3-2 Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 46 were added. In the "Clock Conditioning Circuit (CCC) and PLL" section, the Wide Input Frequency Range (1.5 MHz to 200 MHz) was changed to (1.5 MHz to 350 MHz). The "Clock Conditioning Circuit (CCC) and PLL" section was updated. In the "I/Os Per Package" section, the A3P030, A3P060, A3P125, ACP250, and A3P600 device I/Os were updated. Table 3-5 Package Thermal Resistivities was updated with A3P1000 information. The note below the table is also new.
Page 3-2 i i ii 3-5 ii N/A 2-15 2-15 2-29 2-18 2-21 2-25 2-25 2-28 2-29 2-34 2-64 2-40
v2.0 (April 2007)
In the "Packaging Tables", Ambient was deleted. The timing characteristics tables were updated. The "PLL Macro" section was updated to add information on the VCO and PLL outputs during power-up. The "PLL Macro" section was updated to include power-up information. Table 2-11 ProASIC3 CCC/PLL Specification was updated. Figure 2-19 Peak-to-Peak Jitter Definition is new. The "SRAM and FIFO" section was updated with operation and timing requirement information. The "RESET" section was updated with read and write information. The "RESET" section was updated with read and write information. The "Introduction" in the "Advanced I/Os" section was updated to include information on input and output buffers being disabled. PCI-X 3.3 V was added to Table 2-11 VCCI Voltages and Compatible Standards. In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were updated for levels 3 and 4. Table 2-43 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was updated. Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7 to 5 x 52.7. The "VCCPLF PLL Supply Voltage" section was updated. The "VPUMP Programming Supply Voltage" section was updated. The "GL Globals" section was updated to include information about direct input into quadrant clocks. VJTAG was deleted from the "TCK Test Clock" section. In Table 2-22 Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to TCK in note 2. Note 3 was also updated. Ambient was deleted from Table 3-2 Recommended Operating Conditions. VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45". Note 3 is new in Table 3-4 Overshoot and Undershoot Limits (as measured on quiet I/Os)1.
2-50 2-50 2-51 2-51 2-51 3-2 3-2
4-4
R e vi s i o n 9
Revision v2.0 (continued)
Changes In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951. Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was updated. Table 3-5 Package Thermal Resistivities was updated.
Page 3-5 3-6 3-5
Table 3-14 Summary of Maximum and Minimum DC Input and Output Levels 3-17 to 3Applicable to Commercial and Industrial ConditionsSoftware Default Settings 17 (Advanced) and Table 3-17 Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were updated. Table 3-20 Summary of I/O Timing CharacteristicsSoftware Default Settings (Advanced) and Table 3-21 Summary of I/O Timing CharacteristicsSoftware Default Settings (Standard Plus) were updated. Table 3-11 Different Components Contributing Consumption in ProASIC3 Devices was updated. to Dynamic Power 3-20 to 3-20 3-9 3-22 to 3-22 3-18 3-24 to 3-26 3-27 3-82 to 3-84 3-96 iv N/A 4-2 4-4 4-6 4-8 4-11 ii N/A ii ii iii
Table 3-24 I/O Output Buffer Maximum Resistances1 (Advanced) and Table 325 I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated. Table 3-17 Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions was updated. Table 3-28 I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 I/O Short Currents IOSH/IOSL (Standard Plus) were updated. The note in Table 3-32 I/O Input Rise Time, Fall Time, and Related I/O Reliability was updated. Figure 3-33 Write Access After Write onto Same Address, Figure 3-34 Read Access After Write onto Same Address, and Figure 3-35 Write Access After Read onto Same Address are new. Figure 3-43 Timing Diagram was updated. Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". Notes were added to the package diagrams identifying if they were top or bottom view. The A3P030 "132-Pin QFN" table is new. The A3P060 "132-Pin QFN" table is new. The A3P125 "132-Pin QFN" table is new. The A3P250 "132-Pin QFN" table is new. The A3P030 "100-Pin VQFP" table is new. Advance v0.7 (January 2007) Advance v0.6 (April 2006) In the "I/Os Per Package" table, the I/O numbers were added for A3P060, A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77. The term flow-through was changed to pass-through. Table 1 was updated to include the QN132. The "I/Os Per Package" table was updated with the QN132. The footnotes were also updated. The A3P400-FG144 I/O count was updated. "Automotive ProASIC3 Ordering Information" was updated with the QN132.
Revision 9
4 -5
Revision Advance v0.6 (continued)
Changes "Temperature Grade Offerings" was updated with the QN132. B-LVDS and M-LDVS are new I/O standards added to the datasheet. The term flow-through was changed to pass-through. Figure 2-7 Efficient Long-Line Resources was updated. The footnotes in Figure 2-15 Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT were updated. The Delay Increments in the Programmable Delay Blocks specification in Figure 2-24 ProASIC3E CCC Options. The "SRAM and FIFO" section was updated. The "RESET" section was updated. The "WCLK and RCLK" section was updated. The "RESET" section was updated. The "RESET" section was updated. The "Introduction" of the "Advanced I/Os" section was updated. The "I/O Banks" section is new. This section explains the following types of I/Os: Advanced Standard+ Standard Table 2-12 Automotive ProASIC3 Bank Types Definition and Differences is new. This table describes the standards listed above. PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 211 VCCI Voltages and Compatible Standards Table 2-13 ProASIC3 I/O Features was updated. The "Double Data Rate (DDR) Support" section was updated to include information concerning implementation of the feature. The "Electrostatic Discharge (ESD) Protection" section was updated to include testing information. Level 3 and 4 descriptions were updated in Table 2-43 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices. The notes in Table 2-43 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices were updated. The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout" section is new. A footnote was added to Table 2-14 Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in Automotive ProASIC3 Devices (maximum drive strength and high slew selected). Table 2-18 Automotive ProASIC3 I/O Attributes vs. I/O Standard Applications Table 2-50 ProASIC3 Output Drive (OUT_DRIVE) for Standard I/O Bank Type (A3P030 device) Table 2-51 ProASIC3 Output Drive for Standard+ I/O Bank Type was updated. Table 2-54 ProASIC3 Output Drive for Advanced I/O Bank Type was updated.
Page iii N/A N/A 2-7 2-16 2-24 2-21 2-25 2-25 2-25 2-27 2-28 2-29
2-29 2-30 2-32 2-35 2-64 2-64 2-41 2-30
2-45 2-83 2-84 2-84
4-6
R e vi s i o n 9
Revision Advance v0.6 (continued)
Changes The "x" was updated in the "User I/O Naming Convention" section. The "VCC Core Supply Voltage" pin description was updated. The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information concerning leaving the pin unconnected. The "VJTAG JTAG Supply Voltage" pin description was updated. The "VPUMP Programming Supply Voltage" pin description was updated to include information on what happens when the pin is tied to ground. The "I/O User Input/Output" pin description was updated to include information on what happens when the pin is unused. The "JTAG Pins" section was updated to include information on what happens when the pin is unused. The "Programming" section was updated to include information concerning serialization. The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information. "DC and Switching Characteristics" chapter was updated with new information. The A3P060 "100-Pin VQFP" pin table was updated. The A3P125 "100-Pin VQFP" pin table was updated. The A3P060 "144-Pin TQFP" pin table was updated. The A3P125 "144-Pin TQFP" pin table was updated. The A3P125 "208-Pin PQFP" pin table was updated. The A3P400 "208-Pin PQFP" pin table was updated. The A3P060 "144-Pin FBGA" pin table was updated. The A3P125 "144-Pin FBGA" pin table is new. The A3P400 "144-Pin FBGA" is new. The A3P400 "256-Pin FBGA" was updated. The A3P1000 "256-Pin FBGA" was updated. The A3P400 "484-Pin FBGA" was updated. The A3P1000 "484-Pin FBGA" was updated. The A3P250 "100-Pin VQFP*" pin table was updated. The A3P250 "208-Pin PQFP*" pin table was updated. The A3P1000 "208-Pin PQFP*" pin table was updated. The A3P250 "144-Pin FBGA*" pin table was updated. The A3P1000 "144-Pin FBGA*" pin table was updated. The A3P250 "256-Pin FBGA*" pin table was updated. The A3P1000 "256-Pin FBGA*" pin table was updated. The A3P1000 "484-Pin FBGA*" pin table was updated.
Page 2-48 2-50 2-50 2-50 2-50 2-50 2-51 2-53 2-54 3-1 4-13 4-13 4-16 4-18 4-21 4-25 4-32 4-34 4-38 4-48 4-54 4-58 4-68 4-14 4-23 4-29 4-36 4-32 4-45 4-54 4-68
Revision 9
4 -7
Revision Advance v0.5 (November 2005)
Changes The "I/Os Per Package" table was updated for the following devices and packages: Device A3P250/M7ACP250 A3P250/M7ACP250 A3P1000 Package VQ100 FG144 FG256
Page ii
Advance v0.4
M7 device information is new. The I/O counts in the "I/Os Per Package" table were updated.
N/A ii ii N/A 2-16 2-24 2-15 2-29 2-28 2-30 2-33 2-34 2-35 2-64 2-97 2-50 2-51 2-53 3-6 3-6 3-93-8 3-20 3-27 3-31 to 373 3-85 to 3-90 3-97
Advance v0.3
The "I/Os Per Package" table was updated. M7 device information is new. Table 2-4 ProASIC3 Globals/Spines/Rows by Device was updated to include the number or rows in each top or bottom spine. EXTFB was removed from Figure 2-24 ProASIC3E CCC Options. The "PLL Macro" section was updated. EXTFB information was removed from this section. The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 211 ProASIC3 CCC/PLL Specification EXTFB was removed from Figure 2-27 CCC/PLL Macro. Table 2-13 ProASIC3 I/O Features was updated. The "Hot-Swap Support" section was updated. The "Cold-Sparing Support" section was updated. "Electrostatic Discharge (ESD) Protection" section was updated. The LVPECL specification in Table 2-43 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices was updated. In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was changed to VCCIB1. The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section. The "JTAG Pins" section was updated. "128-Bit AES Decryption" section was updated to include M7 device information. Table 3-6 was updated. Table 3-7 was updated. In Table 3-11, PAC4 was updated. Table 3-20 was updated. The note in Table 3-32 was updated. All Timing Characteristics tables were updated from LVTTL to Register Delays The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. FTCKMAX was updated in Table 3-110.
4-8
R e vi s i o n 9
Revision Advance v0.2 Figure 2-11 was updated.
Changes
Page 2-9 2-9 2-9 2-15 2-28 2-19 2-25 2-25 2-27 2-30 2-31 2-34 2-64 2-45 2-51 2-48 3-6 3-10 3-33,3-32 4-14 4-23 4-29 4-36 4-32 4-45 4-54 4-68
The "Clock Resources (VersaNets)" section was updated. The "VersaNet Global Networks and Spine Access" section was updated. The "PLL Macro" section was updated. Figure 2-27 was updated. Figure 2-20 was updated. Table 2-5 was updated. Table 2-6 was updated. The "FIFO Flag Usage Considerations" section was updated. Table 2-13 was updated. Figure 2-24 was updated. The "Cold-Sparing Support" section is new. Table 2-43 was updated. Table 2-18 was updated. Pin descriptions in the "JTAG Pins" section were updated. The "User I/O Naming Convention" section was updated. Table 3-7 was updated. The "Methodology" section was updated. Table 3-40 and Table 3-39 were updated. The A3P250 "100-Pin VQFP*" pin table was updated. The A3P250 "208-Pin PQFP*" pin table was updated. The A3P1000 "208-Pin PQFP*" pin table was updated. The A3P250 "144-Pin FBGA*" pin table was updated. The A3P1000 "144-Pin FBGA*" pin table was updated. The A3P250 "256-Pin FBGA*" pin table was updated. The A3P1000 "256-Pin FBGA*" pin table was updated. The A3P1000 "484-Pin FBGA*" pin table was updated.
Revision 9
4 -9
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3 Device Status" table on page III, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy

The Actel products described in this advance status document may not have completed Actels qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actels Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actels products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
4- 10
R e visio n 9
Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation
2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600
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Revision 9

ProASIC3 Flash Family FPGAs

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

Clock Conditioning Circuit (CCC) and PLL

High-Performance Routing Hierarchy

ARM Processor Support in ProASIC3 FPGAs

M1 ProASIC3 DevicesARMCortex-M1 Soft Processor Available with or without Debug

Table 1 ProASIC3 Product Family

Supported only by A3P015 and A3P030 devices.

ProASIC3 Flash Family FPGAs

I/Os Per Package 1

19 13 34 24 38 151 97 178 194

154 97 177 235

ProASIC3 Flash Family FPGAs

ProASIC3 Ordering Information

ProASIC3 Device Status

ProASIC3 Flash Family FPGAs

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

A3P015 and A3P030

ProASIC3 Flash Family FPGAs

ProASIC3 DC and Switching Characteristics

Package Pin Assignments

1 ProASIC3 Device Family Overview

ProASIC3 Flash Family FPGAs

Advanced Flash Technology

CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*

ISP AES Decryption*

User Nonvolatile FlashROM Bank 1

The A3P015 and A3P030 do not support PLL or SRAM.

ProASIC3 Device Family Overview

CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block

ISP AES Decryption

User Nonvolatile FlashROM Bank 2

D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF

User Nonvolatile FlashROM

SRAM and FIFO

PLL and CCC

Additional CCC specifications:

ProASIC3 Flash Family FPGAs

I/Os with Advanced I/O Standards

Wide Range I/O Support

2 ProASIC3 DC and Switching Characteristics

Storage temperature Junction temperature

LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes:

Programmin g Cycles 500 500

PLL Behavior at Brownout Condition

ProASIC3 DC and Switching Characteristics

Internal Power-Up Activation Sequence

Region 1: I/O Buffers are OFF

Region 1: I/O buffers are OFF

I/O State as a Function of VCCI and VCC Voltage Levels

ProASIC3 Flash Family FPGAs

Package Thermal Characteristics

ProASIC3 DC and Switching Characteristics

Temperature and Voltage Derating Factors

Calculating Power Dissipation

Power per I/O Pin

Static Power PDC2 (mW) 1 2.26 5.72

3.3 3.3 2.5 1.8 1.5 3.3 3.3 2.5 3.3

Static Power PDC2 (mW) 1