IT09 406: Microprocessor Based Design

Lecture 5,

THE HARDWARE STRUCTURE OF 8086

Differences between 8086 and 8088

8088 CPU pin diagram

8086 CPU pin diagram

Modes of 8086

Minimum mode when used in uniprocessor configuration Maximum mode when used in multiprocessor configuration

8086 pins in the minimum mode

De-multiplexing the Address/Data Bus The 8086 chip is a 40 pin DIP The 8086 has 16 data lines and 20 address lines Data and address lines are multiplexed i.e., the lower address lines are carried by the data lines in the beginning The action of separating address and data is called de-multiplexing

Block diagram of the de-multiplexed address/data bus

Latching the address lines

The lower address lines are to be latched, and the use of the latch IC 74LS373 is sought The ALE (Address Latch Enable) outputted by the processor is used as a clock for the latch

Pin diagram of the octal latch IC 74LS373

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The buffered and de-multiplexed address bus

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Data bus and control pins

The data bus is bidirectional It may sometimes not have sufficient driving capacity to provide current Hence it is usually buffered by a tri-state bidirectional chip 74LS 245 The control signals for read and write are unidirectional For buffering the control signal, the IC 74LS244 is used, which is a unidirectional tri-state buffer

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Buffered data bus and control pins

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Pin diagram of the octal tri-state bidirectional buffer 74LS245

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Memory and I/O

The 8086 generates control signals for reading and writing, but does not distinguish between memory and I/O operations For this, additional logic is used

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Generation of memory and I/O read/write signals

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Clock Generation
One cycle of the clock is called a T state, and all timings and delays are multiples of this T state duration There is no circuitry inside the processor for this, and so an external clock generator IC is used Intel has provided the clock generator IC 8284A which is compatible with 8086/8088

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Pin configuration of the clock generator 8284A

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Clock generator IC

The clock generator IC performs a few more functions than just supplying the clock frequency to the processor The crystal is connected between the X1 and X2 pins. The READY output pin of 8284A is connected to the READY input pin of 8086. This pin is used to overcome the timing inconsistencies that are possible when a slow peripheral/memory device is connected to the processor

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Connections of the clock generator IC to 8086

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Reset

An active low reset signal from the control bus is sent to the 8284 which synchronizes it with the trailing edge of the clock Most systems include a line that goes to all system components and is possibly controlled by an operator push button (or just after power on), which causes a low signal on the RESET pin of the clock generator
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Reset Timings and reset vector

The RESET line of 8086 must remain high for at least 4 clock periods The 8086 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH A high on the RESET pin of the processor causes all system components to be reset, and inside it, the instruction queue, PSW, DS, SS, ES and IP are cleared CS gets a value of FFFFH and with IP = 0000, the first instruction will be executed from the 22 location FFFF0H

Power on reset circuit

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Charging of the capacitor and generation of reset pulse

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The generation of the reset pulse using a Schmitt trigger (inside the 8284 IC)

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Meeting the reset pulse specifications

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Machine/Bus cycles

Any read or write cycle is called a bus cycle. For 8086, a bus cycle takes four T states, where one T state is defined as the period of the clock If the clock frequency is 10 MHz, one T state = 0.1 usecs or 100 nsecs A bus cycle is also called a machine cycle During a machine cycle, a specific operation say, reading or writing is accomplished.
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Typical machine cycles

Memory Read Memory Write I / O Read I / O Write Interrupt Acknowledge

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Read Machine Cycle

Place on the address bus, the address of the location whose content is to be read. This action is performed by the processor. Assert the read control signal which is part of the control bus. Wait until the content of the addressed location appears on the data bus. Transfer the data on the data bus to the processor. De-activate the read control signal. The read operation is over and the address on the address bus is not relevant anymore.

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Read machine cycle timing diagram

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If the access time for a device is longer than that permitted by 8086 timing, extra clock cycles termed wait states have to be inserted in the bus cycle Sample the READY line at the end of T2. If the READY signal is found low, an extra T state is inserted into the bus cycle, between T 3 and T4, which is designated as TW All signals on the bus remain unchanged during this extra wait state (TW) In the middle of TW, once again the READY signal is checked. If it is at logic 1, the next T state will be T4 otherwise, another wait state 31 TW will be inserted

Wait Cycles

Sampling the READY signal and inserting wait states

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Insertion of a wait state generator to add wait states

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Example 6.1

What is the duration of the bus-cycle in an 8086 based microcomputer, if the clock frequency is 12 MHz and three wait states are inserted?

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Example 6.1 Solution

The period of a 12 MHz microprocessor is T = 1/f = 83 ns. Thus, the duration of the bus-cycle, without any wait-states is given by: Tbus-cycles = 4* T = 4* 83 ns = 332 ns Duration of the wait-states is, T w = 3* T = 249 ns So the extended bus-cycle T bus-cycle+ Tw = 332 + 249 = 581 ns

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Simplified write machine cycle timing

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Other Processor Activities

Interrupt Lines It has an INTR line and an NMI (Nonmaskable Interrupt) line for external interrupts

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DIRECT MEMORY ACCESS(DMA)

This is the method of transferring data between the memory and a peripheral without involving the processor During the time of DMA, the buses of the processor are tri-stated The pins HOLD and HLDA are devoted to DMA operation

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Concept of direct memory access

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Timing of the HOLD and HLDA signals

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TEST and BHE pins

Both these pins are active low The TEST pin is used to synchronize the activities of the 8086 with an arithmetic coprocessor 8087(refer Chapter 13) The BHE (Bus High Enable) is used to enable high bank of memory (refer Chapter 7)

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Halt Machine Cycle

Another machine cycle is the HALT machine cycle. The processor enters this machine cycle in response to a HLT (Halt) instruction To bring the processor out of this state, an interrupt or a RESET signal must be issued

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8086 in the minimum mode configuration

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Maximum Mode

In this mode, which is used for multi processing ,the processor needs a lot more pins Some pin designations are changed The pins that are lost are retrieved by generating them by using a bus controller IC 8288

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Maximum mode pins of 8086

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Control Signals Generated by the Bus Controller

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Pin diagram of the bus controller IC 8288

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Connection between the 8086 and 8288

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REQUEST/GRANT pins

These are two bi-directional, active low pins, on which other processors in a multi processing system can place their bus requests

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Queue Status pins QS0, QS1

These pins are inputs to the 8086 It becomes useful when an arithmetic coprocessor is the second processor in the system Since the co-processor is expected to work in step with 8086, the co-processor can interrogate the 8086 about its queue status, on these lines, and decide its course of action accordingly More details are given in Chapter 13
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The active low LOCK signal can be used to prevent other bus masters from acquiring the bus of the 8086 For example, if the 8086 wants to retain the bus until a string transfer is completed fully, it can use the instruction (say) LOCK REP MOVSB So the processor does not have to relinquish the bus after one bus cycle, as may be the case if the LOCK prefix is not used Instead, the bus is retained until the complete string operation is over

The LOCK signal

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Maximum mode configuration of the 8086

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Instruction Cycle

The time taken by the processor to execute an instruction is called an instruction cycle, and it is specified in terms of the number of clock cycles needed to do it The operation of the CPU is just fetch, decode and execute Once an instruction is fetched and is ready for execution, it will be decoded immediately, and after that, execution can be set in motion
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FETCH EXECUTE CYCLE

The fetch-execute cycle can be decomposed into 6 stages: FI Fetch instruction DI Decode instruction CO Calculate operand addresses FO Fetch operands EI Execute instruction WO Write or store result in memory

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The time for all these activities should constitute the instruction cycle Because of pre-fetching, the fetch time is usually not a part of the instruction cycle But calculation of the effective address does take time

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Execution Times of Some Sample Instructions

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Table 6.4 | Number of Cycles Expended in Calculating the Effective Address

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Delay Loops

MOV CX, 100 HERE: LOOP HERE

;4 cycles ;17 / 5 cycles

Delay cycles: 4 + (17 100) 12 = 1692 cycles For a system with 12 MHz, one clock period is 0.083 usecs Total delay = 140 usecs
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Example 6.2

Write a program to create a delay of 1 msec.

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Example 6.2 Solution

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Example 6.2 Calculation

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Example 6.3

Write a delay loop with appropriate values of the count to get a delay of 1 second

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Example 6.3 Solution

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Example 6.3 Calculation

The inner loop is that which corresponds to the LOOP instruction. It repeats N2 times, which is the count in the CX register The LOOP instruction plus a few overheads (caused by the instructions MOV CX, N2 and DEC BX) repeat N1 times, which is the count of the outer loop

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Calculation Contd.
Thus a large delay can be obtained. To calculate N1 and N2, the best way would be to make N2 = FFFFH and then get a corresponding value for N1 For a total delay of 1 second, Total cycles = N1 [17 N2 + 4 + 2 + 16] = N1 [22 + 17 N2] If N2 = FFFFH i.e., 65,535 the calculation comes to 1114117 N1 .083 = 1000 000 usecs 92471.711 N1 = 1000000 N1 = 10.81 Thus, a value of 11 (0BH) can be used in the place of N1 in the program

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Why Delay Loops?

Generating delays in this manner is called software delay. One can generate a square wave using a software delay Delay loops can also be used to generate events spaced intime

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Example 6.4

Generate a square wave of frequency 1 KHz at the output port with address 78H

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Example 6.4 Solution

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