Designing and Implementing Synchronization Circuits for Spread Spectrum Communications in FPGAs

John C. Porcello Senior Research Engineer Georgia Tech Research Institute (GTRI) 7220 Richardson Road Smyrna, GA 30080 John.Porcello@gtri.gatech.edu AbstractCommunications in the aerospace environment is often very challenging. 12These challenges increase with the demand for higher data rates. This paper focuses on design and implementation of synchronization circuits for Direct Sequence Spread Spectrum (DSSS) receivers using Field Programmable Gate Arrays (FPGAs). In aerospace communications, it is the wireless digital communications receiver which bears the burden of synchronization. This includes the task of both acquisition and tracking a transmitted communications signal such that the demodulator can operate properly. Furthermore, the task of EB / N 0 synchronization of wideband or low communications systems is often the most challenging aspect of a communications system design. This paper presents DSSS acquisition and tracking circuits to meet challenging communications system designs, and addresses implementation issues for these circuits in FPGAs. Design and implementation issues for DSSS acquisition and tracking circuits in FPGAs are considered, beginning with a general discussion of design and implementation issues for DSSS synchronization circuits. Important factors that impact synchronization are discussed. This is followed by a specific discussion of high performance acquisition and tracking circuits for challenging communications systems. Design considerations such as acquisition time, tracking accuracy and real-time updating of matched filter coefficients in a dynamic communications environment are discussed. Design data and reference circuits for high performance acquisition and tracking circuits are provided to support synchronization design that meets performance requirements. This is followed by a discussion of implementation considerations for high performance acquisition and tracking circuits in FPGAs. Finally, an example design and implementation is provided for a DSSS synchronization circuit using Xilinx Virtex-6 FPGAs. The example design demonstrates the design and implementation techniques discussed in the paper.

TABLE OF CONTENTS 1. INTRODUCTION AND SCOPE ............................................. 1 2. GENERAL DESIGN CONSIDERATIONS .............................. 2 3. HIGH PERFORMANCE SYNCHRONIZATION CIRCUITS .... 5 4. IMPLEMENTATION CONSIDERATIONS IN FPGAS ........... 8 5. EXAMPLE DESIGN ............................................................ 8 6. CONCLUSIONS .................................................................. 9 REFERENCES...................................................................... 10 BIOGRAPHY ....................................................................... 10

1. INTRODUCTION AND SCOPE

In wireless digital communications, it is the digital communications receiver which must perform synchronization in order for the communications system to operate properly. Synchronization generally refers to a two step process of acquisition of some parameters (frequency, timing, phase) followed by tracking the parameter with sufficient accuracy such that the demodulator [1] inside the receiver can demodulate transmitted symbols at or below a specified Symbol Error Rate (SER). Direct Sequence Spread Spectrum (DSSS) communications typically applies a Pseudonoise (PN) spreading code to some form of data modulation such as Phase Shift Keying (PSK), prior to transmission. The DSSS Receiver must synchronize to this spreading code prior to synchronizing to the modulation. In this paper, the focus is on synchronizing to the PN code in a DSSS receiver. Specifically, we will look at design issues and circuits that support acquiring and tracking the code phase and frequency of a DSSS transmitted signal. The flexibility of digital communications systems allows for many types and variations of systems to meet a broad range of communications requirements. This flexibility comes with many system design issues. In this paper we will only focus on transmission over an Additive White Gaussian Noise (AWGN) channel, and neglect some system issues such as interference performance and suppression, Doppler spread, Multiple-User Access including power control, fading channels, error correction coding and interleaving, capacity, channel equalization, automatic gain control and other issues related to DSSS communications. These important issues are beyond the scope of this paper. The purpose of this paper is to focus only on synchronization of 1

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the DSSS portion of the communications system. Specifically, we will look at design issues and circuits that support acquiring and tracking the code phase and frequency of a DSSS transmitter in demanding environments such as wideband or low E B / N 0 communications. Synchronization of any type of wireless digital communications system requires an initial timing mark. That is, during the DSSS acquisition process a signal indicates that the PN code is present and initiates the start of despreading the received signal [4] with a stored copy of the PN code. In this paper the initial timing mark is the output of the matched filter. The DSSS synchronization discussions in this paper are related to the use of a known preamble between the transmitter and the receiver and processed by a matched filter. In synchronization terminology, this is referred to as a Data-Aided (DA) synchronization algorithm [1][15]. For the purposes of this paper, the preamble is assumed to be a DSSS signal. It should be noted that the choice of the preamble is based on the communications requirements and the environment in which it operates. In some communications systems, a simple unmodulated preamble or a preamble that has not been spread by a PN code may be the best choice. The designs in this paper are not specific to any digital modulation type. Any digital modulation type may be used with the circuits described in this paper. After the preamble DSSS signal has been synchronized using the techniques presented in this paper, the type of digital modulation used (M-ary PSK, etc.) requires additional synchronization processing in order to perform Carrier and Symbol Timing Recovery [2][3]. Furthermore, this paper takes the viewpoint of solving challenging communications system design issues by pushing the performance burden into a Digital Signal Processing (DSP) domain implemented using Field Programmable Gate Arrays (FPGAs). FPGAs represent the todays high performance DSP engines. The circuits in this paper are based on the ubiquitous Fast Fourier Transform (FFT) [19] to implement fast correlation, large coherent integration gains to improve Signal-to-Noise Ratio (SNR), parallel signal processing, and other functions required of high performance DSSS synchronization circuits. The techniques presented in this paper assume the DSSS communications system requires parallel acquisition techniques for acquiring PN code phase and frequency offset, versus more traditional sequential serial acquisition techniques which take longer periods of time to acquire the PN code and require fewer DSP resources.

unknowns exist between the transmitter and receiver: the clock timing offset, the PN code offset, and a significant frequency offset. The unknown clock offset is due to the fact that the transmitter and receiver clocks are never perfectly synchronized and a timing offset is present. The unknown PN code phase offset is due to the fact that the received and stored PN references in the receiver are not aligned. The unknown frequency offset represents velocity and acceleration between the transmitter and receiver. In the aerospace communications environment, velocity and acceleration between the transmitter and receiver can be expected. The waveform used for the preamble is significant. The preamble waveform will be sent by the transmitter and the receiver will process the waveform through a matched filter. The received waveform will typically have both a time delay and Doppler shift present. The time delay and Doppler shift will decorrelate the received signal from the stored reference in the receiver and the synchronizer must correct for these differences. The aerospace communications systems requirements for Doppler shift and Doppler rate of change (the change in Doppler Shift per time) can be determined via an analysis of the physical dynamics (time, space, position) between the transmitter and receiver. The minimum and maximum relative velocities and accelerations between the transmitter and receiver are determined and a sufficient design margin is added to obtain the minimum and maximum Doppler shift and Doppler rate of change that the synchronizers must acquire and track the preamble waveform. These values also apply to maintaining synchronization during data transmission. In the aerospace environment this can be any platform with relative motion, and an example for low earth orbit (LEO) satellites is described in [20]. In any aerospace communications system, a worst-case Doppler versus time curve based on the flight paths of aerospace vehicles is a useful tool for obtaining these design values. Although a Doppler S-curve is described in [20] for a LEO satellite, it is important to note that Doppler curves for other types of aerospace communications systems may be very different. We are interested in the output of the matched filter for the preamble in the receiver and the amount of decorrelation due to a known value of Doppler shift and unknown PN code offset. The design choice of preamble waveform used for aerospace communications can be aided by calculating the ambiguity function. The ambiguity function expresses matched filter output as a function of time delay and Doppler shift. For the purposes in this paper, we define the ambiguity function as:

2. GENERAL DESIGN CONSIDERATIONS

DSSS Synchronization must successfully acquire and track a known preamble under the conditions that the following 2

X (t D , f D ) =
2

2 * D D

s(t ) s (t t )exp( j 2f t )dt

(1)

s (t ) is the preamble waveform, f D is the Doppler shift and t D is time delay offset.
where The ambiguity function provides insight into the preamble waveform design and selection. The ambiguity function can be seen as an approach to quantify the waveform performance in terms of frequency and code phase offset. For many spread spectrum waveforms, this yields the classic thumbtack response where the waveform energy is spread over Doppler shift and PN code phase (time delay) such that only one single peak is observed at the correct code phase and zero Doppler shift and the remaining output is noise like at a significantly lower magnitude. Serial search acquisition techniques include sequentially searching over the range of possible frequency and PN code phase offsets. The circuits presented in section 3 of this paper perform parallel acquisition and search over all code phases simultaneously. For the discussion in this paper, a real-time communications system [1] is assumed. Additional systems requirements are necessary to design the synchronization circuits. Specifically, the received power level, AWGN power level and noise bandwidth at the receiver input are required. Furthermore, a maximum acquisition time may be specified which may impose a limit on the length of the preamble. These values along with the PN code chip rate determine the Figure of merit, E C / N 0 , for comparing DSSS system performance [1]:

design choice may be driven by several factors such as performance gain, received E B / N 0 , implementation complexity and available system resources to perform synchronization. In this paper our goal is to leverage FPGA signal processing resources to improve synchronization performance. This is achieved at the expense of requiring more FPGA resources, increased design complexity and implementation costs. Figure 1 shows a simplified block diagram of a DSSS transmitter, an AWGN channel and a DSSS receiver. Note that only specific digital blocks of the DSSS transmitter and receiver are shown. RF/Microwave transmitter and receiver chain components are also omitted. A frequency and PN Code phase offset exists between the transmitter and receiver. DSSS synchronization and despreading must be performed first by the DSSS acquisition circuit followed by the DSSS tracking circuit. Once the correct frequency and PN code phase is known, the acquisition circuit can release control of the RXR Direct Digital Synthesizer (DDS) to the tracking circuit. The tracking circuit then maintains the correct frequency and PN code phase for despreading. Many variations of this functionality can be designed. DSSS acquisition circuits must perform two important tasks. First, the acquisition circuit must detect the presence of the preamble. The link budget estimates received power level and the receiver performance analysis estimates noise power level. Matched filter threshold detection is used to declare the preamble waveform present. A longer preamble results in a longer integration time and greater energy available for detection, up to the point where decorrelation due to frequency or timing error reduces the peak output of the matched filter. A variation of the matched filter, called a Segmented Matched Filter (SMF) or Partial Matched Filter (PMF) and non-coherent combining of matched filter sections have been used to reduce the impact of matched filter decorrelation [5]. Circuits that can provide real-time updates to matched-filter coefficients are described in the next section. The second task the acquisition circuit must perform is to determine the frequency and code phase offset accurately enough to begin tracking. Many types of frequency, timing and carrier tracking circuits exist. Each tracking circuit has an acquisition range or bandwidth over which it can lock to a signal. Tracking circuits also have a tracking bandwidth over which an input signal can be tracked. For example, a preamble waveform with a thumbtack ambiguity function can be tracked with an Early-Late Gate (ELG) typically within a range of +/-1 code chip of the PN code. For the Phased-Lock Loop (PLL) and many of the PLL based tracking circuits, the acquisition bandwidth is much less than the tracking bandwidth. The properties of the tracking circuits make the second task of the DSSS acquisition circuit a function of the acquisition 3

EC PR = N 0 N 0 RCHIP

(2)

where E C is the energy per chip, N 0 is the noise power spectral density (equal to noise power divided by the bandwidth), PR is the received power, and RCHIP is the PN code chip rate. When the system is specified in terms of an E B / N 0 , where E B is the energy per bit and the bit rate R BIT , the following relationship can be used to calculate E C / N 0 :

EC E P RCHIP = B RBIT = R N0 N0 N0

(3)

It should be noted here that acquisition and tracking circuits fall into the general class of parameter estimators. That is, an estimate of a parameter such as carrier phase, frequency, or timing is used for synchronization. Many types of estimators exist, with Maximum Likelihood (ML) estimators one of the most common. Whether or not to use an ML estimator versus a legacy estimator or modified legacy estimator, for example, is a design choice. This

range of the PN code tracking circuit and the acquisition bandwidth of the frequency tracking circuit. Once the acquisition circuit has determined the frequency and code phase offsets of the preamble within the acquisition bandwidths of the frequency and code phase tracking circuits respectively, the tracking loops are closed and tracking is initiated. This process can be thought of as a hand off to the tracking circuits, which then control frequency and code phase within the receiver. Symbol Timing Recovery, for our discussion, is performed in the data demodulator. Tracking circuits for frequency, timing, and PN code tracking come in a wide variety [1] [2] [3] [5] [6] [7] [9]

extract information about the data modulation. Two common tracking loops are the Delay-Locked Loop (DLL) for PN code tracking and PLL based loops for frequency tracking. Feedback control loop based tracking circuits, such as PLL based circuits, have a tracking accuracy that is a function of the SNR in the control loop. Given that the signal level usually cannot be increased, the loop bandwidth (and hence noise bandwidth) is reduced to maintain sufficient SNR to maintain tracking accuracy. For example PLLs typically require an SNR above 6 dB to maintain good tracking performance, defined by the probability of a phase error

/2

[9]. SNR estimators can be used to reduce

the loop bandwidth in order to maintain sufficient SNR. However, as less energy becomes available and the loop

Figure 1 Simplified block diagram showing the DSSS Acquisition and DSSS Tracking Circuits. [10] [11] [12] [14] [15] [16] [21] [22]. Many designers have used creative methods to extend the acquisition and tracking performance of synchronization circuits. Traditional and legacy circuits often contrast synchronization and data demodulation circuits in the sense that synchronization circuits generally perform a data wipeoff process and extract parameter information about the carrier while data demodulation circuits perform a carrier wipeoff process and 4 bandwidth is reduced, both the lock-in frequency and the acquisition bandwidth of PLL based circuits will be reduced. DSSS requires synchronization to be performed on the PN code spreading signal prior to synchronizing with the digital modulation used for data transmission. Once the DSSS signal is despread, traditional wireless modem

synchronization techniques have relied on exploiting zerocrossings, signal derivatives and/or spectral lines. It should be noted that suppressed carrier modulation types such as M-ary PSK modulation (QPSK) do not produce a spectral line during modulation. Tracking circuits such as Band-edge filters [2], Costas loops and squaring loops (or Mth power loops) [1][16] are all examples of suppressed carrier tracking loops used to track this class of modulation. It should also be noted here that both DSSS and non-DSSS synchronization circuits may utilize un-modulated sinusoids as preambles to synchronize prior to data transmission. To summarize, the DSSS acquisition circuit performs initial signal detection and estimates the PN code phase offset and frequency offset of the preamble accurately enough such that PN code tracking and frequency tracking circuits can track the preamble. The required estimation accuracy is a function of the acquisition bandwidth of the tracking circuits. The designer has a wide variety of acquisition and tracking circuits to select from based on communication system requirements and available DSP resources for synchronization. Perhaps one of the most important points to note in this section is that, in traditional matched filter receiver design, the receiver DDS may be tuned to correct for frequency based on a fixed set of matched filter coefficients. In low dynamic environments, matched filter decorrelation loss is not significant. In high dynamic environments the designer accepts the performance penalty of matched filter decorrelation loss and may have to trade other parameters in order to close the communications link. The circuits described in the next section, among other things, provide a means to adjust matched filters coefficients in real-time.

requirements dictate a short preamble and low E C / N 0 , the designer needs additional choices for DSSS acquisition and tracking circuits. Discrete Fourier Transform (DFT) techniques will be used to overcome some of these issues. Since the FPGA implementations are based on the Fast Fourier Transform (FFT), we refer to the DFT and FFT synonymously in this paper. A few important properties of the Fast Fourier Transforms (FFTs) are briefly reviewed. For the FFT, the frequency resolution can be described by:

f SAMPLING = f RES N

(4)

where N is the length of an FFT that does not have zeropadded data, f SAMPLING is the sampling frequency of the input data, and f RES is the frequency resolution of a single FFT frequency bin. Signals that straddle FFT frequency bins will contain energy in more than one bin reducing the amplitude in a single bin, described as frequency straddle loss. If the input of a non-windowed FFT receives a signal plus noise and the signal frequency does not straddle FFT output bins, the FFT will deliver an improvement in SNR described by:

SNR IMPROVEMENT = 10 log10 ( N )

(5)

3. HIGH PERFORMANCE SYNCHRONIZATION CIRCUITS

For the purposes of this paper, high performance synchronization circuits refers to synchronization circuits that must acquire and track under one or more of the following conditions: 1) a very short acquisition time, 2) a low E C / N 0 or, 3) aerospace dynamics result in significant Doppler decorrelation in the matched filter such that an acquisition scheme primarily based on tuning the DDS with fixed matched filter coefficients may not meet performance requirements. Given a long enough acquisition time, no Doppler offsets, and enough E C / N 0 , DSSS synchronization can be a relatively easy design problem. However, in aerospace communications this is usually not the case. Often high dynamic environments require fast acquisition of PN code phase and frequency offset during the preamble interval. In the case where challenging communications system 5

The FFT property of providing this coherent integration gain is significant. Given that an initial SNR is presented to the RF and microwave receiver from the antenna, as the signal is processed by the RF and microwave receiver, the finite properties of the components (Noise Figure, etc.) only reduce the SNR. Likewise, wideband systems pay a performance penalty with the increased receiver bandwidth in terms of a higher thermal ( kTB ) noise power. The FFT property of frequency shifting is also important. A time domain signal multiplied by a complex exponential is equivalent to a shift in the frequency domain representation of that signal. Specifically:

x[ n]e j0 n F X e j ( +0 )

(6)

Finally, we should note the effect of zero-padding an FFT. Zero padding in this article refers to adding zeros at the end of the (time-domain) data sent to the input of the FFT. Zeropadding does not improve frequency resolution, but it does improve the capability to select the peak frequency component in the output of the FFT. Zero-padding is also used in fast convolution algorithms to perform linear convolution. The price of zero-padding is an increase in FFT size. However, typically half of the inputs to the FFT

are zero and substantial cancellation can be realized for FPGA implementations of parallel or semi-parallel FFTs. Figure 2 shows a high performance DSSS acquisition circuit using an FFT complex matched filter. The input I and Q signals represent the baseband signals after downconversion by the receiver DDS and low pass filtering as shown in Figure 1. The matched filtering is performed using the FFT of a stored reference of the PN code. The two complex FFTs and complex Inverse FFT (IFFT) are configured to perform fast correlation. It should be noted here that the all three FFTs (the inverse FFT is simply an FFT with conjugated input and a scale factor of 1 / N on the output) can be implemented in FPGAs as parallel or semi-parallel FFTs. Likewise, the complex multipliers can also be implemented in a parallel or semi-parallel manner. The two FFTs shown in Figure 2 which receive timedomain data are zero-padded. The magnitude of the IFFT outputs are calculated. If the magnitude is above a specified threshold level, the threshold detection block declares a signal present. This threshold

operation of the PN code representation in the frequency domain. When the threshold detection block declares a signal present, the IFFT peak magnitude bin location and peak magnitude value is used by the search logic block to calculate the location of the PN code phase offset and perform a fine frequency estimate. The fine frequency estimate is performed by multiplying the time-domain representation of the PN Code by a complex exponential equal to the estimated frequency difference. This can be an iterative procedure if sufficient acquisition time exists to execute processing. Again, the frequency estimate must be within the acquisition bandwidth of the frequency tracking circuit. For low E C / N 0 communications systems this can be a very narrow frequency range due to the narrow loop bandwidth required to maintain sufficient SNR. It should be noted here that the search criteria used by the search logic block in Figure 2 is based on a calibration curve derived from the matched filter length (FFT size), Doppler shift, preamble waveform ambiguity function, and

Figure 2 High performance DSSS acquisition circuit. level is based on the link budget and receiver implementation losses, and also includes matched filter decorrelation loss. If a magnitude is not found above the specified threshold level, the search logic block performs a coarse frequency acquisition search across a subset of IFFT frequency bins (determined by the system specification for maximum Doppler offset and f RES ). The coarse frequency acquisition search is performed using an FFT bin shift 6 acquisition bandwidths of the tracking circuits. It also should also be noted here that the value of angular frequency used for the complex exponential that is multiplied by the PN code in Figure 2 need not be a constant frequency. A Doppler frequency profile can be used that is adjusted for acceleration when the aerospace flight path is known, or it can be calculated in real-time. The circuit in Figure 2 presents a means to adjust matched

filter coefficients in real-time and to use large matched filters in the presence of large Doppler offsets by correcting for Doppler decorrelation loss in real-time. In this scenario, the search logic block would track the current frequency and rate of change and use the PN code reference and the complex exponential in the fine frequency tuning path to generate a corrected frequency domain reference for the complex FFT matched filter. Once the correct PN code phase offset and frequency offset for the preamble has been determined, DSSS acquisition is

If enough FPGA resources are available, the circuit in Figure 2 can be implemented in full parallel to search across all Doppler frequencies and PN code phases simultaneously. This type of full parallel implementation would consist of a single FFT performed on the I and Q input, and then multiple copies of the complex multiplier, stored PN waveform (at various Doppler shifts) and IFFT used to implement the FFT complex matched filter. Figure 3 shows a modified extension of Figure 2, which performs faster

Figure 3 High performance DSSS acquisition and tracking circuit. completed and DSSS tracking can begin. Note that the search logic block would also control the receiver DDS. Depending on the actual system requirements, some modifications to the circuit in Figure 2 may save substantial resources including the use of pre-computed frequency domain versions of the PN code at different Doppler shifts to obtain frequency, as opposed to the FFT, complex exponential multiplier and PN Code generator which make up the fine frequency search chain in Figure 2. acquisition and tracking at the cost of increased FPGA resources, but less than a full parallel implementation. Figure 3 has the addition of one extra matched filter channel. The addition of one channel allows for a reduction in frequency estimation time by allowing for coarse frequency search of twice as many frequencies in the same time interval and faster fine frequency estimation via interpolation of the output magnitudes from each IFFT. This is indicated in Figure 3 via the addition of channel comparator logic. Note that the circuit in Figure 2 could 7

perform the same interpolation, it would simply require additional processing time. Finally, it should be mentioned that the circuit shown in Figure 3 has the capability to send different versions of the PN code to each of the two fine frequency search channels. By holding both search channels at the same frequency, different PN code phases may be correlated to the received PN code. In this configuration, the circuit shown in Figure 3 can perform fast PN code tracking as well as fast frequency tracking.

newest generation of high performance FPGAs and contain the DSP48E1 Slice primitive. This primitive is the high performance embedded multiplier and adder in the FPGA. It contains a 25 bit by 18 bit multiplier followed by a sign extension to a 48 bit wide adder. The multiplier and adder can be accessed individually in the DSP48E1 Slice primitive. Other capabilities exist in the DSP48E1 Slice primitive for use in a wide variety of DSP applications. Reconfigurability, parallel DSP processing, and very high throughput are some of the hallmarks of FPGAs that make them far and away the dominant high performance DSP engine of today. Performance capabilities and technical details of Virtex-6 FPGAs are provided online [23].

4. IMPLEMENTATION CONSIDERATIONS IN FPGAS

In the circuits shown in Figure 2 and Figure 3, the FFTs require the largest amount of FPGA resources. As mentioned in the previous section, zero-padding results in half of the inputs to the FFT being zero. Therefore, substantial cancellation can be realized for FPGA implementations of parallel or semi-parallel FFTs. Actual resources savings is a function of which algorithm is used to implement the FFT. The complex multipliers and memory requirements are the next implementation blocks which will require substantial resources. An FPGA resource budget is typically constructed based on design and implementation choices. Design values such as the number samples per chip for acquisition and tracking loops, data processing paths and decimation ratios to reduce data rates can be derived by communication system simulation. Wideband communications will have larger instantaneous bandwidths which require higher sampling rates. In the previous section, it was indicated that several of the components can be implemented in parallel or semi-parallel. When the FFT size is small enough, the sampling rates are low enough, and there are enough FPGA resources available, parallel and semi-parallel implementations at the sampling frequency are an option. In a parallel or semiparallel configuration, one FFT can be processed in less than the FFT dwell time (a.k.a. FFT overlap processing) and very fast synchronization is an option. As the matched filter size increases, FFT sizes increase beyond available FPGA resources and the FPGA designer must use resources sharing and other FPGA design techniques to fit the algorithm into available resources. This represents a tradeoff in terms of how many sample points are collected per FFT processed (% FFT overlap processing used). It should also be noted that serial FFTs are also an option when FFT processing time is sufficiently small enough to meet acquisition time. Other implementation considerations include the class of FPGAs which will be used and the maximum clock speed for the FPGAs. The illustrative example in the next section was designed to target FPGA implementation in a Xilinx Virtex-6 series FPGA. Xilinx Virtex-6 FPGAs are the 8

5. EXAMPLE DESIGN
A simple example design is provided to illustrate the concepts described in this paper. A DSSS preamble is to be used for synchronizing an air-to-ground communication system. The following parameters are used for this example:

RCHIP = 10 Mcps EC / N 0 = -18 dB

Maximum Doppler Shift: < 7 KHz Maximum Doppler Rate: Negligible Acquisition Time / Preamble Length: < 25 ms The preamble waveform for this example is to consist of a fixed number of repeated copies of a PN code sequence. The circuit from Figure 2 is used for DSSS acquisition. Note that a relatively long acquisition time is available for the preamble and sufficient E C / N 0 is also available. The FFT size selected is based on the PN code length of the preamble (2048) and zero-padding requirements for the FFTs. For this example an FFT size of 32K is selected. The performance requirements in this example are not demanding, and a Xilinx Core Generator FFT (a serial FFT) in a Virtex-6 FPGA will meet these requirements. The Virtex-6 FPGA clock frequency is 500 MHz and the sampling rate is 100 MHz, this yields the following FPGA metrics: FFT Size: 32K FFT Requirements for FPGA Resources (per FFT): 52 DSP48E1 Slices and 175 Block RAMS FFT Latency estimate (per FFT): 262 us

Complex Multiplier Requirements: 15 DSP48E1 Slices ea.

The sampling rate of the data presented to the input of the FFT is 100 MHz. The frequency resolution combined with the maximum value of Doppler shift of less than 7KHz implies only a few IFFT output bins will require a coarse frequency search using FFT bin shifting. Coarse frequency search time is essentially the time to execute an FFT and IFFT or just over about 0.5 ms. From simulation, a coarse and fine frequency search strategy is verified such that even in the presence of matched filter decorrelation loss due to the maximum Doppler shift, sufficient SNR exists at the output of the matched filter to meet the desired probability of detection. After the threshold detection logic declares a signal is present, the correct PN Code phase offset is obtained. A frequency search strategy is used to perform frequency estimation of the Doppler shift. The search logic in Figure 2 must obtain a correct frequency estimate within the acquisition bandwidth of the frequency tracking circuit. An accurate PN code phase and frequency estimate is obtained, and the tracking loops are closed. The PN Code tracking circuit consists of an ELG and requires an initial PN code estimate within +/- 1 PN code chip. Figure 4 shows a plot of the ELG initial tracking after the loop is closed.

A discussion of high performance DSSS acquisition and tracking circuits was provided. The requirements for these circuits was based on several assumptions, such as a DSSS preamble, short acquisition times, low E C / N 0 , and aerospace communications environments in which large matched filters are required and the matched filter coefficients need to be updated in real-time to reduce decorrelation loss due to Doppler shift. Two high performance circuits were presented to implement DSSS acquisition and tracking circuits in FPGAs under these conditions. For the circuits presented in this paper, the FFTs complex multipliers and memory requirements are the most demanding and challenging aspects of FPGA implementation. An example design was provided to illustrate the techniques identified in the paper.

Figure 4 Early-Late Gate tracking performance.

6. CONCLUSIONS
Designing and implementing communications systems in the aerospace environment can present many challenges to the communications designer. This paper has provided a general discussion of the some of the challenges associated with DSSS synchronization in aerospace communications. The aerospace environment often has high physical dynamics between the transmitter and receiver. The determination of Doppler and Doppler rate was discussed as well as using the ambiguity function to examine preamble waveform properties under PN code phase delay and Doppler shift. This paper has also presented general design considerations for DSSS acquisition and tracking circuits. 9

REFERENCES
[1] Sklar, Bernard, Digital Communications Fundamentals and Applications, 2nd Edition, Prentice Hall, Upper Saddle River, NJ, 2001. [2] Harris, F.J., Multirate Signal Processing for Communication Systems, Prentice Hall, Upper Saddle River, NJ, 2004. [3] Rice, M., Digital Communications: A Discrete-Time Approach, Prentice Hall, Upper Saddle River, NJ, 2008. [4] Ziemer, R.E., Peterson, R.L., and Borth, D.E., Introduction to Spread-Spectrum Communications, Prentice Hall, Upper Saddle River, NJ, 1995. [5] Holmes, J.K., Spread Spectrum Systems For GNSS and Wireless Communications, Artech House, Norwood, MA, 2007. [6] Holmes, J.K., Coherent Spread Spectrum Systems, John Wiley & Sons, Inc., New York, 1982. [7] Simon, M.K., Omura, J.K., Scholtz, R.A., Holmes, and Levitt, B., Spread Spectrum Communications Handbook, Electronic Edition, McGraw Hill, Inc. New York, 2002. [8] Dixon, R.C., Spread Spectrum Systems with Commercial Applications, 3rd Edition, John Wiley & Sons, Inc., New York, 1994. [9] Stephens, D. R., Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations, 2nd Edition, Kluwer Academic Publishers, Inc., Norwell, MA, 2002. [10] Kaplan, E.D., Hegarty, C., Understanding GPS: Principles and Applications, 2nd Edition, Artech House, Norwood, MA, 2005. [11] Gardner, F.M., Phaselock Techniques, 3rd Edition, John Wiley & Sons, Inc., New York, 2005. [12] Viterbi, A.J., Principles of Coherent Communication, McGraw Hill, Inc. New York, 1966. [13] Viterbi, A.J., CDMA: Principles of Spread Spectrum Communication, Addison-Wesley, Reading, MA, 1995. [14] Meyer, H., Ascheid, G., Synchronization in Digital Communications Volume 1 Phase-, FrequencyLocked Loops, and Amplitude Control, John Wiley & Sons, Inc., New York, 1990. [15] Meyer, H., Moeneclaey, M., and Fechtel, S.A., Digital Communications Receivers Volume 2 Synchronization, Channel Estimation, and Signal Processing, John Wiley & Sons, Inc., New York, 1998. [16] Xiong, F., Digital Modulation Techniques, Artech House, Norwood, MA, 2000. [17] Tranter, W.H., Shanmugan, K.S., Rappaport, T.S., and Kosbar, K.L., Principles of Communications Systems Simulation with Wireless Applications, Prentice Hall, Upper Saddle River, NJ, 2004. [18] Proakis, J.G., Salehi, M., and Bauch, G., Contemporary Communication System Using MATLAB and Simulink, 2nd Edition, Brooks/Cole-Thomson Learning, Belmont, CA, 2004. [19] Brigham, E.O., The Fast Fourier Transform and Its Applications, Prentice Hall, NJ, 1988. [20] Ali, I., Al-Dhahir, N., Hershey, J.E., Doppler Characterization for LEO Satellites, IEEE Transactions on Communications, Vol. 46, No. 3, March, 1998. [21] Akopian, D., Fast FFT based GPS satellite acquisition methods, IEE Proc.-Radar Sonar Navig., Vol. 152, No. 4, August, 2005. [22] Natali, F. D, AFC Tracking Algorithms, IEEE Trans. on Communications, Vol. COM-32, No. 8, August, 1984. [23] Xilinx Web site for Virtex-6 product information http://www.xilinx.com/products/virtex6/

BIOGRAPHY
John Porcello is a Senior Research Engineer for the Sensor Systems Engineering Division (SSED) of the Sensors and Electromagnetic Applications Laboratory (SEAL) at Georgia Tech Research Institute (GTRI). Mr. Porcello designs, develops and implements Digital Signal Processing (DSP) Algorithms in FPGAs for a wide range of applications including radar and communications, and is a member of the IEEE.

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