Du microprocesseur au microcontrôleur

De l’ordinateur au système embarqué

Hervé BOEGLEN
 Plan

1. Introduction
2. Technologie des SoC-FPGA
3. Technologie ARM
4. L’écosystème Arduino
5. Exemples

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 1. Introduction
Trois niveaux de performance

SoC-FPGA µP embarqué µC

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 1. Introduction
Evolution de l’électronique depuis 1948

2011 : Intel Core I7

2600K, 32nm :
Die : 216mm2
1,16 x 109 transistors !

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 1. Introduction
La loi de Moore

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 1. Introduction
La densité de puissance

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 1. Introduction
Les systèmes numériques aujourd’hui :

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 1. Introduction
La conception des systèmes numériques :

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 1. Introduction
Les cibles logicielles et matérielles :
Les cibles logicielles (=µP, µC, DSP)

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 1. Introduction
Les µP :

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 1. Introduction
Les µC :

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 1. Introduction
Les µC :

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 1. Introduction
Les Digital Signal Processors (DSP) :

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 1. Introduction
Les Digital Signal Processors (DSP) :

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 1. Introduction
En résumé sur les cibles logicielles :
• Avantages :
– Flexibilité: il suffit de modifier le programme pour
modifier l’application
– Simple à mettre en œuvre grâce à la programmation de
haut niveau (langage C) (possibilité de grande abstraction
par rapport au matériel)
– Temps de conception courts et coûts de conception faibles
– Prix de revient faible
• Inconvénients :
– Faibles performances (consommation de puissance, vitesse
de fonctionnement, puissance de calcul, etc,) à cause
d’une architecture séquentielle (une opération à la fois, ou
quelques unes dans le cas superscalaire) et de trop
nombreux accès à la mémoire (instructions + données)
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 1. Introduction
 Les cibles matérielles spécialisées (ASIC) :

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 1. Introduction
 Les différentes cibles matérielles :

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 1. Introduction
 ASIC full custom :

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 1. Introduction
 ASIC standard cell :

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 1. Introduction
 ASIC gate array:

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 1. Introduction
 ASIC gate array:

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 1. Introduction
 Circuit configurable (ici FPGA) :

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 1. Introduction
 Le marché des FPGA :

Xilinx

58%

31% 11%

Altera All Others

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 1. Introduction
 ASIC vs FPGA:

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 1. Introduction
 De 1997 à 2005 : évolution des coûts

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 1. Introduction
 Temps de conception comparés :

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 1. Introduction
 Conclusion ASIC :
• Avantages :
– Haute intégration,
– Hautes performances (vitesse, consommation),
– Coûts unitaires faibles en production de masse
– Personnalisation
– Sécurité industrielle
• Inconvénients :
– Prix du 1er exemplaire,
– Pas d’erreur possible
– Non-flexible
– High time to market
– Fabrication réservée aux spécialistes (fondeurs),

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 1. Introduction
 Conclusion FPGA :

• Avantages :
– Possibilité de prototypage,
– Low time to market
– Adaptabilité aux évolutions futures (reconfiguration)
– Flexibilité
• Inconvénients :
– Intégration limitée,
– Moins performant qu’un ASIC
– Prix unitaire élevé en production de masse

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 1. Introduction
 Mais les méthodes de conception évoluent car :
• Toujours plus d’intégration (SoC)
• Les FPGA sont de plus en plus performants et de
moins en moins chers,
• Les FPGA remplacent peu à peu les ASIC…

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2. Technologie des SoC-FPGA

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 2. Technologie des SoC-FPGA
What is an FPGA ?
 Field Programmable Gate Array
 Gate Array
Two-dimensional array of logic gates
Traditionally connected with customized metal
Every logic circuit (customer) needs a custom-
manufactured chip
 Field Programmable
Customized by programming after manufacture
One FPGA can serve every customer
 FPGA: re-programmable hardware 31/119
 2. Technologie des SoC-FPGA
Basic Internals of an FPGA
Logic Logic Logic
Element Element Element

Logic Logic Logic

Element Element Element

Each logic element is

programmed to
Logic Logic Logic to implement the
Element Element Element desired function

Programmable Connections
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 2. Technologie des SoC-FPGA
FPGA Logic Element
 Look-Up Table (LUT) + register + extra …
SRAM
LUT 0
Cell
0
A 0
Out 0 Out
B 1
0
1

A B

 FPGAs typically use 4-input or larger LUTs

 Cyclone family (low cost): 4-inputs
 Stratix II: Adaptive Logic Module implements 4 – 6 input
LUTs efficiently
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 Virtex 5: 6 inputs
 2. Technologie des SoC-FPGA
Connecting the Logic

y
LE
z

f
I/O Pads

x I/O Pad

FPGA
 Logic elements implement the pieces of the circuit
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 Now hook them up with the programmable routing
 2. Technologie des SoC-FPGA
Programmable Routing
 Programmable switches connect fixed metal wires
 Choose pattern so any logic element can connect to
any other

In2
Logic Block
In1 Out
SRAM
cell

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 2. Technologie des SoC-FPGA
Modern, mid-size FPGA – 2S60
I/O Channels with
External Memory
Adaptive Logic Interface Circuitry
Modules
High-Speed I/O
Channels with
M512 Block DPA
Digital Signal
Processing
M4K Block (DSP) Blocks

M-RAM Blocks
High-Speed I/O
Channels with
Dynamic Phase
Alignment (DPA)

I/O Channels with Phase-Locked

External Memory Loops (PLL)
Interface Circuitry
60,440 Equivalent Logic Elements
2,544,192 Memory Bits
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90nm Stratix II 2S60
2. Technologie des SoC-FPGA

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2. Technologie des SoC-FPGA

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 2. Technologie des SoC-FPGA
FPGA-SoC SDR platform

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2. Technologie des SoC-FPGA

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 2. Technologie des SoC-FPGA
400MHZ max mais traitement parallèle !
Exemple soit à réaliser :
• Réalisation logicielle à 400MHz : 7 cycles machine
= 17,5 ns

• Réalisation matérielle : temps de traversée des

portes = 2 ns

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 2. Technologie des SoC-FPGA
Attention on travaille par défaut en virgule fixe !

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 2. Technologie des SoC-FPGA
Attention on travaille par défaut en virgule fixe !

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 2. Technologie des SoC-FPGA
Attention on travaille par défaut en virgule fixe !

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 2. Technologie des SoC-FPGA
Attention on travaille par défaut en virgule fixe !

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 2. Technologie des SoC-FPGA
Attention on travaille par défaut en virgule fixe !

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 2. Technologie des SoC-FPGA
Une multiplication coûte de la ressource

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 2. Technologie des SoC-FPGA
Techniques d’implémentation spécifiques
Exemple : FIR

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 2. Technologie des SoC-FPGA
Techniques d’implémentation spécifiques
Exemple : FIR

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 2. Technologie des SoC-FPGA
Techniques d’implémentation spécifiques
Exemple : FIR

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2. Technologie des SoC-FPGA
Software & Development Tools
Quartus Prime
 All Stratix, Arria & Cyclone Devices
 APEX II, APEX 20K/E/C, Excalibur, &
Mercury Devices
 FLEX 10K/A/E, ACEX 1K, FLEX 6000
Devices
 MAX II, MAX 7000S/AE/B, MAX 3000A
Devices
Quartus Prime Lite Edition
 Free Version
 Not All Features & Devices Included
• See www.altera.com for Feature Comparison

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2. Technologie des SoC-FPGA

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 2. Technologie des SoC-FPGA
SoCKit Specifications
FPGA
Cyclone V SX SoC—5CSXFC6D6F31C8NES
119K LEs, 41509 ALMs
5140 M10K memory blocks
6 FPGA PLLs and 3 HPS PLLs
2 Hard Memory Controllers
3.125G Transceivers
ARM®-based hard processor system (HPS)
800 MHz, A Dual-Core ARM Cortex™-A9 MPCore™ Processor
512 KB of shared L2 cache
64 KB of scratch RAM
Multiport SDRAM controller with support for DDR2, DDR3,
LPDDR1, and LPDDR2
8-channel direct memory access (DMA) controller
Memory
1GB (2x256MBx16) DDR3 SDRAM on FPGA
1GB (2x256MBx16) DDR3 SDRAM on HPS
128MB QSPI Flash on HPS
Micro SD Card Socket on HPS
EPCQ256 Flash on FPGA
IO
USB 2.0 OTG (ULPI interface with micro USB type AB connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
VGA, LCD
Audio
Switches, buttons, LEDs
G sensor (HPS) , Temp. sensor (FPGA) 66/119
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2. Technologie des SoC-FPGA
DE1-SoC

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 3. Technologie ARM
La société
 ARM founded in November 1990
 Advanced RISC Machines

 Company headquarters in Cambridge, UK

 Processor design centers in Cambridge, Austin, and Sophia Antipolis
 Sales, support, and engineering offices all over the world

 Best known for its range of RISC processor cores designs

 Other products – fabric IP, software tools, models, cell libraries - to help
partners develop and ship ARM-based SoCs

 ARM does not manufacture silicon

 Over 30 billion ARM® technology based chips shipped to date

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 3. Technologie ARM
 ~4 Billion ARM® Processors Each Year

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 3. Technologie ARM
 Communauté ARM

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 3. Technologie ARM
 Processeurs pour l’embarqué

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 3. Technologie ARM
 Processeurs pour applications

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 3. Technologie ARM
 Evolution de l’architecture
v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword interworking Multi-processing
/ byte support CLZ v6 Memory architecture
Architecture Profiles
Saturated arithmetic Unaligned data support
System mode DSP MAC 7-A -
instructions Extensions: Applications
Thumb Thumb-2 7-R - Real-
instruction set Extensions: (6T2) time
(v4T) Jazelle TrustZone® 7-M -
(5TEJ) (6Z) Microcontroller
Multicore
(6K)
Thumb only
(6-M)

 Note that implementations of the same architecture can be different

 Cortex-A8 - architecture v7-A, with a 13-stage pipeline
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 Cortex-A9 - architecture v7-A, with an 8-stage pipeline
 3. Technologie ARM
 Architecture ARMv7 : profils
 Application profile (ARMv7-A)
 Memory management support (MMU)
 Highest performance at low power
 Influenced by multi-tasking OS system requirements
 TrustZone and Jazelle-RCT for a safe, extensible system
 e.g. Cortex-A5, Cortex-A9

 Real-time profile (ARMv7-R)

 Protected memory (MPU)
 Low latency and predictability ‘real-time’ needs
 Evolutionary path for traditional embedded business
 e.g. Cortex-R4

 Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)

 Lowest gate count entry point
 Deterministic and predictable behavior a key priority
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 e.g. Cortex-M3
 3. Technologie ARM
 Quelle est l’architecture de mon processeur ?

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 3. Technologie ARM
 Quelle est l’architecture de mon processeur ?

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 3. Technologie ARM
 Architecture ARMv7 : profils A et R
 Application profile (ARMv7-A)
 Memory management support (MMU)
 Highest performance at low power
 Influenced by multi-tasking OS system requirements
 e.g. Cortex-A5, Cortex-A8, Cortex-A9, Cortex-A15

 Real-time profile (ARMv7-R)

 Protected memory (MPU)
 Low latency and predictability ‘real-time’ needs
 Evolutionary path for traditional embedded business
 e.g. Cortex-R4, Cortex-R5
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 3. Technologie ARM
 Exemple Cortex-A9
 ARMv7-A Architecture
 Thumb-2, Thumb-2EE
 TrustZone support
 Variable-length Multi-issue
pipeline
 Register renaming
 Speculative data prefetching
 Branch Prediction & Return
Stack
 64-bit AXI instruction and data  Optional features:
interfaces  PTM instruction trace interface
 TrustZone extensions  IEM power saving support
 L1 Data and Instruction caches  Full Jazelle DBX support
 16-64KB each  VFPv3-D16 Floating-Point Unit (FPU) or
 4-way set-associative NEON™ media processing engine 78/119
 3. Technologie ARM
 Exemple Cortex-A15 (Samsung Galaxy S4)
 1-4 processors per cluster
 Fixed size L1 caches (32KB)
 Integrated L2 Cache
 512KB – 4MB
 System-wide coherency
support with AMBA 4 ACE
 Backward-compatible with
AXI3 interconnect
 Integrated Interrupt Controller
 0-224 external interrupts for
entire cluster
 CoreSight debug
 Advanced Power Management
 Large Physical Address Extensions (LPAE) to ARMv7-A Architecture
 Virtualization Extensions to ARMv7-A Architecture
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 3. Technologie ARM
 Modèle de programmation
 ARM is a 32-bit load / store RISC architecture
 The only memory accesses allowed are loads and stores
 Most internal registers are 32 bits wide
 Most instructions execute in a single cycle
 When used in relation to ARM cores
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)
 Doubleword means 64 bits (eight bytes)
 ARM cores implement two basic instruction sets
 ARM instruction set – instructions are all 32 bits long
 Thumb instruction set – instructions are a mix of 16 and 32 bits
 Thumb-2 technology added many extra 32- and 16-bit instructions to the original 16-
bit Thumb instruction set

 Depending on the core, may also implement other instruction sets

 VFP instruction set – 32 bit (vector) floating point instructions
 NEON instruction set – 32 bit SIMD instructions
 Jazelle-DBX - provides acceleration for Java VMs (with additional software support)
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 Jazelle-RCT - provides support for interpreted languages
 3. Technologie ARM
 Modes du processeur
 ARM has seven basic operating modes
 Each mode has access to its own stack space and a different subset of registers
 Some operations can only be carried out in a privileged mode
Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes

Entered when a high priority (fast) interrupt is

FIQ
raised

IRQ Entered when a normal priority interrupt is raised

Privileged
modes
Abort Used to handle memory access violations

Undef Used to handle undefined instructions

Privileged mode using the same registers as User

System
mode
Mode under which most Applications / OS tasks Unprivileged
User 81/119
run mode
 3. Technologie ARM
 Les registres
User mode IRQ FIQ Undef Abort SVC
r0
r1
r2 ARM has 37 registers, all 32-bits long
r3
r4 A subset of these registers is accessible in
r5 each mode
r6 Note: System mode uses the User mode
r7 register set.
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr
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Current mode Banked out registers
 3. Technologie ARM
 Les bases du jeu d’instructions
 The ARM Architecture is a Load/Store architecture
 No direct manipulation of memory contents
 Memory must be loaded into the CPU to be modified, then written back out

 Cores are either in ARM state or Thumb state

 This determines which instruction set is being executed
 An instruction must be executed to switch between states

 The architecture allows programmers and compilation tools to reduce

branching through the use of conditional execution
 Method differs between ARM and Thumb, but the principle is that most (ARM) or
all (Thumb) instructions can be executed conditionally.

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 3. Technologie ARM
 Instruction de traitement de données
 These instructions operate on the contents of registers
 They DO NOT affect memory
arithmetic logical move
manipulation ADC SBC BIC ORR MVN
(has destination ADD SUB RSB AND EOR MOV
register) RSC ORN

comparison CMN CMP TST TEQ

(set flags only) (ADDS) (SUBS) (ANDS) (EORS)

 Syntax:
<Operation>{<cond>}{S} {Rd,} Rn, Operand2
 Examples:
 ADD r0, r1, r2 ; r0 = r1 + r2
 TEQ r0, r1 ; if r0 = r1, Z flag will be set
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 MOV r0, r1 ; copy r1 to r0
 3. Technologie ARM
 Transfert de données en accès simple
 Use to move data between one or two registers and memory
LDRD STRD Doubleword
LDR STR Word

Memory
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load 31 0
Upper bits zero filled or
Rd
sign extended on Load

 Syntax:
 LDR{<size>}{<cond>} Rd, <address>
 STR{<size>}{<cond>} Rd, <address>

 Example:
 LDRB r0, [r1] ; load bottom byte of r0 from the
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 3. Technologie ARM
 Qu’est-ce que NEON ?
 NEON is a wide SIMD data processing architecture
 Extension of the ARM instruction set (v7-A)
 32 x 64-bit wide registers (can also be used as 16 x 128-bit wide registers)
 NEON instructions perform “Packed SIMD” processing
 Registers are considered as vectors of elements of the same data type
 Data types available: signed/unsigned 8-bit, 16-bit, 32-bit, 64-bit, single prec. float
 Instructions usually perform the same operation in all lanes
Source
Source
Registers
Registers
Dn
Elements
Dm
Operation

Dd Destination
Register
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Lane
 3. Technologie ARM
 Processeurs Cortex MPCore
 Standard Cortex cores, with additional logic to support MPCore
 Available as 1-4 CPU variants
 Include integrated
 Interrupt controller
 Snoop Control Unit (SCU)
 Timers and Watchdogs

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 3. Technologie ARM
 Architecture ARMv7 : profil M
 v7-M Cores are designed to support the microcontroller market
 Simpler to program – entire application can be programmed in C
 Fewer features needed than in application processors
 Register and ISA changes from other ARM cores
 No ARM instruction set support
 Only one set of registers
 xPSR has different bits than CPSR
 Different modes and exception models
 Only two modes: Thread mode and Handler mode
 Vector table is addresses, not instructions
 Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
 Different system control/memory layout
 Cores have a fixed memory map
 No coprocessor 15 – controlled through memory mapped control registers 88/119
 3. Technologie ARM
 Exemple Cortex M3
 ARMv7-M Architecture
 Thumb-2 only
 Fully programmable in C
 3-stage pipeline
 von Neumann architecture
 Optional MPU
 AHB-Lite bus interface
 Fixed memory map
 1-240 interrupts
 Configurable priority levels
 Non-Maskable Interrupt support
 Debug and Sleep control
 Serial wire or JTAG debug
 Optional ETM
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 3. Technologie ARM
 Jeu de registres
R0  Registers R0-R12
R1
R2  General-purpose registers
R3
R4  R13 is the stack pointer (SP) - 2 banked versions
R5
R6
R7
 R14 is the link register (LR)
R8
R9  R15 is the program counter (PC)
R10
R11
R12
 PSR (Program Status Register)
 Not explicitly accessible
R15 (PC)
 Saved to the stack on an exception
 Subsets available as APSR, IPSR, and EPSR
PSR

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 3. Technologie ARM
 Organisation mémoire
External Private Peripheral Bus
E00F_FFFF
ROM Table
E00F_F000

UNUSED FFFF_FFFF

E004_2000 512MB System (XN)

ETM E000_0000
E004_1000
TPIU
E004_0000

1GB
External
E003_FFFF Peripheral
RESERVED
E000_F000
NVIC A000_0000
E000_E000
RESERVED
E000_3000
FPB 1 GB
External
E000_2000 SRAM
DWT
E000_1000
ITM
E000_0000 6000_0000
Internal Private Peripheral Bus
512MB Peripheral
4000_0000

512MB SRAM
2000_0000

512MB Code 91/119

0000_0000
 3. Technologie ARM
 ARM SoC
 ARM core deeply embedded within an
SoC
Clocks and DMA
 External debug and trace via JTAG or Reset Controller Port
CoreSight interface (XN)
 Design can have both external and ARM
FLASH
External
internal memories Processor

AMBA AXI
Memory
core
 Varying width, speed and size – Interface

depending on system requirements DEBUG

SDRAM
 Can include ARM licensed CoreLink nIRQ
nFIQ On chip
peripherals CoreLink
memory

 Interrupt controller, since core only has Interrupt

Controller APB
two interrupt sources

AMBA APB
Bridge
Other
 Other peripherals and interfaces CoreLink
Peripherals
 Can include on-chip memory from
ARM Artisan Physical IP Libraries Custom
ARM based
Peripherals
 Elements connected using AMBA SoC
(Advanced Microcontroller Bus
Architecture)
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 3. Technologie ARM
 ARM SoC : smartphone

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 3. Technologie ARM
 Exemple système AMBA (Advanced Microcontroller
Bus Architecture) APB (Advanced
Peripheral Bus)
High Performance
ARM processor UART
AHB
High (Advanced
Bandwidth Timer
High APB
External performance Bridge
Memory Bus) Keypad
Interface

High-bandwidth DMA PIO

on-chip RAM Bus Master
Low Power
Non-pipelined
High Performance Simple Interface
Pipelined
Burst Support
Multiple Bus Masters
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 3. Technologie ARM
 Outils de développement

Software Tools JTAG Debug and Trace Development Platforms

 DS-5  DSTREAM  Fast Models
 Application Edition  Versatile Platform
 Linux Edition baseboards
 Professional Edition

 MDK: Keil  ULINK  Keil MCU development

Microcontroller boards
Development Kit  Keil µVision simulator

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 3. Technologie ARM
 Outil DS-5 Professionnel
 Integrated solution, professionally supported and maintained
 End-to-end development, from SoC bring-up to application debug
 Powerful ARM compiler
 Best code size and performance DS-5
Eclipse
 Intuitive DS-5 debugger Compiler
IDE Debugger Streamline
 Flexible graphical user interface
Device Configuration Database
 DSTREAM probe with 4GB trace buffer
Simulation Hardware Debug
 Fast SoC simulation models
 Develop in a controlled environment
 Examples and applications
 Streamline performance analyzer
 System-wide analysis of Linux
and Android systems
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 3. Technologie ARM
 Development Kits
 Low cost tools for ARM7, ARM9, Cortex-M and Cortex-R4 MCUs
 Extensive device support for many devices
 Core and peripheral simulation
 Flash support
 Microcontroller Development Kit (MDK)
 IDE, optimized run-time library, KEIL RTX RTOS
 ARM Compiler
 Realtime trace (for Cortex-M3 and Cortex-M4 based devices)
 Real-Time Library
 KEIL RTX RTOS + Source Code
 TCP networking suit, Flash File System, CAN Driver Library, USB Device Interface
 Debug Hardware
 Evaluation boards

 Separate support channel

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 See www.keil.com
 3. Technologie ARM
 Exemple pour moins de 13$ :

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 3. Technologie ARM
 Exemple pour moins de 15€ : STM32F4 Discovery

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 3. Technologie ARM
 Le projet Raspberry PI

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 3. Technologie ARM
 Le projet Raspberry PI :

Raspberry PI
Model B+

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 3. Technologie ARM
 Le projet Raspberry PI : caractéristiques RPI 3 :

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SoC
Broadcom BCM2835
“High Definition Embedded Multimedia
Application Processor.”

Uses ARM1196JZF-S(ARM v6)

J- Jazelle bytecode
Z- Trust zone
F- Floating point
S-Synthesizable core.
AMBA-3 improves memory bus performance.
OS
-mainly linux based OS.
-
OS and Programming language
Linux or Windows 10 IoT.
Fedora , Archlinux & Debian .
Most recommended Debian ,Because it supports python programming language.

Raspberry Pi Versions of Kernels are

available
Fedora-Pidora
Debian-Raspbian
 3. Technologie ARM
 Démo Raspberry Pi Linux PIXEL

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 4. L’écosystème Arduino
 Arduino Uno :

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 5. Exemples
 Applications :

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 5. Exemples
 Applications :
 SoC FPGA : TERASIC SPIDER

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 5. Exemples
 Applications :
 SoC FPGA : TERASIC SPIDER

 Vidéo 110/119
 5. Exemples
 Applications :
 ARM Cortex M : Drone FPV 100% logiciel libre

FPV
youtube

Drone
speed
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 5. Exemples
 Applications :
 ARM Cortex M : Drone

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 5. Exemples
 Applications :
 Boucle de contrôle

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 5. Exemples
 Applications :
 Carte contrôleur : SP Racing F3

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 5. Exemples
 Applications :
 Propulsion : moteurs et contrôleurs brushless (flashés avec BLHELI)

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 5. Exemples
 Applications :
 Retour vidéo

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 5. Exemples
 Applications :
 Radiocommande : FRSKY Taranis OPENTX, X4R-SB et retour télémétrie

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 5. Exemples
 Applications :
 Logiciels de configuration

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 5. Exemples
 Drone 250 FPV

Démo
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 TEST
 Questions :
 1. Quelles sont les différences entre un microprocesseur et un
microcontrôleur
 2. Qu’est-ce qu’un ASIC ?
 3. Qu’est-ce qu’un FPGA ?
 4. Qu’est-ce qu’un SoC ?
 5. ARM est une société qui fabrique des microprocesseurs. Vrai ou Faux ?
 6. On peut faire tourner un système d’exploitation comme Linux sur un
ARM Cortex M. Vrai ou Faux ?
 7. Le Raspberry Pi est un mini ordinateur qui utilise un ou plusieurs cœurs
ARM. Vrai ou Faux ?
 8. L’Arduino Uno est un système à microprocesseur. Vrai ou Faux ?
 9. Dans l’écosystème Arduino qu’est-ce qu’un shield ?
 10. Qu’est-ce qu’un serveur VNC ?

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