PCB Design For Fabrication Issues

Design for Fabrication issues
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Panelisation Build Drilling Inner copper layers Outer copper layers Other copper design issues Solder mask Additional prints Finishing steps
Panelisation
The cost of a panel is made up of 40% materials, 20% process materials, and 40% overheads and labour. Using the panel as effectively as possible becomes very important, because you pay for the whole of the panel even if you only use half of it, and only minor savings (for example in drilling and profiling time) can be made. So you incur all the costs of materials and process materials, and most of the labour/overheads. A typical range of standard panels1 available is given in Table 1:
Table 1: Standard panel sizes available
inches 24 14 24 18 24 20 24 21 24.4 14 24.4 21 25.2 14* 25.2 21*
mm 609.6 355.6 609.6 457.2 609.6 508 609.6 533.4 619.76 355.6 619.76 533.4 640 355.6* 640 533.4*
doublerouted down or double-sided 605 351 6.5 453 605 504 605 524 615 351 615 524 635 351* 635 524* 625 510**
* Only use after consultation ** Double-sided only
1 All
the specific figures on this page are based on the Circatex Capability Statement as at December 2002. They are representative of general practice within the industry, but you should always check with your supplier before deciding on a board specification.
To get the best utilisation factor, take your circuit board element, and try laying it out on panels of different sizes, with the circuit stepped both vertically and horizontally. The
http://www.ami.ac.uk/courses/ami4945_dpb/restricted/u08/supplementary/sup_02.html
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best usage might in fact be a combination of vertical and horizontal alignment (Figure 1). In doing this you should also take account of how the board will be handled by your assembly house, and look for an overall lowest cost solution.
subFigure 1: An example of sub-optimal panelisation
In order to understand how best to lay out your circuit within the panel, you need to know what margins to leave. Typically the fabricator requires a no-go border of between 15 mm and 25 mm within the outline of the panel to facilitate handling and to accommodate various features such as identification, fixturing, registration and location tooling associated with his manufacturing process. You will see from Table 2 that, for this particular fabricator, the margins required are different for the four sides, for a range of process reasons2, and there are further requirements for multilayer products, again dictated by the tooling.
2
Typical process reasons are that: A margin has to be left around the panel to place the photoresist. The photoresist is narrower than the panel, and is cut short at both ends, in order to get proper adhesion and avoid undercutting, as well as leave an area around the panel that is coated by copper. The plating well has clips with relatively deep throats, with the result that additional depth is needed at the bottom of the panel. Requirements for routing and LPISM relate to the tooling on those processes.
doubleTable 2: Margins required for double-sided product
margin between circuit and
reason for margin
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bottom of panel top of panel left of panel right of panel
photomech resist placement 14.6 14 13.6 8
plating rail rout LPISM 21 15 20 12 10 10 115 20 10 10 13.6 13.6
As a designer, you will find it difficult to deal with this level of detail, especially as panelisation is an area where you must expect differences between fabricators .There are two ways of approaching the problem, both of which will involve consultation with board production: to start with the reasonable estimate that the fabricator will need a clearance of inch (18 mm) all round to use the information on useable area in your fabricators capability statement (Table 3) as the basis for your planning. Either way, you need to check your design if it looks close to the limit and seek advice about where to position your design and what separation to allow between sub-panels. Note that, overall, the useable area is substantially smaller than the original panel.
doubleTable 3: Useable area double-sided
routed down 605 x 351 605 x 453 605 x 504 605 x 524 615 x 351 615 x 524 635 x 351* 635 x 524* 625 x 510** *Only use after consultation
useable area 564 x 323.8 564 x 425.8 564 x 476.8 564 x 496.8 574 x 323.8 574 x 323.8 594 x 323.8* 594 x 496.8* 584 x 482.8**
There is a massive savings potential in correct panelisation. Maybe shaving only 5 mm off one dimension for your product will halve the cost of the board. But of course you can only achieve this saving if you thought about it early enough in the day to be able to adjust the rest of your design, which may include the packaging of the board within its housing. [back to top]
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Build
You will always be encouraged to use available standard materials and the standard thickness tolerance of 10%. For two-layer boards, the range of available nominal thicknesses (including copper) would typically be: 0.5mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.2mm, 1.4mm, 1.5mm, 1.6mm, 2.0mm, 2.4mm, 3.2mm Of these, 1.6mm is still the most common, being close to the earliest one-sixteenth inch board practice for which many connectors were designed. Multilayer builds are a totally different affair, and a major cause of both holds and additional cost. In the past, there have been standard builds, but now they may differ greatly. In fact it has even been said that there is no such thing as a standard. The key information that the fabricator needs is the required eventual thickness. This is because the final pressed thickness depends not only on the starting thickness of the materials, but also on the percentage coverage of copper, the resin flowing to take the place of copper removed by etching. This is referred to as the pressed-out loss.
pressedFigure 2: The source of pressed-out losses
Given the percentage coverage on each layer, and the fruits of experience, one can generate a spreadsheet with macros that enables you to calculate the likely pressed thickness of the board. Some programmes will also indicate the likely shrinkage of the layers, and give information on dielectric properties for controlled impedance boards.
Self Assessment Questions
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1. Describe the process you would go through to panellise a double-sided product. 2. Describe the source of pressed-out losses.
compare your answer with this one One of the most common issues that cause confusion between the PCB fabricator and his customer is where the thickness dimension is to be applied. Often the drawing is ambiguous and therefore the most important factor is to specify where the measurement is to be taken. Figure 3 shows the choices available.
Figure 3: Possible choices for board thickness dimensioning
The following rules are suggested for multilayer builds: The build must be balanced and symmetrical Minimise the number of sheets of prepreg Preferably use single ply prepreg Use cores as thick as possible (preferably >0.3mm) Maximum three sheets of prepreg per dielectric May need fillers for large dielectrics Tolerances for thickness must be 10% Never use standard resin 7628 as a single ply Minimise the number of different types of prepreg in a particular build Never use two plies of 7628HR or 7629HR in a single dielectric Dont specify dielectrics if avoidable Dont specify core construction.
Symmetrical and balanced build

Unless absolutely necessary for electrical reasons the board should be designed symmetrically around the Z-axis. The result of bad balancing of the Z-axis will be
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excessive warp, and twist. Figure 4 shows two boards: a good board on the left and a poor board on the right. The poor board has a variation of core and copper thickness resulting in asymmetry.
good bad Figure 4: A good board with a balanced stack up and a bad board with an unbalanced stack up
An unbalanced copper weight on the cores will make the etching process expensive. In Figure 5 we can see four examples of a 10-layer board. The worst board on the right-hand side has different copper weights on three of the cores and is not symmetrical about the centre line. The bad example has equal copper weighting on each core but still has asymmetry about the centre line. The OK example shows a symmetrical board and each core is balanced but there are different copper weights used throughout the board. The best example has the same copper weight throughout the entire board and is the most desirable option.
10Figure 5: Four 10-layer boards with different build options
Whenever possible select the same copper foil weight throughout the build, but if different copper weights must be used (for example, 35 m for signal layers and 70 m for power/ground layers) then try to use the same copper weight on each core
Prepregs
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Historically, two layers of prepreg have been used to separate foils and inner layers, on the principle that one is unlikely to get glass cloth flaws in successive layers, so the yield would be better. With improvements in the quality of the glass cloth used for prepreg, and the use of resin rich prepregs, with a higher percentage of resin, it is possible to create reliable assemblies with just one layer of prepreg (Figure 6). The cost saving can be quite significant in terms of both material and handling, with a six-layer 1.6 mm build comprising just seven components rather than ten. Again, this is not a view that every fabricator will hold, which is why you need to select your fabricator and then agree a process for minimum cost.
8Figure 6: Single prepreg builds for 4, 6 and 8-layer boards
Dielectric spacing
The minimum dielectric may be specified, if required, but individual spacing between copper layers should be left to the fabrication house, unless electrical requirements dictate that it be controlled.
Figure 7: Build and cost implications of specifying dielectric thickness
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The above example shows that three additional plies of prepreg would be required for the design on the right-hand side. This could add 1015% to the cost of the board.
Tolerance
A good rule of thumb for thickness tolerance is to use 10%. If a particular pair of copper layers requires a tighter tolerance, specify it on those layers only. To maintain tighter than 10% tolerance the fabricator must use higher glass to resin ratio in the build and this generally increases cost. The other option is to sort at final and eliminate the outof-specification product. Again, the customer will pay a premium for the sorting as well as the fallout.
Layer count
The lower the layer count the lower the cost. This is almost always the case, but not always! An 8-layer design with 150 m lines, and via holes 250 m or larger, may well be cheaper to manufacture than a 6-layer with 100 m lines and 150 m vias. There is no direct formula to follow but the designer must be aware of the capabilities of the fabricator he intends to use, both prototype and volume. In almost all cases an even number of layers should be used. A 5-layer PCB is no less expensive to fabricate than a 6layer and may have some significant manufacturability issues due to warp and twist.
Self Assessment Question

When designing a PCB, the fabricators will state a preference for a balanced and symmetrical board. Describe what this means, and why this benefits the fabrication process. compare your answer with this one [back to top]
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Drilling
Aspect ratio
The key aspects of drilling design, shown by the contrast between cost effective designs and technical designs, is the aspect ratio. This is in general the ratio of the depth of a hole to its width, and a fabricator will define the aspect ratio as the ratio of board thickness to hole diameter (Figure 8).
Figure 8: One definition of the aspect ratio of a hole
There are differences in practice of which you should be aware: Dimension t may be either the dielectric separation (as shown), or the overall laminate thickness including the copper (as in previous BS specifications) Dimension d may be either the drill size (which is the most appropriate for electroless plating), or the finished hole size (which is more applicable for the subsequent electroplating stage). However measured, aspect ratio is a major factor in yields through plating process, with a high aspect ratio leading to plating voids that are not detectable until bare board test. This gets particularly difficult when the holes are small. In consequence, a typical capability statement will have different categories for aspect ratio depending on the hole size (Table 4).
Table 4: Aspect ratio as a function of hole diameter in relationship to capability statement
hole size 0.25 mm <0.4 mm 0.4 mm
volume capability no review DfF review 6:1 7:1 7:1 8:1 11 : 1 12 : 1
pilot/special 10 : 1 panel thickness dictated
An alternative approach to recommending aspect ratio limits is shown in Table 5. Here the minimum suggested drilled hole diameter is expressed as a function of the board thickness, and does not reduce in line with the board thickness, the minimum hole size
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being determined by the fluid dynamics of the plating processes.

Table 5: Drilled hole aspect ratio chart (Merlin Circuit Technology)
start board thickness 0.5 mm 0.5 mm 0.8 mm 1.6 mm 2.4 mm 3.2 mm 4.0 mm 5.0 mm
drilled hole diameter 0.20 mm 0.25 mm 0.25 mm 0.30 mm 0.30 mm 0.30 mm 0.50 mm 0.50 mm
aspect ratio 2.5 : 1 2:1 3.2 : 1 5.33 : 1 8:1 10.7 : 1 8:1 10 : 1
Note that the hole diameters given do not represent the technical limit, but rather what can be achieved at 100% yield, with DC plating and no special process conditions. Smaller holes would be achieved by such means as better aeration of the plating bath, vibration to prevent bubble formation in small vias, and pulse plating.
Hole sizes
Most PCB fabricators have a wide selection of drill (hole) sizes available. Some charge per drill size used, others offer a standard set of drill sizes for no charge and then charge for any non-standard drill sizes. When choosing a hole size to fit a component lead, remember that the internal plating will reduce the effective diameter of the hole. Plating thicknesses vary considerably, but are likely to be in the range 2575 m. As with aspect ratios, the capability statement will categorize different hole sizes (Table 6). Note that capability statements for other fabricators will use slightly different terminology. For example, the volume capability no review column may be described as cost effective design, whereas the pilot/special column is regarded as technical design.
Table 6: Drilling design categories
dimension minimum drilled hole size non-PTH size drill-to-drill tolerance controlled depth nail-head datum top datum bottom oz 1 oz
volume capability no review DfF review 0.30 mm 0.25 mm 25 m 50 m 150 m 100 m 200% 150%
pilot/special 0.20 mm <25 m <50 m <150 m <100 m 170% 135%
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2 oz hole roughness countersunk holes counter-bored holes second drill tolerance
135% 35 m yes yes 200 m
150 m
125% <35 m 100 m
Pad sizes
The biggest issues to do with pad size are solderability and manufacturability. Solderability is a matter of process and materials control and will not be considered here as it lies within the remit of our Materials and Processes for EDR module; manufacturability is concerned with whether or not the pad will be broken when the hole is drilled in it.
Figure 9: Minimum annular ring 3
photograph actually shows a problem caused by poor outer-layer photomechanical alignment, rather than drilling positional accuracy, but the end result is the same whether or not an annular ring is visible will be a function of relative pad/drill sizes coupled to positional accuracy.
3 The
This is mainly a function of the accuracy of the fabricators drilling process. Dont forget that, for reasons of economy, drilling is carried out on a stack of boards rather than one board at a time. As well as targeting errors, deviations from intended position can therefore be caused by misalignment between boards, and the fact that drills tend to wander as they go through the stack. If a drill hole is slightly off-centre (misregistration) the pad may be broken at one edge, possibly leading to an open in the circuit (tangency or breakout). A standard requirement for pad sizes is a 125 m annulus. For example, a 0.7 mm diameter hole would require a 0.95 mm pad. However, something a little larger than this, maybe a 250 m annulus, is recommended for soldering, and the CECC 23000 recommendation is that
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the outer pad diameter should be 0.5 mm greater in diameter than the nominal finished hole size, in order to ensure 80 m minimum copper annular ring. Sometimes it is not possible to increase the annular ring without breaking other manufacturability rules. A good second option is the addition of teardrops to via holes where the track enters the pad (see Figure 10). This modification usually does not require major change to the design and adds a factor of safety to the annular ring. This feature can be added at layout or by the fabricator. A typical design would add a pad 250 m greater than the via finished size and position it 250 m along the track.
Figure 10: Annular ring problem and possible solutions
The final option is to relax the specification, allowing drill breakout along one-quarter of the hole perimeter (referred to as 90 breakout), and this is permissible for some consumer applications.
Hole density and clearance

Hole density is purely a cost issue. The more holes there are on a board, the longer the drilling process will take, the more drills will be used, and the more wear and tear there will be on the equipment, so the more the board will cost. Also, as hole density increases, so does the chance that the board will be defective: most fabricators set a maximum hole density and boards with greater density are charged more pro rata. Whenever possible non-plated holes should have adequate clearance around them on both sides of the board. Circatex recommend a minimum of 305 m free of metal (Figure 11): this allows both non-plated and plated holes to be drilled during the same operation, which is required to maintain good registration between the two types of holes. Other fabricators recommend 0.5 mm clearance between non-plated through-holes and adjacent
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pads or tracks.
Figure 11: Annular ring: requirements for tangency
Note that, if copper is required to be nearer the hole than the minimum recommended clearance, non-plated through-holes must be drilled after the plating operation, using a separate set-up. This demands tight positional tolerancing that may not be acceptable for larger holes such as tooling and mounting holes. Inner-layer copper must also be cleared back from the non-plated hole, in order to prevent shorts: 230 m minimum clearance is recommended to ensure good sealing of the laminate.
SingleSingle-sided plated holes

Occasionally component designs call for a plated through-hole with a copper pad on one side only. This is a difficult operation to complete successfully, and fabricators may be unable to give any guarantee of plating in the barrel of the hole. This is because the holes become partially tented by photoresist before the plating operation, which inhibits effective movement of the plating solution in the hole, leading to poor plating, as indicated in Figure 12.
singlethroughFigure 12: Potential problems with single-sided plated through-holes
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Unless cost is a real issue, you will get better results with single-sided PTH boards by starting with double-sided laminate and using an expanded (0.2 mm greater diameter) drill mask to pattern the component side. This gives perfectly plated holes and a 0.1 mm annular ring on the surface.

From the description above, produce your own summary of drilling recommendations. compare your answer with this one [back to top]
Inner copper layers

Any fabricator will introduce a number of changes to the original design, in order to make sure that the customer gets what was asked for. Some of these changes are less obvious than others and are discussed in the sections that follow: etch compensate artworks for the processes being used by adjusting the dimensions of features add teardrops to via holes where the track enters the pad wherever the annular ring is small enough to cause potential breakout and cannot be increased in size add circuit robbing for isolated features or unbalanced copper distribution through board remove non functional pads (NFPs) to increase drill accuracy and reduce the risk of short-circuits fill slivers and pin holes add identification markings adjust score to copper distance depending on depth of score make rout to copper distance 305 m on all layers adjust clearances between NPTH and copper: outer layers 305 m; inner layers 230 m balance the copper pattern.
Track width and spacing

The chemical and photographic processes used to fabricate a board put constraints on the minimum width of track and on the minimum spacing between tracks. If a track is made smaller than this minimum width, there is some chance that it will open (no connection) when manufactured; if two tracks are closer together than the minimum
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spacing, there is some chance they will short when manufactured. These parameters are usually specified as x/y rules or track/gap rules, where x is the minimum track width and y is the minimum track spacing. These rules (especially spacing) apply to any metal on the board, including pad to track spacing. In some parts of the industry, imperial measurements (in thousandths of an inch) are still used to specify minimum track width and spacing. For example, 8/10 rules indicate 8 thou (0.2 mm) minimum track width and 10 thou (0.25 mm) minimum track spacing, and 6 thou track and gap indicates 6 thou (150 m) minimum track width and spacing. However, in the UK, process rules are now more likely to be stated in m, as shown in Table 7.
Table 7: Inner layer design categories
volume capability dimension core thickness core thickness (differential copper) plated core thickness copper thickness oz etched track/printed gap 1 oz 2 oz min. pad to track plated core thickness plated core track/gap plated core annular ring min. annular ring min. PTH to copper oz no review 100 m 350 m 150 m 1870 m 75/75 m 100/100 m 150/150 m 90 m 150 m 125/125 m 150 m 150 m 225 m DfF review 75 m 250 m 125 m 125 m 100/100 m 125 m 100 m 175 m pilot/special 50 m <250 m 100 m 105140 m 50/50 m 75/100 m 125/125 m 75 m 100 m 75/100 m 100 m 75 m 150 m
These dimensions are moving inexorably downwards. Once a rarity, modern boards often have some areas with 4/5 (100/125 m) rules. Note that the smaller of the two dimensions will always be the track width, because this leads to better yields: processes are less likely to cause open-circuits by over-etching than they are to yield short-circuits. Of course, one reason why dimensions are moving downwards is that auto-routing tends to make overmuch use of minimum design criteria. In the example shown in Figure 13, some tracks have been designed on 75/100 m rules, which will incur a cost penalty, whereas room is available for a much more conservative layout.
AutocostFigure 13: Auto-routing producing a design that is not cost-effective
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Copper balancing on internal layers

The general concept of copper balance is to evenly distribute copper on both sides of the PCB, and also within each side. As we will see when considering outer layers, a balanced copper pattern is important for even plating distribution, but for inner layers the main consideration is to create a balanced lay-up, giving a board that will not warp during subsequent heat processing. Figure 14 shows before and after pictures of an internal PCB layer: before copper balancing the layer has areas with sparse copper tracking that will cause problems for the fabricator; after copper balancing has been added, the previously bare areas have been filled with isolated copper dots.
Figure 14: An internal layer with and without copper balancing
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before copper balancing
the same layer plus copper balancing
There are some general points to bear in mind when designing the copper balancing:
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added copper should be kept 2.5 mm from any functional feature and 3.75 mm from the board edge the copper pattern should be adjusted to balance the copper distribution the copper pattern should be covered by solder mask design rule checks must be run after balancing to ensure the circuit has not been altered (note that added copper should be give a (.thieving) attribute, in order to prevent it being considered by the test generation routine for high frequency circuits, impedance effects should be considered before adding balance, and it may be necessary to ground the added copper. Copper balancing may be carried out by designer or fabricator. If the latter, the board specification has to specify the rules to be applied, and it becomes very important that the designer should indicate clearly on the individual design any areas where adding copper might affect circuit performance. [back to top]
Outer copper layers Track width and spacing

The comments made for inner copper layers apply equally to outer copper layers, except that the dimensions are generally different. This reflects both the additional functions of the outer layers (used for component attachment and test probing) and the fact that outer layers are plated as part of the through-hole fabrication process. Table 8 gives a typical set of process rules.
Table 8: Outer layer design categories
volume capability dimension 0.25 mm aspect ratio for hole size <0.4 mm 0.4 mm base copper thickness oz etched track/ printed gap copper in PTH (min. average) copper in BV 1 oz >1 oz no review 6:1 7:1 7:1 1270 m 75/100 m 75/100 m 150/150 m 25 m DfF review 8:1 11 : 1 12 : 1 105 m 75/75 m 75/75 m abs. min. 25 m pilot/special 10 : 1 panel thickness dictated 9 m; >105 m <75/75 m <75/75 m 125/125 m to 40 m
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(min. average) min. a/r for tangency
15 m 125 m
100 m
to 25 m 75 m
As with inner layers, the trend in these dimensions continues downwards, and there is a preference for the smaller of the two dimensions to be the track width.
Copper balancing on external layers

Plating thickness varies according to the presence or otherwise of adjacent copper features. In general, it may be said that the more areas you are trying to plate, the thinner the copper will be. Conversely, when one plates isolated tracks, the plating thickness can be substantially greater than one wants. As shown in Figure 15, although the process conditions are identical, the plating thickness on a track becomes progressively thicker as the track moves further away from other tracks. This can be explained in simplistic terms as being due to the isolated pad experiencing less competition for current and the availability of metal in the plating solution.
Figure 15: Heavier plating on isolated copper features
But does a thick track matter? Not from the point of view of conductivity, and the extra width will not matter if it is isolated. There are, however, two important effects of which you must be aware. The first of these is on the thickness of the solder mask coat: thick copper will give a locally thin coat, with the potential to break down. There is also the mechanical effect on the board, where unbalance may lead to subsequent warpage.
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The magnitude of the difference between isolated pads and tracks close together is demonstrated clearly in Figure 16. Not only is the plating on the isolated pad much thicker, with a substantial degree of edge distortion, but the solder mask coating is very much thinner.
overFigure 16: Example of over-plating of copper feature
A second problem with heavier plating on isolated copper features, and the greater of the two when it comes to high frequency designs, is maintaining control of impedance values. Mushrooming affects the track widths and entraps dry-film resist between the tracks, which eventually retards the etching. The effect is similar to that of over-plating tin/tinlead resist which was illustrated in More about board fabrication, and is especially likely to happen with differential pairs. The resultant raggy tracks give ohmic values outside the normal accepted 10% tolerance. You may have noticed the term well-robbed in Figure 16. This relates to the usual practice of attempting to even out copper distribution on the board by adding areas of spare copper, so that the electrolytic plating process can add equal amounts of copper across the board without creating a thicker copper deposit on less-populated areas. These areas of spare copper are isolated from each other and from any active tracks. Because they act by attracting excessive copper plating away from otherwise isolated tracks, these areas are referred to as robber pads or copper thieves. (Figure 17) The patterns used vary, being sometimes arrays of dots and sometimes cross-hatching.
Figure 17: Addition of copper robbing
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Difficult to plate evenly due to isolated tracking
Solution: Robbing added in an attempt to even out copper distribution

Can you describe the following features and explain why they are used:
1. Copper balancing on internal layers 2. Copper balancing or robbing on external layers
compare your answer with this one [back to top]
Other copper design issues

Bottlenecks
Not all copper features are tracks and pads. Particularly with complex designs that have been extensively reworked, or where additional copper areas are used for screening or thieving, there may be instances of conductor narrowing, producing narrow strips of
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copper referred to as bottlenecks. As these can lead both to open-circuits and shortcircuits (where copper slivers can become detached during the fabrication process), it is important to detect bottlenecks. There are two broad types: the classic bottleneck, where conductor narrowing occurs between two features in a surface or between a feature and the outer edge of a surface conductor narrowing close to the end of a copper surface or feature (a tail). Some examples of bottlenecks are shown in Figure 18:
Figure 18: Four examples of copper bottlenecks (Valor)
Removal of non functional pads and tracks

One of the cleanup procedures that a fabricator will carry out on a layout is the removal of any non-functional pads (NFPs) or tracks. Figure 19 shows an example of a nonterminated vector, where it is not clear from the design whether this track is a remnant from a previous design iteration, or is an intentional feature.
nonFigure 19: A non-terminated vector is this intentional?
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The fabricator will query every unterminated track, so time can be saved if the designer tells the fabricator which NFPs are intentional. Figure 20 is an example of tracks which may or may not be designed to function as shielding tracks.
NonFigure 20: Non-terminated vectors that may be shielding tracks
Internal pads
In order to provide the best reliability of construction, it is usual for through-holes and vias not to have associated pads on internal layers except where they are actually electrically connected to tracks on the layers. There is, however, a case to be made for the designer setting the CAD program to create such pads automatically, and for the board specification requiring the fabricator to remove unused pads as part of the CAM process. This may appear somewhat bizarre, but having internal pads forces the CAD program to allow sufficient clearance between
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internal copper tracks and through-holes, preventing problems such as that shown in Figure 21.
throughFigure 21: Violation of plated through-hole to copper spacing
Thermal vias
Thermal vias are commonly used to improve heat transfer, and therefore often occur closely spaced. Figure 22 shows an example of poor design, where the net list will show the thermal vias as being connected, whereas the overlap between adjacent thermal vias means that the central vias will be ineffective, because the thermal spoke connection is only 0.0005 inch.
Figure 22: Inadequate thermal pad design
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Note that in this figure it is the copper areas that are shown in black
Autorouting problems
We have already seen from Figure 13 that autorouting may result in specifying areas with tracks and gaps that are too tight. Figure 23 is another example of sub-optimal design; of the three areas highlighted:
A represents a particular problem, where rounding during etching will result in narrowed tracks, but will also create problems when scanning with some AOI machines B shows an unnecessarily tight gap due to auto-routing and no clean-up routine C shows typical same-net spacing violation.
SubautoFigure 23: Sub-optimal design from auto-routing
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The ziggurat effect noted above is just one example of autorouting creating unnecessary problems for the fabricator. In Figure 24 and Figure 25, we see other examples of poor practice, which will produce faults with photoresist and etching.
AutocleanFigure 24: Auto-route requiring clean-up by the designer
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sameFigure 25: Two examples of same-net spacing violations
One of our reviewers commented Anyone who still has an autorouter that produces howlers like these should either invest in a decent auto-router or remember that the A in CAD stands for aided, and not be afraid to route the occasional track manually! But there was a counter-argument from a fabricator who maintained that auto-routing is still a major source of problems: "Although clean-up routines are widely available, these are rarely used to full effect. Most CAD guys I speak with are always pushed for time and tend to be presented with lastminute component changes from the electronics guys. These are incorporated manually, and the final clean-up/DfM checks are operations that are bypassed to save time." In the original email there were many exclamation marks following that final phrase! Note that the CAM will not allow the fabricator to rectify complex errors, which must be returned to the layout designer, incurring delay to the project. However, there are some types of problem with which the fabricator would normally deal, and examples of this are shown in Figure 26. The areas marked would normally be filled, to prevent problems either from acid trapping causing over-etching or from slivers in the photoresist potentially becoming detached during photo-imaging processes in fabrication. Not only do pieces of detached photoresist change the intended pattern, but they can be deposited in unwanted areas. The piece of photoresist will stop the tin etch resist being plated, allowing the etch to eat into the unprotected copper below the resist flakes, and causing opens.
Figure 26: Potential areas for photoresist defects
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Spacing issues
Finally in this section on copper design issues we have to consider some more clearance requirements. For example, Figure 27 has a test pad enclosed within a copper land, and correctly isolated from it, as the net list will demonstrate. However, it lacks the 0.25 mm clearance necessary to ensure maximum first time pass rates at electrical test.
Figure 27: Leave space for electrical test!
Figure 28 shows insufficient clearance between copper tracks and non-plated throughholes of different dimensions. The clearances to copper allowed in this case are 0.05 mm for the small hole and 0.1 mm for the large hole. With drilling inaccuracies of the order of 0.08 mm, the risk of open-circuits is substantial.
Figure 28: Insufficient clearance between NPTH and copper
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Identify as many as possible of the kinds of problems related to copper features that the designer can create for the fabricator. How does the CAD system, in particular the way that auto-routing is used, contribute to these problems? compare your answer with this one [back to top]
Solder mask
As you will know from your studies, there are several different types of solder mask and a number of ways of applying it. However, most solder masks are photoimageable types: both liquid materials (LPISM = Liquid Photo-Imageable Solder Mask) and dry film materials are used, the former being by far the more common. For both types, a layer of material is applied to the entire board surface, dried (if liquid), exposed to ultraviolet light through an artwork, developed and finally cured, leaving just the apertures required in an otherwise impermeable and even coating of solder resist. In practice, as we saw when considering plating thieves, the evenness of coat will depend on the profile of the copper tracks. So the typical capability statement extract in Table 9 gives different coverage thicknesses for the knee and the crest of the track.
Figure 29: Section through resist and track
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Table 9: Solder mask design categories4
dimension 6 gsm dam by wet weight (on FR-4 laminate) min aperture to copper breakdown voltage track coverage knee crest 7 gsm 9 gsm
volume capability no review DfF review 75 m 75 m 75 m 50 m 500 V 3 m 8 m 40 m 1000 V 5 m 12 m
pilot/special 50 m 50 m 50 m < 40 m > 1000 V >5 m > 12 m
In the full Circatex version, this table includes mention of tented, covered and plugged vias. We havent included that topic in this module because tenting needs thick dry film solder mask, which is bad news for fine-pitch assembly. Most people have junked their dry film solder mask laminators, and almost all vias now produced are plugged. The current fashion is for LPISM, with vias plugged by a separate printing operation.
Solder mask apertures

The minimum aperture suggested is 50 m larger than the copper pad which the solder mask surrounds. Whilst not at the limit of attainable accuracy, this is in line with designs using 100 m gaps. The normal recommendation is that the aperture size should be determined by minimum pad-to-pad/track gaps on a design (Figure 30), and that standard apertures be used across the whole of the design.
Figure 30: Solder mask design features
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However, as with line and space characteristics, the designer may opt to generate the solder mask layers as pad to pad and allow the fabricator to adjust for his process. This gives the manufacturer the option of using different oversize openings for different features, and can improve manufacturability by minimising the areas where the tightest registration must be held. Over-large apertures can present particular problems if they expose adjacent copper tracks (Figure 31), because this may lead to unwanted solder pick-up and short-circuits after soldering.
overFigure 31: Effect of over-large solder mask apertures
Figure 32: Effect of over-large solder mask aperture over-
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Clearances
If the assembly operation does not require pocket windows, with a mask dam or webbing between pads, fabricators will often recommend that designers use a gang solder mask window (also known as a postage stamp aperture) around fine pitch devices. The two different types of window are shown in Figure 33, from which it is clear that pocket windows need solder mask that is much better defined and in register than gang windows.
Figure 33: Solder mask window types
This means that, at the bare board level, gang older mask windows will give a higher yield than pocket windows. The gang window can even sometimes be manufactured by screen printing, using a 0.38 mm spacing, whereas solder mask pockets require clearances of 75 125 m, and must therefore be made with photoimageable resist. However, the standard apertures (also referred to as pocket windows) are needed if there are tracks between pads, and some assembly houses prefer the isolation this affords between solder areas. As shown in Figure 34, Circatex have the capability to process webbing down to 50 m, but recommend a minimum width of 75 m.
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Figure 34: Minimum dimensions for solder mask webbing
Two more thoughts about solder resist between pads, which are taken from Materials and Processes for EDR: Dont assume that putting fingers of resist between pads on an otherwise bare board might help overcome bridging, because most bridging occurs between component leads above the board. You are just adding to the cost by using a more expensive process, and gaining little. Omitting mask between chip component pads is also sometimes recommended to reduce drawbridging, and make cleaning easier, though of course this is not possible when tracks are run in the spaces between pads. There are specific problems when solder resist is used to surround the pads for fine-pitch BGAs. With a pad size of 0.2 mm diameter on 0.5 mm pitch, allowing 75 m all round window clearance demanded by the 75 m alignment tolerance is not a problem, because the web between pads will still be 150 m wide. However, the designer may well wish to have some surface tracking: even with 100 m tracks, it is not possible to guarantee that the solder mask alignment will be sufficiently good to cover the track. You will need to negotiate with your fabricator to find an acceptable compromise on size and positional tolerance.
Solder mask problems

A number of processing problems associated with solder mask have their origins in fine features in the design. For example, slivers of material can become detached and move during development, but are not totally removed from the board. The curing process which follows development will then bake the slivers into an inappropriate position,
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perhaps on a pad surface or down a plated through-hole. Either way, the result may be a reject assembly.
Figure 35: Solder resist sliver
Figure 36: Solder resist in through hole
Other things that go wrong are more the fault of the layout designer. For example, all printing and placement machines need a clear view of fiducials in order to have an accurate alignment target, so the solder mask should be cut back from the fiducial as far as possible.
Figure 37: Fiducial (on board fret) with good solder mask clearance
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Provided that the CAM system has the net list information, and is programmed to review interconnections, then the fabricator will be able to detect problems such as that in Figure 38, where there is no solder mask aperture for some SMD pads.
Figure 38: Missing SMD clearance on solder mask
A final caveat concerns keeping solder mask clear of parts that are attached mechanically. For example, if a board is retained by screws, these should act directly onto bare laminate or copper, and not onto a resist-coated surface, so that the resist is not damaged when the screw is tightened.
Figure 39: Keep solder mask away from screws!
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1. Define solder mask ganging and pocket windows and explain under what circumstances you would use each. 2. What sort of problems do assemblers see with solder mask?
compare your answer with this one [back to top]
Additional prints
There are many Design for Fabrication considerations, of which Design for Fewest Processes is one key issue that affects not just the layout designer, but other members of the team. Ask questions such as Do we really need legend? Do we need both score and rout? Bear in mind that scoring will add 50p to the price of a panel, and printing 70p per side. If the process isnt needed, dont pay for it. Alongside design for fewest processes is the absolute need to eliminate all but the most essential special processes, such as via plug, use of peelable resist, gold fingers, and so on. All additional processes cost money, and non-mainstream processes are more expensive. For example, ask whether you really need plugged vias they are not needed to stop solder migration to the top surface.
Legend
Legend inks are available in a variety of colours and may be cured by UV or thermal methods. White is by far the most common colour selected and generally has the best contrast to the common masks in use. Other available colours are yellow, red, orange and blue. As with non-standard mask colours, a premium may be charged for non-standard legends, depending on the volume of the application.
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Legend ink should be kept as far as practicable away from the copper features on a PCB, as indicated in Table 10:
Table 10: Legend (nomenclature) design categories
dimension Minimum line width Minimum aperture (to copper)
volume capability no review DfF review 200 m 300 m 150 m
pilot/special 150 m <150 m
If there is contention between legend and other mask features, as in the top image of Figure 40, where the legends impinge on copper and solder mask, the fabricator will crop the legend as shown in the middle image. The final image shows the preferred starting point, which needs no correction.
Figure 40: Options for legend prints
One also has to bear in mind that screen printing is associated with fairly loose tolerances, both in positioning the print and because the ink tends to flow. Features such as lines surrounding pads to indicate component position should therefore be kept well clear of any solderable pads. Also, bearing in mind that legend prints have a third dimension, and are not totally flat, designers should not position legend under chip components, in order to avoid the possibility of drawbridging.
Figure 41: Incorrect component identification
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Peelable solder resist

Peelable resist is one of the thickest materials ever printed onto a board! Intended to withstand immersion during wave soldering, it is then removed by hand in order to reveal unsoldered pads intended for non-wet assembly.
Figure 42: Removing peelable solder mask
As shown in Table 11, the definition of peelable solder mask print is not very good, but, because the material is thixotropic, it can be used successfully to tent even quite large vias.
Table 11: Peelable solder resist design categories
dimension min. gap resist to copper min. resist width max. tented hole size min. resist coverage
volume capability no review DfF review 300 m 3 mm 1.6 mm 300 m
pilot/special 250 m 2 mm 1.8 mm 250 m
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colour
green/blue
white
Edge connector plating

Another process carried out towards the end of manufacture is the plating of edge connectors. Electroless nickel and immersion gold are both inadequate materials for surfaces that will be subjected to continued rubbing, so electrolytic nickel and hard gold are used. This process requires that the areas to be plated are electrically connected to the cathode of the plating circuit, so a shorting bar is used, as indicated in Figure 43 (left).
Figure 43: Making electrical contact to gold-plated edge connectors gold-
Although the process may be continuous, in order to reduce the amount of gold used, most baths for this process immerse only part of the board. The panel layout therefore has to locate the edge connectors at opposite edges, as shown in Figure 43 (right), so that the board can be cut in half before plating. To reduce still further the usage of gold, areas not designed to be plated will be covered with a temporary plating resist. An alternative approach preferred by some fabricators is to carry out the deep nickel/gold plating of areas for edge connectors, key pads, slip rings, and similar between the first drill and electroless copper/direct metallisation process steps. The plated areas are then protected by resist during much of the subsequent processing. This adds process and equipment complexity, but allows a much greater proportion of the panel to be used, and may be the cheaper option when quantities are high. As always, any requirement for electroplated nickel/gold should be discussed with your fabricator at an early stage in design.
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[back to top]
Finishing steps
Testing
Final steps in manufacture include testing to ensure correctness of interconnection, and scoring and/or routing to define the board outline. The probing aspects are considered under Design for Test, but the practicalities of test should be borne in mind especially during panelisation. Although each of the three circuits making up the panel in Figure 44 is testable on its own, as panellised there is a small area (surrounded by the yellow rectangle) where the density of 0.050 inch connections exceeds the probing capabilities of the equipment. This means that the board cannot be tested completely in a single pass, which adds cost.
Figure 44: A problem for electrical test!
Note that, had the left-hand side circuit been rotated through 180, the panel could have been tested in one operation. Unfortunately, this proposal for reducing cost could not be implemented, since all the other manufacturing fixtures had already been made. This is a small example of how much of the cost of a product is determined by decisions made early in the development life-cycle, a point we made in our very first unit. Where impedance is important, it is also necessary to include coupons for TDR (time domain reflectrometry) test. These coupons are placed at 90 to each other, as shown in Figure 45, to ensure that all process variables are taken into account. Note that the fabricator will keep the coupons with the board to which they relate, even after the routing operation, until final measurements have verified that the impedances are correct.
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Figure 45: TDR test coupons
Depanelling
Most smaller circuits are shipped to the customer in panels from which individual circuits will be broken. Separation can be effected by pre-scoring during fabrication, and then snapping after assembly, or by routing at the end of fabrication, leaving some break-off tabs to allow the assembler to press or snap the sub-units apart. This is not without risk, especially to chip ceramic capacitors, as has been pointed out in Materials and Process for EDR! The common problem experienced by fabricators when sub-panels are requested is simply lack of sufficient information: missing step-and-repeat details and a drawing there are many ways of arranging even a six-up sub-panel! what tooling holes are required? missing fiducial positions is the board to be V-scored or routed? if routed: how many break-offs are required? what is the intended diameter of the router cutter? if V-scored: is there enough clearance from tracks to edge?
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V-score requirements
Figure 46 is a PCB end view cross-section showing the V-score cut into the material before separation. The clearance indicated, which is typically 1.0 mm minimum, is to prevent the copper tracks from being damaged during the scoring process. Figure 47 shows a plan view of a representation of the board: the red stripe down the centre shows the keep-out area for any copper features or components.
crossVFigure 46: Schematic cross-section of the V-score cut
VFigure 47: Copper tracks too close to V-score
Beware that scoring is prone to run-out, where the score is not parallel to the circuit, although a typical specification is that scores should be parallel to board edge to within 0.15mm.
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The score depth depends on the board thickness, and the figures for the thickness of the residual material shown in Table 12 have been selected to get good breakout:
Table 12: Recommended score depth as a function of board thickness
Thickness Residual (D)
0.80 mm 0.25 mm 0.05 mm
1.00 mm 0.35 mm 0.1 mm
1.20 mm 0.35 mm 0.1 mm
1.60 mm 0.40 mm 70.1 mm
Note that, when the scored panel is broken up into individual boards, the size of the boards is greater than might be expected. This increase, illustrated in Figure 48, depends on where the actual break occurs, and on the geometry of the cutting blade used to separate the boards. For 1.6mm boards, the typical web thickness W is 0.3mm, and the extension k is 0.10.15mm. Where scoring affects both sides of the board, the total increase in board dimension will be 2k, or 0.20.3mm.
Figure 48: Dimensional increase due to scoring
Routing
Routing is more expensive than V-scoring, but generally more accurate, and results in a vertical profile. With profiling, remember that a small radius on an internal corner means using a smaller diameter drill for the whole routing process, with increased costs due to breakage and quality issues. Particularly if your design has sections removed by internal routing, try and use wide radius corners.
Figure 49: View of a routed profile, showing rounded end and vertical sidewalls
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Also remember to provide some weak points, so that each element will break away cleanly from the panel! By drilling small holes slightly inside the outline, as shown in Figure 50, the board can be encouraged to break at modest flexural stress, and the rough edges of the break can be kept within the boundary of the profiled board.
Figure 50: Break-out tab design Break-
BreakFigure 51: Break-out tab on a board
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Clearances are important for post-assembly routing and for the in-board chamfers used to accommodate standard edge connectors. Figure 52 suggests a 3.0mm minimum clearance at both sides to accommodate the over-run of the cutter: smaller clearances will require hand finishing.
Figure 52: Clearance required for in-board chamfers in-
1. Explain why it is important to place silkscreen legend without contention with the copper features. 2. What are the requirements of a fabricator when you are specifying sub-panels?
compare your answer with this one [ back to top ]
22/10/2010

PCB Design For Fabrication Issues

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PCB Design For Fabrication Issues

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Design for Fabrication issues

Design for Fabrication issues

inches 24 14 24 18 24 20 24 21 24.4 14 24.4 21 25.2 14* 25.2 21*

* Only use after consultation ** Double-sided only

Design for Fabrication issues

doubleTable 2: Margins required for double-sided product

margin between circuit and

reason for margin

Design for Fabrication issues

bottom of panel top of panel left of panel right of panel

photomech resist placement 14.6 14 13.6 8

plating rail rout LPISM 21 15 20 12 10 10 115 20 10 10 13.6 13.6

Design for Fabrication issues

Self Assessment Questions

Design for Fabrication issues

Symmetrical and balanced build

Design for Fabrication issues

Design for Fabrication issues

Design for Fabrication issues

Self Assessment Question

Design for Fabrication issues

hole size 0.25 mm <0.4 mm 0.4 mm

volume capability no review DfF review 6:1 7:1 7:1 8:1 11 : 1 12 : 1

pilot/special 10 : 1 panel thickness dictated

Design for Fabrication issues

being determined by the fluid dynamics of the plating processes.

aspect ratio 2.5 : 1 2:1 3.2 : 1 5.33 : 1 8:1 10.7 : 1 8:1 10 : 1

pilot/special 0.20 mm <25 m <50 m <150 m <100 m 170% 135%

Design for Fabrication issues

2 oz hole roughness countersunk holes counter-bored holes second drill tolerance

135% 35 m yes yes 200 m

125% <35 m 100 m

Design for Fabrication issues

Hole density and clearance

Design for Fabrication issues

SingleSingle-sided plated holes

Design for Fabrication issues

Self Assessment Questions

Inner copper layers

Track width and spacing

Design for Fabrication issues

Design for Fabrication issues

Copper balancing on internal layers

Design for Fabrication issues

before copper balancing

the same layer plus copper balancing

Design for Fabrication issues

Outer copper layers Track width and spacing

Design for Fabrication issues

(min. average) min. a/r for tangency

Copper balancing on external layers

Design for Fabrication issues

Design for Fabrication issues

Difficult to plate evenly due to isolated tracking

Solution: Robbing added in an attempt to even out copper distribution

Self Assessment Questions

compare your answer with this one [back to top]

Other copper design issues

Design for Fabrication issues

Removal of non functional pads and tracks

Design for Fabrication issues

Design for Fabrication issues