A Vocational Training Report in SCIENTECH LEARNING CENTRE INDORE (M.

P)
Submitted In partial fulfillment of requirement for the award of degree Of

Bachelor of Engineering in Branch To Chhattishgarh Swami Vivekanand Technical University, Bhilai In Session: 2010- 2011

Submitted by:

SHASHANK DEKATE
B.E., 7thSemester/ 4thYear

DEPARTMENT OF ELECTRONIC AND TELECOMMUNICATION

Chhatrapati Shivaji Institute of Technology

[ISO 9001:2008 Certified & NBA Accredited] Balod Road, Durg. C.G. Pin: 491001

ACKNOWLEDGEMENT
I express humble gratitude to all the people associated with my training. The completion would have been a distant dream without their support. It is my privilege to have such intellectual people at our side and we thank everybody with humble regards. The valuable suggestions, guidelines , tips and conceptual brief ups propelled us through rough waters which hindered us during this training duration. Critical views and appreciations were the driving force behind my determination and honesty towards this training program. Some of the prominent hands behind our training completion are of Mr. Mangal Singh (HOD ET&T Department) and the entire college community and basically the training and placement department. Thanking you

CERTIFICATE

This is to certify that MR. SHASHANK DEKATE Roll No.3032808081 Semester 5th Branch ELECTRONIC AND TELECOMMUNICATION student of Chhatrapati Shivaji Institute of Technology, Durg has undergone his/her Vocational Training in SCIENTECH LEARNING CENTRE, INDORE (M.P) at From 30/05/2011 to 25/06/2011

Head of Department (ET&T Depts) CSIT, Durg

Date:30/07/2011 Place: Durg

TABLE OF CONTENTS:-

1. INTRODUTION ON VLSI 2. FLOW CHART 3. VHDL 4. VERILOG 5. FABRICATION PROCESS OF IC

INTODUCTION:Vlsi is the process of creating integrated cricuits by combining thousands of transistors based circuits into a single chip.It is nothing but a level of integration. Sources disagree on what is measured (gates or transistors?) SSI Small-Scale Integration (0-102) MSI Medium-Scale Integration (102 -103) LSI Large-Scale Integration (103 -105) VLSI Very Large-Scale Integration (105 - 107) ULSI Ultra Large-Scale Integration (>= 107)

ADVANTAGE:1. 2. 3. 4. 5. 6. 7. Compactness. Mobility. Reliability. Less power consumption. Effective use of space. Easily available productivity. Large market background.

DISADVANTAGE:1. Previously the cost was high 2. Still the basic things like mobile phones and other related things are cheaper but high end products are pocket eater 3. Advancement in Indian market is required 4. Lack of training institute so affects on production in India

APPLICATION- Daily life prospective

1. 2. 3. 4. There are so many applications in our daily life. From a simple mobile phone to the server used in large companies. Recent example is Intel's new upcoming 45 nm integration processor The low power design in VLSI is upcoming trend in this industry

VLSI

FRONT END

BACK END

VHDL

VERILOG

FABRICATION OF IC

INTRODUCTION:In 1980s rapid adavance in integrated circuit tecnology lead to effect to develop standard design practices for digital ckt. VHDL was develop as a part that effect. VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High SpeedIntegrated Circuits). It is a hardware description language that can be used to model a digital system at many levelsof abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system beingmodeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. Thedigital system can also be described hierarchically. Timing can also be explicitly modeled in the same description. VHDL is a complex, sophisated language. VHDL was originally intended to serve two main purpose. First, it was used as documentation language for describing the structure of complex digital circuit. Second, VHDL provided features for modelling the behaviour of digital circuit, which allowed its use as input to software program that were then used to simulate the circuits operation.

HISTORY AND DEVELOPMENT:The requirements for the language were first generated in 1981 under the VHSIC program. In this program, a number of U.S. companies were involved in designing VHSIC chips for the Department of Defense (DoD). A team of three companies, IBM, Texas Instruments, and Intermetrics, were first awarded the contract by the DoD to develop a version of the language in 1983. Version 7.2 of VHDL was developed and released to thepublic in 1985. There was a strong industry participation throughout the VHDL language development process, especially from the companies that were developing VHSIC chips. After the release of version 7.2, there was an increasing need to make the language an industry-wide standard. Consequently, the language was transferred to the IEEE for standardization in 1986. After a substantial enhancement to the language, made by a team of industry, university, and DoD representatives, the language was standardized by the IEEE in December 1987; this version of the language is now known as the IEEE Std 1076-1987. The official language description appears in the IEEE Standard VHDL Language Reference Manual made available by the IEEE. The language described in this book is based on this standard. The language has since also been recognized as an American National Standards Institute (ANSI) standard. The Department of Defense, since September 1988, requires all its digital Application-Specific Integrated Circuit (ASIC) suppliers to deliver VHDL descriptions of the ASICs and their subcomponents, at both the behavioral and structural levels. Test benches that are used to validate the ASIC chip at all levels in its hierarchy must also be delivered in VHDL.

VHDL DESIGN ENTITY:-

ENTITY

ENTITY DECLARATION

ARCHITECTURE

THE GENERAL STRUCTUREOF A VHDL DESIGN ENTITY

ENTITY DECLARATION:The input and output signal in an entity are specified using the ENTITY decleration. Syntax :ENTITY entity_name IS PORT([SIGNAL]signal_name{,signal_name}:[mode] type_name {; [ SIGNAL]signal_name{,signal_name}:[mode] type_name } ); END entity_name;

ARCHITECTURE :An ARCHITECTURE provide the circuit detail for an entity. Syntax:ARCHITECTURE architecture_name OF entity_name IS [SIGNAL declarations] [COSTANT declaration] [ TYPE declaration] [ COMPONENT declarations]

[ ATTRIBUTE specification] BEGIN {COMPONENT instantiation statement;} {CONCURRENT ASSIGNMENT statement;} {PROCESS statement;} {GENERATE statement;} END [architecture_name];

SIGNAL DECLARATION:An object belonging to the signal class has a past history of values, a current value, and a set of future values. Future values can be assigned to a signal object using a signal assignment statement. Signal objects can be regarded as wires in a circuit. Signal objects are typically used to model wires and flip-flops. FOR EXAMPLE :signal CLOCK: BIT; signal DATA_BUS: BIT_VECTOR(0 to 7); signal GATE_DELAY: TIME := 10 ns; The interpretation for these signal declarations is very similar to that of the variable declarations. The first signaldeclaration declares the signal object CLOCK of type BIT and gives it an initial value of '0' ('0' being the leftmostvalue of type BIT). The third signal declaration declares a signal object GATE_DELAY of type TIME that has aninitial value of 10 ns.

CONTANT DECLARATION:An object of constant class can hold a single value of a given type. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation. constant objects are analogous to their counterparts in a high-level programming language like C or Pascal. constant objects are typically used to model the behavior of the circuit. FOR EXAMPLE :constant RISE_TIME: TIME := 10ns; constant BUS_WIDTH: INTEGER := 8: The first declaration declares the object RISE_TIME that can hold a value of type TIME (a predefined type in thelanguage) and the value assigned to the object at the start of simulation is 10 ns. The second constant declaration declares a constant BUS_WIDTH of type INTEGER with a value of 8.

TYPE DECLARATION:A subtype is a type with a constraint. The constraint specifies the subset of values for the type. The type is called the base type of the subtype. An object is said to belong to a subtype if it is of the base type and if it satisfies the constraint. Subtype declarations are used to declare subtypes. An object can be declared to either belong to a type or to a subtype. The set of operations belonging to a subtype is the same as that associated with its base type. Subtypes are usefulfor range checking and for imposing additional constraints on types.

Examples of subtypes are subtype MY_INTEGER is INTEGER range 48 to 156 ; type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ; subtype MIDDLE is DIGIT range '3' to '7' ; In the first example, MY INTEGER is a subtype of the INTEGER base type and has a range constraint with values ranging from 48 through 156. DIGIT is a userdefined enumeration type. The last subtype declaration declares a new subtype called MIDDLE whose base type is DIGIT and has the values '3', '4', '5', '6' and '7'. A subtype need not impose a constraint. In such a case, the subtype simply gives another name to an already existing type. For example: subtype NUMBER is DIGIT; NUMBER is a subtype with no constraint. Therefore, its set of values are the same as that for type DIGIT.

COMPONENT DECLARATION:It uses syntax similar to to that of entity decleration. This statement allow the entity to used as component (subcircuit) in the architecture body. Synatax:COMPONENT component _name IS PORT([SIGNAL]signal_name{,signal_name}:[mode] type_name {; [ SIGNAL]signal_name{,signal_name}:[mode] type_name } ); END component _name;

PROCESS STATEMENT :-

A process statement contains sequential statements that describe the functionality of a portion of an entity in sequential terms. The syntax of a process statement is process [ ( sensitivity-list ) ] [process-item-declarations] begin sequential-statements; these are variable-assignment-statement signal-assignment-statement wait-statement if-statement case-statement loop-statement null-statement exit-statement next-statement assertion-statement procedure-call-statement return-statement. end process [ process-label];

COMPONENT INSTANTIATION:A component instantiation statement defines a subcomponent of the entity in which it appears. It associates the signals in the entity with the ports of that subcomponent. A format of a component instantiation statement is component-label: component-name port map ( association-list) ', The component-label can be any legal identifier and can be considered as the name of the instance. The component-name must be the name of a component declared earlier using a component declaration. The association-list associates signals in the entity, called actuals, with the ports of a component, called locals. An actual must be an object of class signal. Expressions or objects of class variable or constant are not allowed. An actual may also be the keyword open to indicate a port that is not connected.

GENERATE STATEMENT:It is often useful to pass certain types of information into a design description from its environment. Examples of such information are rise and fall delays, and size of interface ports. This is accomplished by using generics. A generic declares a constant object of mode in (that is, the value can only be read), and can be used in the entity declaration and its corresponding architecture bodies. The value of this constant can be specified as a locally static expression in one of the following: 1. entity declaration 2. component declaration 3. component instantiation 4. configuration specification 5. configuration declaration The value of a generic must be determinable at elaboration time, that is, a value for a generic must be explicitly specified at least once using any of the ones mentioned.

CONCURRENT STATEMENT:One of the primary mechanisms for modeling the dataflow behavior of an entity is by using the Concurrent assignment statement. Signal assignment statements that appear outside of a process are called concurrent signal assignment statements. Concurrent signal assignment statements are event triggered, that is, they are executed whenever there is an event on a signal that appears in its expression architecture CON_SIG_ASG of FRAGMENT2 is begin -- Following are concurrent signal assignment statements: A<=B; Z<=A; end; In architecture CON_SIG_ASG, the two statements are concurrent signal assignment statements. When an event occurs on signal B, say at time T, signal A gets the value of B after delta delay, that is, at time T+.. When simulation time advances to T+., signal A will get its new value and this event on A (assuming there is a change of value on signal A) will trigger the second signal assignment statement that will cause the new value of A to be assigned to Z after another delta delay, that is, at time T+2.. The delta delay model is explored in more detail in the next section.

PACKET DECLARATION:A package declaration is used to store a set of common declarations like components, types, procedures, and functions. These declarations can then be imported into other design units using a context clause. Here is an example of a package declaration. package EXAMPLE_PACK is type SUMMER is (MAY, JUN, JUL, AUG, SEP); component D_FLIP_FLOP port (D, CK: in BIT; Q, QBAR: out BIT); end component; constant PIN2PIN_DELAY: TIME := 125 ns; function INT2BIT_VEC (INT_VALUE: INTEGER) return BIT_VECTOR; end EXAMPLE_PACK; The name of the package declared is EXAMPLE_PACK. It contains type, component, constant, and function declarations. Notice that the behavior of the function INT2BIT_VEC does not appear in the package declaration; only the function interface appears. The definition or body of the function appears in a package body Assume that this package has been compiled into a design library called DESIGN_LIB. Consider the following context clauses associated with an entity declaration. library DESIGN_LIB; use DESIGN_LIB.EXAMPLE_PACK.all; entity RX is . . .

PACKET BODY:A package body is primarily used to store the definitions of functions and procedures that were declared in the corresponding package declaration, and also the complete constant declarations for any deferred constants that appear in the package declaration. Therefore, a package body is always associated with a package declaration; furthermore, a package declaration can have at most one package body associated with it. Contrast this with an architecture body and an entity declaration where multiple architecture bodies may be associated with a single entity declaration. A package body may contain other declarations as well Here is the package body for the package EXAMPLE_PACK declared in the previous section.

package body EXAMPLE_PACK is function INT2BIT_VEC (INT_VALUE: INTEGER) return BIT_VECTOR is begin --Behavior of function described here. end INT2BIT_VEC; end EXAMPLE_PACK;

The name of the package body must be the same as that of the package declaration with which it is associated. It is important to note that a package body is not necessary if the corresponding package declaration has no function and procedure declarations and no deferred constant declarations.

INTRODUCTION:Verilog has a number of constructs similar to C programming language. Verilog allow the designer to represent circuit in two fundamentally different ways. One possibility is to use verilog constructs that represent simple circuit element such as logic gates or even transistors. A larger circuit is defined by writing code that connects such elements together. This is referred to as the structural reprentation of logic circuits. The second possibility is to describe a circuit by using logic expression and programming constructs that define the behaviour of the circuit but not its actual structure in term of gates. This is called the behavioral representation. Verilog was originally intended for simulation and verification of digital circuit.

HISTORY AND DEVELOPMENT:The original version of Verilog was developed by gateway design automation, which was later acquired by cadence design system. In 1990 Verilog was put into public domain, and it has since became the most poular for describing digital cricuit. In 1995 Verilog was abdopted as an IEEE Standard, called 1364-1995. An enhanced version of Verilog, called Verilog 2001, was adopted as IEEE Standard 1364-2001 in 2001. While this version introduced a number of new feature, it also support all the feature in the feature in the original Verilog standard.

A circuit or subcricuit described with the verilog code is called a module.

module moudle_name[(port_name{,port_name})]; [parameter declaration] [input declaration] [output declaration] [inout declaration] [wire or tri declaration] [reg or integer declaration] [function or task declaration] [assign continous assignment] [initial block] [always block] [gate instantiations] [module instantiations ] endmodule

PARAMETER DECLARATION:We can make code more general by introducing a parameter. Verilog allows parameter, such as delay, to be associated with continuous assignments. For example:Parameter n=4; Wire #2c; Assign #5c = x & y; This code specifies that two time units of delay are incurred on the wire c in addition to five time units for the AND gate that produces x & y.

INPUT DECLARATION :we design a chip, for that chip how many input are required, all that input are given here. for ex:input x,y; x,y now act as input.

OUTPUT DECLARATION :we design a chip, for that chip how many output are required, all that output are given here. for ex:output x,y; x,y now act as output.

INOUT DECLARATION :Inout are bidirectional and can be scalar or vector. For ex :inout [3:0]bus ;

WIRE OR TRI DECLARATION :For specifying that are neither input output of the module, which are used for internal connection with in the module, Verilog provide the wire type. For example :Wire [3:1]c;

INTEGER OR REG DECLARATION :Verilog provide variable to allow a circuit to be described in term of it behavior. A variable can be assigned a value in one Verilog statement, and it retains this value untill it is overwritten by subsequent assignment statement. Ther two type of variable is used reg and integer. Such variable are useful for decribing a circuit s behavior; they do not usually correspond directly to signal in the resulting circuit. For ex:integer k ;

FUNCTION AND TASK DECLARATION:Verilog function which has a general form Function [range\integer] function_name; []input declaration] [Parameter,reg,integer declaration] begin Statement; end end function

The purpose of a function is to allow the code to be written in a modular fashin without defining separate modules. A function is defined with in module and its called either in a continuous assignment statement inside that module. A function can have more than one input, but it does not have any have an output because the function name it self serves as the outpu variable.

CONTINOUS ASSIGNMENT:While gate installation allow the description of the circuits structure, continuous assignment statement permit the description of the circuit function. The general form of this statement is assign net_assingment{,net_assingement};

ALWAYS BLOCK:An always block is a construct that contain one or more procedural statement it has a form always @ (sensitivity_list) begin [procedural assingnment statement] [if-else statement] [case statement] [while,repeat and for loops] [task and function calls] end The sensitivity_list is a list of signal that directly affect the output result generated by the always block. A value assigned to variable with a procedural assignment statement. There are two type of assignment: Blocking assignment denoted by = symbol and non blocking assignment denoted by <= symbol.

INITIAL BLOCK:For simulation purpose, Verilog also provide the initial construct. The initial and always construct have the same, form, but statement inside the initial construct executed only ones, at the start of simulation.

Fabrication Steps:-

Polysilicon Refining

Crystal Pulling

Wafer Slicing & Polishing

Oxidation

Etch

Lithography

Photoresist

Strip Photoresist

n-well

Strip Oxide

Self-Aligned Process

Polysilicon Patterning

Polysilicon

Diffusion

Contacts

Metallization

POLYSILICON REFINING:Chemical Reactions Silicon Refining: SiO2 + 2 C Si + 2 CO Silicon Purification: Si + 3 HCl HSiCl3 + H2 Silicon Deposition: HSiCl3 + H2 Si + 3 HCl Reactants H2 Silicon Intermediates H2SiCl2 HSiCl3

CRYSTAL PULLING:Process Conditions:Flow Rate: 20 to 50 liters/min

Time: 18 to 24 hours Temperature: >1,300 degrees C Pressure: 20 Torr Materials Polysilicon Nodules *Ar *H2

WAFER SLICING & POLISHING:The silicon ingot is sliced into individual wafers, polished, and cleaned.

DIMENSIONS OF THE SILICON WAFER:-

OXIDATION: Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation Furnace.

SiO2 p-substrate

PHOTORESIST: Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO2 p-substrate

LITHOGRAPHY: THE WAFER STEPPER:The mask is imaged on a photosensitive film (photoresist) that coats the wafer and then the wafer is scanned (stepped) to the next position. Expose photoresist through n-well mask Strip off exposed photoresist

ETCH: Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

STRIP PHOTO RESIST: Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesnt melt in next Step

N-WELL: n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

STRIP OXIDE: Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

POLYSILICON: Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of siliconlayer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

POLYSILICON PATTERING: Use same lithography process to pattern Polysilicon

SELF ALIGNED PROCESS: Use oxide and masking to expose where n +dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

N-DIFFUSION:Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

N-DIFFUSION CONT: Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

Strip off oxide to complete patte

rning step

P-DIFFUSION: Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

CONTACTS: Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

METALLIZATION: Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

CONCLUSION
The conclusion is that I got from this project is that from every aspects this project is technically faceable and valuable and useful.We gathered alot of practial knowledge with the help of this training.

RESULT
I got from this training is that this project is knowledgeable ad commercially its valuable and useful.We gained alot of therotical as well as pratical knowledge with the help of this training.

RECOMMENDATION:I get recommondation to join Scientech learning center from my friends and seniors because of their good guidance I greatfully completed my training.

INTRODUCTION ABOUT COMPANY

SCIENTECH TECHNOLOGIES PVT.LTD. (SCIENTECH LEARNING CENTER)

Founded in 1983, SCIENTECH TECHNOLOGIES PVT. LTD. started as a Test & Measurement Instruments manufacturing & marketing company. Today, organizational infrastructure extends beyond Test & Measurement, having grown into a renowned Provider of World-Class Technical Training Equipments and Training Solutions as well. Scientech maintains close links with the world of Education and Training. Today, we are the leading manufacturers, exporters and importers of Electr Scientech Learning Centre is the Training Division of Scientech Technologies Pvt. Ltd., a leading company in the field of Design, Manufacturing and Marketing of Electronic Test & Measuring Instruments and Technology Training products for Industry. Scientech Learning Centre was been established in January 2007, with a mission to Bridge the Gap Between Education and Industry by imparting Hands-on Training in various Skills , thus enabling students to become Readily Employable in the Industry.The TRAINING is conducted within HIGH-TECH Electronic Manufacturing Factory premises, making it totally application oriented. A number of there products are already in use in the labs in the Engineering Institutions , and this training will help the students to assimilate instructions in the college better

REFRENCES:BOOKS
1. Stephan Brown 2. Zvonko Vranesic 3. Bhaskar

WEBSITE
1.www.latticesemi.com 2.www.altera.com 3.www.xilinx.com