STUDY GUIDE FOR

DIGITAL ELECTRONIC DESIGN

EDG780
Compiled by S Sinha, J Schoeman, & Dr T-H Joubert 2009 University of Pretoria

1 Lecturers and departmental administrator

Primary Lecturer: Office: Saurabh Sinha Make an appointment via email CEFIM Main Campus University of Pretoria
*Ideally email me with the question; if we cannot resolve over email, we can meet in person.

Mail address:

Telephone: Fax number: *E-mail address: Secondary Lecturer: Office:

Dept. of Electrical, Electronic and Computer Engineering University of Pretoria Pretoria 0002 +27 12 420 3794 (Dept. Administrator) 086 684 0588 (first attempt) or +27 12 362 5115 ssinha@ieee.org Johan Schoeman Make an appointment with Dept. Administrator CEFIM Main Campus University of Pretoria Dept. of Electrical, Electronic and Computer Engineering University of Pretoria Pretoria 0002 +27 12 420 3794 (Dept. Administrator) +27 12 362 5115 johan.schoeman@eng.up.ac.za By appointment only Mrs T. Loubser Room 2-11 CEFIM Main Campus University of Pretoria Dept. of Electrical, Electronic and Computer Engineering University of Pretoria Pretoria 0002 +27 12 420 3794 +27 12 362 5115 tilla.Loubser@up.ac.za Office hours (by appointment only)

Mail address:

Telephone: Fax number: E-mail address: Consulting hours: Dept. Administrator Office:

Mail address:

Telephone: Fax number: E-mail address: Consulting hours:

Guest Lecturer(s): The CSIR will be partly involved with our delivery for this module. For more information on their works, please see: http://www.csir.co.za/contacts.html Business unit: Defence Peace Safety & Security (DPSS) Mr Casper van Zyl is the person that will be responsible for this, for his details: Telephone: +27 12 841 3374 E-mail address: cvzyl@csir.co.za For maps to DPSS, CSIR (Main site, Pretoria campus): http://www.csir.co.za/roadmaps.html While attending classes at the CSIR, please meet at the reception (DPSS (Building 44)).

2 References
Prescribed textbooks
TITLE 1) High-Speed Digital Design: A Handbook of Black Magic 2) CMOS Digital Integrated Circuits Analysis & Design AUTHOR Howard W. Johnson & Martin Graham Sung-Mo Kang & Yusuf Leblebici PUBLISHER Prentice Hall McGraw-Hill ISBN 978-0133957242 978-0072460537

Recommended textbooks Jan M. Rabaey, Digital Integrated Circuits : A Design Perspective, Prentice Hall, 1996. Wayne Wolf, Modern VLSI Design: Systems on Silicon 2nd Ed. , Prentice Hall, NJ, 1999. Stefan Sjoholm & Lennart Lindh, VHDL for Designers, Prentice Hall, 1997. Jan M Rabaey, Digital Integrated Circuits: A Dsign Perspective, Prentice Hall, 1996. Pucknell & Eshragian, Basic VLSI Design, Prentice Hall, 1994. Uyemura, Fundamentals of MOS Digital Integrated Circuits, Addison Wesley, 1988. Victor P Nelson, H Troy Nagle, Bill D Carrol, J David Iwin, Digital Logic Circuit Analysis & Design, Prentice Hall, 1995.

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Recommended software and training 1 SPICE circuit simulator for up to Level 7 device models. For instance, http://www.tanner.com/EDA/ (a demo version is available) Other alternatives: http://cgi.www.catena.uk.com (Catena) http://www.linear.com/company/software.jsp (LTSpice/SwitcherCAD III) http://www.ee.up.ac.za/~subjects/files/ENE310/OrCAD_Demo_160.zip (~716 Mb) The University of Pretoria has limited licences available for the full version - OrCAD (SPICE) and Tanner Tools:
http://www.ee.up.ac.za/~subjects/files/EPR400_uE/Installing%20OrCAD%20on%20the%20UP%20network.pdf http://www.ee.up.ac.za/~subjects/files/EPR400_uE/Tanner_Installation.pdf

2 Mask layout editor that can generate GDSII format data. Once again, http://www.tanner.com/EDA/ 3 VHDL simulator, place-and route software for FPGA, and FPGA programmer. Recommended journals IEEE Journal of Solid State Circuits. IEEE Transactions on Circuits and Systems II.
Should you not be a member of the IEEE, you may join: www.ieee.org/join If you do not wish to use your credit card for joining, please download an alternative payment mechanism: http://www.ee.up.ac.za/~subjects/files/EPR400_uE/ieee_reg.doc (57.86 kb)

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3 Course objectives and study themes

Introduction Abstraction in digital design leads to a hierarchy of levels ranging from semiconductor devices to systems. The two traditional approaches in handling this large range are systems design or the "topdown" approach, and circuit design or the "bottom-up" approach. The emphasis in this digital design course is on the common ground between these two digital design approaches, requiring some detail from both of the traditional perspectives. Course Objective The objective of this course is to ensure that the student has a fundamental understanding of the design process for electronic digital design over several levels of design abstraction. The student must learn the ability to apply correct methodology to problems associated with digital design from the circuit to the system level. The following is valid for this course: NQF Level: 7 Field: 6 Sub-Field: Engineering Learning assumed to be in place: Learning required for a BEng or BSc-degree, with background in logic design and electronic components. Range statement: Suitable for students busy with an Honours or Masters degree in electronic engineering, or an Honours or Masters degree in Science. Study themes Five themes cover the contents for this course: Design methodology, Design strategy, Digital circuit design, Digital system design, and Interconnection and termination design.

Theme 1 : Design methodology

Objective At the end of this section you must be able to discuss and apply aspects of the methodology used in complex digital design. Outcomes Give an overview of digital VLSI design styles; Discuss the design flow used for digital design; Explain why hierarchic design is used in complex digital designs, referring to concepts like: regularity, modularity, locality; Discuss abstraction and modelling in digital design, referring to the following levels: specification, behavioural,

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register-transfer, logic, circuit, layout;

Draw a diagram depicting the design cycle used in digital design, including steps for Design specification, design capture' design verification, design testing; Describe current practice in design automation (CAD). Reference Kang & Leblebici, Chapter 1.

Theme 2 : Design strategy

Objective At the end of this section you must be able to discuss and apply strategies used in the design of digital system implementations. Outcomes Discuss the aspects that impact on the choice of level of integration for a digital design. Consider discrete logic level, programmable logic level, including FPGA's ASIC level, custom IC level; Discuss the aspects that impact on the choice of design style for a digital design. Consider synchronous vs. asynchronous design style, static design style, dynamic design style; Discuss the aspects that impact on the choice of integration technology for a digital design. Consider CMOS technology, bipolar technology, GaAs technology, BiCMOS technology, Low temperature and superconductive technology. References Kang & Leblebici, Chapter 2 & 12; Nelson, Nagel et al, Chapter 5; Rabaey, Chapter 5; and Pucknell & Eshragian, Chapter 12.

Theme 3 : Digital circuit design

Objective At the end of this section you must be able to analyse and design digital circuits, with emphasis on CMOS technology. Outcomes Describe the structure and model of MOS transistors, and the process require for manufacturing. Discuss the classification of digital circuit techniques.

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Analyse and design inverters, considering the following aspects: Static transfer characteristics, Switching characteristics. Analyse and design digital circuits and subsystems using the following circuit techniques: static combinational logic, pseudo NMOS logic, DCVSL logic, domino and zipper logic, transmission gate logic, single phase dynamic logic, two-phase dynamic logic; Describe and (analytically and experimentally) extract the following performance measures: speed, power, noise margins; Design sticks diagram layouts for digital circuit designs. Capture and verify digital circuit mask layouts. Design combinational logic networks and sequential machines in the context of IC design. Design the circuit diagrams of important digital subsystems. Reference Kang & Leblebici, Chapters 2, 3, 4, 5 ,6 7, 8, 9.

Theme 4 : Digital system design Objective At the end of this section you must be able to analyse and design complex digital systems. Outcomes Describe low-power design techniques. Describe chip interface circuits. Discuss design for manufacturability. Discuss design validation and design for testability. Discuss the following architecture issues: floorplanning, partitioning, interconnect, power rail distribution; timing and scheduling, clock generation and distribution; Describe the components of typical digital design CAD systems: describe logic simulation, discuss layout synthesis and analysis, outline methods for timing analysis and optimization, explain the concepts of logic synthesis and optimization, summarize test generation; Describe the use of design modelling in digital system design. Apply VHDL modelling for digital hardware design. References Kang & Leblebici, Chapters 11, 13, 14, 15, Pucknell & Eshragian, Chapter 10, Rabaey, Chapter 9, Wolf, Chapters 7, 8.

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Theme 5 : Interconnection and termination design Objective At the end of this section you will understand that the interconnections between high speed digital components (design blocks) are as important as the designs in the block themselves. Outcomes Understand transmission lines and their role in digital design. Ground planes and layer stacking in PCBs Terminations Reference Johnson & Graham, Chapters 1, 4, 5 & 6.

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4 Assessment Summary
Grading Policy The final mark for EDG780 will be the average of the semester mark and examination mark. The semester mark is based on evaluation during the semester, and the examination mark is based on a substantial final assignment. Contributions towards the mark for EDG780 are as follows: Semester mark 40% 10% 25% 25% 0% Final mark 20% 5% 12.5% 12.5% 50%

Assignments: Practicals (Practical 1 only): Test 1: Test 2: Exam assignment (includes Practical 2):

Assignments Five assignments are handed in per individual. Tests Two tests of 90 minutes each will be written at the end of the two mini-blocks. Test 1 covers work up to the end of Chapter 7 in the prescribed book (including discussion during block week), and Test 2 incorporates work from Chapters 8, 9, 11 and 13 of the prescribed book (including discussion during block week). Tests in this course are open book - you must take the prescribed text book and one A4page of double-sided hand-written notes into the test venue. Practicals Two practical sessions will be done. The first one will be about circuit design before the second block week. The second one comprises of a demonstration of your FPGA system design when handing in your examination assignment report. Examination The examination comprises of the design of two projects with a written technical report containing a section on each project. Examination refusal Students with semester marks below 40% will not be allowed to attempt the final examination assignment. In addition, if for a student (i) two of five assignments have not been handed in, or (ii) any of the practical experiments have not been completed, the student will also not be allowed to attempt the final examination assignment. Class attendance Class attendance during mini-block weeks is mandatory (schedule provided in this document). Ethics Students are encouraged to discuss course work with each other, especially during mini-block weeks. Co-operative group work will be used during lectures or for short term projects. Free association study groups are also encouraged. However, each student should hand in his/her own work for assignments. Plagiarism, including copying the work of another student and copying from the Internet, is absolutely unacceptable. Dishonesty such as plagiarism during tests and the final exam can be punished by expulsion from the University.

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5 Assignments
Five assignments will be done for this course. A description of each is given below. The assignments must be remitted in the EDG780 post box in the CEFIM building. In cases where this is impossible, you can also fax or email (if you have a scanner handy) please fax to +27-12-362-5115 (and place it to the attention of the evaluator (please see section 9 of this document). Assignment 1: Remittance date is 24 July 2009. Overview, transistors and layout. Do Problems 1.1a, 1.2, 1.4 and 1.7 from Kang&Leblebici. Do Problems 2.1 and 2.4 from Kang&Leblebici. Also draw the schematics for the NOR2 and NAND2 gates from the layouts in Plate8 on page 82 in Kang&Leblebici. Do Problems 3.1, 3.2, 3.3, 3.5, 3.7, 3.11 and 3.14 from Kang&Leblebici. Do Problems 4.2 and 4.4 from Kang&Leblebici.

Assignment 2: Remittance date is 7 August 2009. Logic gates and combinational logic networks. Do Problems 5.1, 5.2a, 5.3, 5.6 and 5.7 from Kang&Leblebici. Do Problems 6.3, 6.6, 6.9 and 6.10 from Kang&Leblebici. Do Problems 7.1, 7.3, 7.10a and 7.11 from Kang&Leblebici. Assignment 3: Remittance date is 11 September 2009. (a) Study appendix A (no submissions required currently). (b) Sequential machines and subsystems. Do Problem 8.3 from Kang&Leblebici. Do Problems 9.1, 9.3, 9.6 and 9.8 from Kang&Leblebici. Assignment 4: Remittance date is 23 September 2009. (a) System concept design (submit to secondary lecturer) -- please see appendix A. Complete the paper design of your FPGA system. You may realize functions in VHDL or on a schematic level or both, but you must be able to motivate your decisions. (a) Low-power design and chip interface circuits. Do Problem 11.1 from Kang&Leblebici. Do Problems 13.1, 13.4 and 13.5 from Kang&Leblebici. Assignment 5: Remittance date is 22 October 2009. Design for manufacturability and testability. (a) Do Problems 14.5, 14.7,14.8 and 14.11 from Kang&Leblebici. (b) Do Problems 15.1, 15.3, 15.4 and 15.6 from Kang&Leblebici. (c) Do a four layer PCB stack design for 60 Ohm system. Show how to make use of four different termination types to optimise signal integrity and minimise EMC on this PCB.

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Examination assignment: Remittance date for the report is 13 November 2009. Part 1 (Primary Lecturer) : This will be provided (via email) on 29 October 2009 Part 2 (Secondary Lecturer) : For the subsystem or system design project (Appendix A) you have done the concept design of a digital system for implementation on an FPGA. Complete the design process for this project, which should include simulation, implementation, and verification of results. Write a technical report on your implemented design, and include design information in electronic form (note, a CD submission is required). The following Xilinx UG230 Spartan-3E Starter Kit Board will be loaned from the CSIR: http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf (~10 Mb) Students will be required to sign-out the boards, and return during the second practical (or this part of the examination).

This section is marked out of 55.

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6 Practicals
Practical 1 Due on 23 October 2009 The circuit of the figure shown below is the core array of a 4 x 4 read-only memory (ROM). Metal 2 runs horizontally and Metal 1 runs vertically. The presence of a transistor in the array indicates a stored 1 while the absence of a transistor is a stored 0. For this part of the EDG780 practical, answer the questions below (please submit (all applicable files) by email (as a DOC/PDF/ZIP/RAR) to Evaluator ssinha@ieee.org). Please use transistors or gates to complete the memory circuit by drawing and simulating the necessary circuits for the core array. Simulation software of your choice may be used.

Tabulate all design assumptions as/where applicable. a) [2] Explain how this circuit works by labelling the wordlines and bit-lines, and describe the operation of one read cycle. b) [3] The circuit uses precharge devices for the bitline pullups. Draw in the pull-up devices on the bitlines. Are there any ratioing or charge-sharing issues to worry about? If so, explain. If not, why not? c) [4] The circuit wordlines are to be controlled by a decoder circuit. Draw the appropriate decoder circuits using gates (not transistors) with the appropriate clock qualification. Why do we need the wordline to be driven by a qualified clock (i.e. ANDed with the clock signal)? d) [6] The output of this circuit is a single bit from the bitlines (i.e. a bit addressable ROM). Draw a multiplexer circuit to select on bitline using transistors and gates to accomplish this on the diagram. Ensure that there is no VT loss in the output and use any inverters / buffers that you need to produce the correct value at the output. Would you use qualified clock signal here? Why or why not? Additional [5] marks for simulation. If necessary, please use the transistor parameters as provided: http://www.ee.up.ac.za/~subjects/files/EDG780/EDG_parameters.doc (39 kB)
If you choose to use Tanner Tools, and have any enquiries, please reach Jannes Venter pjventer@ieee.org

Practical 2 Due on 13 November 2009. Refer to the examination assignment. Demonstration of your FPGA system design when handing in your examination assignment report. The Secondary Lecturer will evaluate (as shown on the previous page)

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7 Student activity schedule

This is an approximate guide of the semester activities. Week Action Week 1 Study Chapters 1 and 2 in Kang & Leblebici. Week 2 Study Chapters 3 and 4 in Kang & Leblebici. Week 3 Study Chapters 5 and 6 in Kang & Leblebici. Week 4 Study Chapter 7 in Kang & Leblebici. Week 5 Study Chapter 8 in Kang & Leblebici. Week 6 Study Chapter 9 in Kang & Leblebici. Week 7 Class in Block A. Learn design tools. Week 8 Proposal for FPGA design. Week 9 Study Chapter 11 in Kang & Leblebici. Week 10 Study Chapter 13 in Kang & Leblebici. Week 11 Concept design for FPGA system. Week 12 Study relevant chapters of Graham & Johnson. Week 13 Class in Block A. Week 14 Study Chapters 14 and 15 in Kang & Leblebici. Weeks 15, 16 Exam assignment : To be announced later. Weeks 17, 18 Exam assignment : FPGA system.

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8. Block weeks

August 2 9 16 23 30 October 4 11 18 25

1 3 4 5 6 7 8 10 11 12 13 14 15 17-18 August EDG780 Block A 17 18 19 20 21 22 24 25 26 27 28 29 31 1 2 3 5 6 7 8 9 10 05/10 Commencement of lectures 05/10 - 12/10 Eng. Test Week

12 13 14 15 16 17 5-6 Oct. EDG780 Block B 19 20 21 22 23 24 26 27 28 29 30 31 27/10 Friday time-table 29/10 Lectures end

All sessions in the University of Pretoria [UP] will be in (Venue: check http://www.ee.up.ac.za/main/en/postgrad/time_tables), unless otherwise specified by the presenter. Block Week 1: Day 1 Morning Session [UP]: Partial coverage of Themes 1 & 2: *09h00-13h00, with 20 minutes break (starting 11h00) 13h00-14h00 lunch 14h00-14h45: Conclusion of Dr Fotys session Afternoon Session [UP]: Tanner EDA [www.tanner.com]:
jannes.venter@up.ac.za)

S Sinha / D Foty

PJ Venter (

*15h00-17h00, with 20 minutes break in-between: Tanner is an EDA software for low-level IC design. The following outcomes are intended:
1 Front End Design with S-Edit 2 Analogue Simulation with T-Spice & W-Edit 3 IC Layout with L-Edit 4 Schematic Driven Layout, DRC, & Net-list Extraction 5 Node Highlighting, LVS, & Place & Route

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Block Week 1: Day 2 Morning Session [UP]: Two parts *08h00-09h30: summarized on *09h30-10h00: *10h00-12h45: Semester Test I (covering all works, until this block week, as Day I of this block week): S Sinha / T Loubser Break Continuation of Tanner EDA hands-on session: PJ Venter

Afternoon Session [DPSS, CSIR]: C van Zyl **12h45-13h30: Lunch; then 30 minute (flexi-) drive to DPSS. **14h00: Students arrive at DPSS, CSIR (Meet C van Zyl at reception, building 44) **14h00-15h00: Introduction to VHDL **15h00-16h30: Students get an introduction on FPGA design; then an introduction to a small project that they must (partly) complete before Block Week II (this forms the basis of practical 2). The rest of the project will form part of the examination assignment. Block Week 2: Day 1 Morning Session [UP]: Coverage of Themes 3 & 4: J Schoeman **08h00-12h30, with a 30 minutes break: The focus here will be on Digital Circuit Design. Afternoon Session [DPSS, CSIR]: Coverage of Theme 5: C van Zyl **14h00-17h00, with a 30 minutes break: The focus here will be on Digital System Design. Block Week 2: Day 2 Morning Session: Two parts **08h00-09h30 [DPSS]: Test II (covering all works, until this block week, as summarized on Day I of this block week): J Schoeman **Students first have their coffee break, and then arrive at DPSS, CSIR, 10h30. **10h30-12h30 [DPSS, CSIR]: Coverage of Theme 5 (continued): Afternoon Session [DPSS, CSIR]: Practical Session (C
van Zyl) C van Zyl

**13h30-16h30: We would like this opportunity extended in the DPSS labs; practical work could be on the FPGA project (practical 2).

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9 Work/Credits break-down and assessment

The following notion should serve as a rough idea, ito work load, 1 credit = 10 hours. Please bear in mind that EDG780 is a 32 credit (postgraduate) module. Any enquiries pertaining to the covered work (for a given assignment) should be discussed with the assigned evaluator for that particular section. The evaluators will (electronically) serve to avail the assessment of the above assignments prior to the block week. Assignment 1: Chapters 1-4 (Covered during the Aug. block week) Evaluator: S Sinha [4 credits] Assignment 2: Chapters 5-7 (Covered during the Aug. block week) Evaluator: S Sinha [4 credits] Assignment 3: Chapters 8-9 + FPGA proposal (to be covered during the Oct. block week) Evaluator (Ch.8-9): S Sinha [4 credits] Assignment 4: Chapters 11 & 13 + FPGA concept design (to be covered during the Oct. block week) The FPGA concept design should be submitted via email to the Secondary Lecturer. Evaluator (Ch.11&13): J Schoeman [2 credits] Evaluator (FPGA related): J Schoeman [3 credits] Assignment 5: Chapters 14 & 15; and Johnson & Graham Evaluator (Ch.14&15): J Schoeman [2 credits] Examination will cover all of the above. Examination Assignment: Part 1: 4 credits (digital/circuit design IC layout devt. + simulation) (Evaluator: S Sinha) Part 2: FPGA Design: 9 credits (Evaluator: J Schoeman)

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APPENDIX A

Project description Objective: The objective of this assignment is to write a piece of firmware, using the VHDL design language. This firmware will be synthesised, placed and routed, and programmed into an FPGA on an evaluation board using the Xilinx ISE software package. Design Specifications: The firmware design will be that of a digital alarm clock. Basic requirements include: Digital logic will keep the time in hours, minutes and seconds; Time will be displayed on the LCD display on the demo board; The user will be able to program the time using available switches on the board. Advanced requirements include: The user will be able to program an alarm time using available switches on the board. The user will be able to turn the alarm on so that when the time matches the alarm time, an alarm tone will be issued. The user will be able to activate a snooze function when the alarm sounds. This will deactivate the alarm for 1 minute before it sounds again. Assessment: The students will be assessed on: The quality of their VHDL source code: How well the source is structured using hierarchy, processes etc; How well the source is commented can the examiner, using the comments, understand what the code is doing; How well appropriate VHDL instructions are used (eg if/then vs case statements); Whether the firmware meets all the basic requirements; Whether the firmware meets all the advanced requirements; How user friendly the final product is: How easy the programming of the clock is; How nice the display looks. In principle, a design which is adequately commented and meets all the basic requirements should achieve a pass mark. A distinction (for the design project) would require good commenting as well as achieving all the advanced requirements. Please also refer to the table provided under Examination Assignment in the Study Manual.

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