Vous êtes sur la page 1sur 7


Mr. R Pavan Sudheer, M.Tech, Dept. of EEE, Sri Venkateswara University College of Engg., Tirupati. A.P. santoshrps@yahoo.co.in Prof. S Narayana Reddy, Professor, Dept. of EEE, Sri Venkateswara University College of Engg., Tirupati. A.P. snreddy_svu@yahoo.com Mr. M R Raghavendra, Scientist- SF, PRCD, SCG, ISRO Satellite Center, Bangalore. mrr@isac.gov.in

ABSTRACT Binary Phase Shift Keying (BPSK) is one of the most efficient binary data modulation techniques in terms of noise immunity per unit bandwidth and is generated from a carrier signal that is modulated by shifting the phase by 00 or 1800 at a specified baud rate. One method of obtaining a practical synchronous receiver system, suitable for demodulating BPSK waves, is to use the Costas receiver. The implementation of BPSK demodulator in digital domain offers numerous advantages compared to the conventional analog systems. One of the advantages is achieving the programmability in terms of adjusting the bandwidth of the data filters according to the data rate. The demodulator is partially realized in conventional analog domain and partially in digital domain. The 900 phase shifter, anti-aliasing filters and local oscillators are implemented in analog domain, where as the mixers, adders, FIR filters (tunable), loop filter and numerically controlled oscillator are implemented in digital domain. The low pass filters are implemented using FIR-Kaiser window design technique. The filter coefficients for the new cutoff frequency are calculated based on the reference cutoff frequency by retaining the length of the filter constant. A microcontroller based keyboard interface with display is provided to enter the cutoff frequency. Digital signal processor ADSP-21062 is used for the DSP operations and microcontroller AT89S52 is used for the keyboard interface. 1. INTRODUCTION To detect the BPSK signal, synchronous detection must be used. Since there is no discrete carrier term in the BPSK signal, a 1

PLL may be used to extract the carrier reference only if a low-level pilot carrier is transmitted together with the BPSK signal. Otherwise, a Costas loop may be used to synthesize the carrier reference from the BPSK signal and to provide coherent detection. The Costas loop is analyzed by assuming that the VCO is locked to the input suppressed carrier frequency, c, with a constant phase error of . The bandwidth of the two low-pass filters is predetermined by the data rate. The two quadrature output signals are multiplied together and filtered with a low-pass that has a cutoff frequency near dc so that the filter acts as an integrator to produce the necessary dc control voltage. The generalized Costas loop is shown in Fig.1.

Fig.1. Costas receiver

The Costas loop technique is implemented on the DSP processor (ADSP21062). The low pass filters are made programmable or tunable, which is tuned according to the data rate. The cutoff frequency is entered through a keyboard that is interfaced to the ADSP-21062 through a microcontroller interface card.

AT89S52. This interfaces ADSP-21062 link ports with a keyboard and display. The new cutoff frequency for the tunable data filters is entered through the keyboard. Reconstruction Filter: This is a low-pass filter, used to remove sampling frequency components from DSP block.
Fig.1.2. The block diagram of the BPSK setup

2. FIR FILTERS Finite impulse-response (FIR) filters, rather than infinite impulse-response (IIR) filters have been most often used in the design of communications equipment. There are several reasons for this. One of the most important advantages, in data communications, is that a linear phase response can be obtained with FIR designs. For data transmission, a linear phase delay causes inter-symbol interference, which increases the error rate, particularly if the signal-to-noise ratio is poor. Non-linear phase delay is caused by time delay through the filter, which varies with the frequency of the particular component of the signal. In an unequalized analog filter or an IIR digital filter, this effect may be quite severe around the cutoff frequency of the filter. An FIR filter on other hand can be designed to have a linear phase response. This corresponds to a constant time delay, which causes no distortion. To guarantee a linear phase response, the filter coefficients must be symmetrical about the center of the filter. An FIR filter can be implemented with simpler hardware or fewer instructions that an IIR filter. A block diagram of an FIR filter is shown in Fig. 2. Each block label Z-1 represents a delay of one sample time for the input data word, x(n). The coefficient values are designated as hk where k=0 to 5(in this case). Often the total number of taps (multipliers) in an FIR filter is designated by the letter N. The time response of the filter shown in Fig.2 is given by
yn = h0 xn + h1 xn-1 + h2 xn-2 + h3 xn-3 + h4 xn-4+ h5 xn-5. (2.1)

The BPSK setup consists of following components: Data source: This is digital data, which is modulated using binary phase shift keying method and demodulated using the DSP based BPSK demodulator. Here the data is generated using the pseudorandom data generator (Tautron). Carrier signal: This is a sine wave, used for modulation. Here the carrier frequency of 27 kHz is selected and can be changed depending on the requirement. . Modulator: The modulation is done using BPSK technique. AD630 IC is used as BPSK modulator. Mixers: These are analog mixers and are implemented using AD630 IC. 900 phase shifter: This phase shift is achieved using a D flip-flop with a delayed clock. LO: The Local Oscillator (LO) frequency is set to the carrier frequency, which is known a priori. Anti-aliasing filters: These are low-pass filters used to filter off the high frequency components which otherwise would interfere during the sampling process. Analog to digital conversion: The analog to digital converter (A/D) performs sampling, quantization and encoding, after which digital signal is given for the ADSP-21062. ADSP-21062: This is Analog Devices floating point digital signal processor, on which the many DSP operations can be implemented. The DSP has necessary hardware to process the digital data. Here DSP processor is used to implement BPSK demodulator with tunable filters. Digital to analog conversion: This performs the reverse operation of the A/D conversion to bring the digital signal to analog form. Microcontroller interface card: This interface card is made using the microcontroller 2

or, more precisely, (2.2) Taking the z-transform gives,

(2.3) and the transfer function is


It follows from the above that, once an FIR low-pass filter has been designed for a given cutoff frequency, it can be tuned simply by changing the c and recomputing the filter coefficients according to the above expression. If hLP denotes the coefficients of the prototype low-pass filter designed for a cutoff frequency c, from Eq(2.8) the constants c[n] are given by,

(2.10) (2.11)

Then, the coefficients LP[n] of the transformed FIR filter with a cutoff frequency c are given by,
Fig.2.The time response of the FIR filter

2.1. Tunable FIR Filters In many practical applications of digital filtering, it is desirable to change the filter characteristics during its operation. The filter that preserves the structure and permits easy tuning of the cutoff frequency is know as a programmable or tunable filter. Tunable FIR filters can be realized as follows:
(2.12) (2.13)


The ideal low-pass FIR filter with a zero-phase response is given by,

The impulse response coefficients are given by,


The above expression can be truncated to obtain the realizable approximation given by,

The prototype filter should be designed such that its coefficients have values not too close to zero. The only limiting factor is that it is not reasonable to make the 6 dB cutoff frequency smaller then [(1/2)] or greater than [(1/2)], where the is the transition bandwidth of the filter. For FIR filters, the transition bandwidth is inversely proportional to the length of the filter. The length of the filter decides the transition bandwidth. In the present case, transition bandwidth, 400Hz is selected for length of the filter 47. The lowest cutoff frequency is 200Hz and the highest cutoff frequency is 3800Hz. To get the variable stop band attenuations, the tunable filters are designed using the FIR- Kaiser window technique. 3. BPSK DEMODULATOR ON DSP PROCESSOR In order to gain the familiarity with BPSK demodulator, two-stage approach is followed. The first stage will be to realize the demodulator partly in analog domain and second stage will be to realize the on DSP processor. 3


Where c is the 6dB cutoff frequency, and


The BPSK modulated signal is obtained using AD630 IC. In demodulation, the analog mixers are implemented using AD630 IC. The 900 shifter is realized by generating delay using the D flip-flop. All anti-aliasing filters are designed using the op-amp circuits. The signals from the anti-aliasing filters are digitized using A/D converters and are given to the digital signal processor (ADSP-21062), where the Costas loop is implemented. All the adders, mixers, tunable FIR filters, loop filter and NCO are implemented in the processor through software code. The input cutoff frequency to the tunable filters is given through a microcontroller interface card (with a keyboard and display). A microcontroller card (with keyboard and display) is interfaced to the link ports of the ADSP-21062 processor for entering the cutoff frequencies for the data filters in the demodulator. After the demodulation operation, the digital signals from the ADSP-21062 are sent to the D/A converters through serial ports. The obtained demodulated signal is passed through reconstruction filter to remove the sampling frequency components.

The ADSP processor performs a BPSK demodulation and produces the demodulated signal. The circuit is synchronized using the clock pulses generated by the ADSP processor. This clock rate is programmable, to suit the necessary applications. In this case clock frequency is adjusted to 128 kHz (TCLK). The timing distribution circuitry makes use of this TCLK to provide the necessary synchronization of the other circuit components.

Fig.3.2. Block diagram of DSP module

Fig.3.1. Block diagram of complete BPSK demodulator

3.1. Digital Signal Processing Module ADSP21062 processor board with supporting circuitry is shown in the Fig.3.2. It has two channels (channel I and channel Q), which are coherent in their operation. The circuit uses an analog to digital converter. The digital data thus obtained from the ADC is given to the DSP processor through a parallel in serial out (PISO), using the ports Serial Port 0 and Serial Port 1.The BPSK program is loaded onto the processor on RESET from the EEPROM. 4

3.2. Loop Filter The filter that is generally incorporated in a Phase Locked Loop (PLL) is a low-pass filter. The loop filter not only removes the high frequency components and noise but also controls the dynamic characteristics such as capture range, lock range, bandwidth and transient response. The loop filter designed is the digital equivalent of analog lead-lag network. This filter is designed using IIR technique.The loop filter is designed with a low cutoff frequency in order to generate a modifier for NCO. The loop filter equations are: w(n) = x(n) + a1*w(n-1) a0=1; (3.1) y(n) = b0*w(n) b1*w(n-1) (3.2) 3.3. Numerically-Controlled Oscillator(NCO) A numerically-controlled oscillator (NCO) is an electronic system for synthesizing a range of frequencies from a fixed time base. Unlike a phase-locked loop based analog

frequency synthesizer, it is capable of synthesizing a very wide range of precise frequency ratios. However, it is limited to producing frequencies that are less than half the time base frequency, due to Nyquist's theorem. The name is by analogy with "voltagecontrolled oscillator ". A NCO generally consists of a digital waveform generator that increments a phase counter by a per-sample increment. This phase is then looked up in a waveform table to create a sine waveform. If an analog output is desired, this waveform is sent to a digital-to-analog converter to produce an analog waveform, and then filtered by an analog filter to remove aliasing and DAC artifacts. Alternatively, the digital waveform may be used directly as input for further digital signal processing. In this way, the frequency ratios that can be produced are limited only to the precision of the arithmetic used to compute the phase. 3.4. Anti-Aliasing Filters In a sampled data system, frequency components greater than half the sampling rate "aliasing" (shift) into the frequency band of interest. Most of the time, aliasing in an undesirable side effect, so the "under-sampled" higher frequencies are simply filtered out before the A/D stage. The maximum frequency component a sampled data system can accurately handle is its Nyquist limit. The sample rate must be greater than or equal to two times the highest frequency component in the input signal. When this rule is violated, unwanted or undesirable signals appear in the frequency band of interest. This is called "aliasing." An anti-aliasing filter is a low-pass filter that provides a cutoff frequency that removes unwanted signals from the ADC input or at least attenuates them to the point that they will not adversely affect the circuit. In practice, the attenuation level of the anti-aliasing filter equals the resolution of ADC. Unity Gain Salenkey Active LPF structure is used for the design of anti-aliasing filers. 3.5. I-Q Detectors The IC 8038 is a function generator, which generates the square wave of required 5

frequency depending upon the RC values. Here IC 8038 serves as local oscillator (LO). The JK flip-flop with both of its inputs high (toggle mode), and with digital clock given from the IC8038 (with XOR gate setup) gives a phase shift of 900. The block diagrams of the arrangement are shown in Fig.3.3.

Fig.3.3. Phase Shifter (IC setup)

4. RESULTS 4.1. Simulation 4.1.1. MATLAB

Fig.4.1 MATLAB simulation (tunable filter)

4.1.2. VDSP++ Simulator

Fig.4.2. I-channel input

Fig.4.3. Input Q-channel

5. LIMITATION The designed stopband attenuation for the data filter is 40 dB. But, the attenuation of 26 dB is achieved in the hardware. The reason for the limitation is explained as follows: The ADSP-21062 is a 32-bit floating-point

Fig.4.4. Simulator demodulated data

4.2. Emulation (Hardware)

Modulating signal
0.8 0.6 0.4 amplitude 0.2 0 -0.2 -0.4 -0.6 -0.8 time

processor. All the registers and memory locations would be 32-bit wide. This causes a limitation for stopband attenuation in the tunable filter design. In tunable filter algorithm, sin(x) is calculated using Taylor's series.
Fig.4.5. Modulating signal
Carrier wave


where The set of constant values C1, C2, C3 Cn are stored in a circular buffer. With 32-bit wide memory locations only 20 constants ( C1, C2, C3 Cn ) can be stored. This causes the stop band attenuation to be 26 dB even though it is designed for 40 dB. The frequency response plots for the 20 factorial values and 100 factorial values are shown in the Fig.5.1 and Fig.5.2 respectively.

1.5 1 amplitude 0.5 0 -0.5 -1 -1.5 time

Fig.4.6. Carrier wave

modulated signal
1.5 1 amplitude 0.5 0 -0.5 -1 -1.5 time

Fig.4.7. BPSK modulated signal

demodulated signal after AAF
0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 time

Fig.5.1. Frequency response of data filter for 20 factorial values (in Taylors series)


Fig.4.8. Demodulated signal

Fig.5.2. Frequency response of data filter for 100 factorial values (in Taylors series)

6. CONCLUSION The BPSK demodulator is implemented partially in analog domain and partially in digital domain. Since the Costas loop technique is coherent, a carrier of 27 kHz is selected and can be changed depending upon the requirement. Unity gain Salenkey active low pass filters are used as anti-aliasing and reconstruction filters, which filters the undersampled components and they are used before and after the DSP processor. The Costas loop with tunable filters algorithm is implemented in the DSP processor. The optimum response for the tunable or data filters for the data range (10 Hz to 3800 Hz with (1-5) Vp-p) is achieved with a length of 47. The length of the filter is inversely proportional to the transition bandwidth. The length can be changed depending upon the data rate. The tunable filters algorithm limits the cutoff frequency from 200 Hz to 3800 Hz with a resolution of 1 Hz. For entering the cutoff frequency, a microcontroller based keyboard interface is used having 14 keys. The sampling frequency is selected as 8 kHz and can be changed depending upon the data rate. With the above considerations, the performance of the demodulator designed is found satisfactory. REFERENCES
1. Sanjit K Mithra, Digital Signal Processing a Computer Based Approach, - TMH edition. 2. Marvin E. Freking, Digital Signal Processing In Communication Systems - Van Nostrand Reinhold, New York. 3. Analog Devices (ADSP-21062) Manual.

4. Simon Haykin, Communication Systems John Willey, 4th edition. 5. Leon W. Couch II, Digital and Analog Communication Systems- Maxwell Macmillan Intl.Edition. 6. Kenneth J. Ayala, The 8051 Microcontroller Architecture, Programming & ApplicationsTMH edition. 7. http://www.analog.com. 8. http://www.rfdesign.com 9. http://www.mathworks.com 10. Petri Jarske, Sanjit K Mithra and Yrjo Neuvo, A Simple Approach To The Design of Linear Phase Fir Digital Filters With Variable Characteristics, in Nov 1987 IEEE Int. Signal Processing, North-Holland. 11. Djordje Babic, Design And Implementation Of Variable (Programmable) Fir Filters, Institute of Communications Engineering, Tampere University of Technology, FINLAND IEEE Int. Symp. 12. Ifeachor and Jervis, Digital Signal Processing A Practical Approach - Van Nostrand Reinhold, New York.