Asynchronous Sequential Circuit

Introduction and Design Issues

Input AB 0001 0010

State(xAB) transition 100101001 100110

Output X 100 11

Remark At AB=00, stable x=1.

0100 0111

001000100 001011

011 00

At AB=01, stable x=0.

1000 1011

110100, 110111

11 11

At AB=10, stable x=1.

1101 1110

011001, 111101001 011010101, 111110

00, 100 011, 11

At AB=00, stable x=0, 1.

Find stable state & corresponding output ?

x A X B Y

AB x 00 0 0/0 1 0/0 01 0/0 0/0 (a) 11 1/0 1/1 10 0/0 1/0 00 / 0 01 / 0 10 / 0 x=0

11 / 0 x=1 00 / 1 01 / 0 (b) 10 / 0 11 / 0

Problems: Hazards

A A _ A (a) _ A Y 1 = NOT gate delay 1 2 (b) 2 = OR gate delay 1

__ AB _ 0 AB 1 AB 1 _ AB 0

_ C

C 0 0 1 1

A C Y B

__ AB _ 0 AB 1

_ C

C 0 0

A C B

_ ( a ) Y = BC + AC

( b ) Circuit with static-1 hazard

1 AB 1 _ 1 AB 0 _ ( c ) Y = BC + AC + AB

( d ) Hazard free circuit

A _ A (a)

A _ A Y

1 = NOT gate delay 1 2 1 (b) 2 = OR gate delay

__ AB 0 _ AB 1 AB _ AB 1 0

_ C

C 0 0 1 1 B C

A Y

__ AB 0 _ AB 1 AB _ AB 1

_ C

C 0 0 1

A B Y

_ ( a ) Y =(B+C ) (A+C ) ( b ) Circuit with static-0 hazard

C 0 1 _ ( c ) Y = (B+C ) (A+C ) (A+B ) ( d ) Hazard free circuit

Dynamic Hazard
Dynamic hazard occurs when circuit output makes multiple transitions before it settles to a final value while the logic equation asks for only one transition. An output transition designed as 10 may give 1010 when such hazard occurs and a 01 can behave like 0101. The output of logic equation in dynamic hazard degenerates into Y=A+A.A or Y=(A+A).A kind of relations for certain combinations of the other input variables. As shown by these equations, these occur in multilevel circuits having implicit static-1 and/or static-0 hazards. Providing covers to each one of them dynamic hazard can be prevented.

A=High, B=High C

Y1 A Y2 Y4 B C Y3 Y1 Y3 Y Y4 Y t=0 (a) (b) 2 3 4 Y2

Design: The Problem

A digital logic circuit is to be designed that has two inputs A, B and one output X. X goes high if at A=1, B makes a transition 10. X remains high as long as this A=1, B=0 are maintained. If any of A or B changes at this time output X goes low. It becomes high again when at A=1, B goes from 1 to 0. The timing diagram corresponding to this problem is shown in Fig. 11-30.

A B X

00 00

01

a/0
00 00 10 01

b/0

01

11 10

e/1
10

10

c/0

11

d/0
11

11

Primitive Flow Table

AB 00 a b c d e a a a 4 a 01 b b 3 b 5 11 1 d d d d 10 c 2 c e e X 0 0 0 0 1

b c d e

d,1 c,2 d,1 b,3 d,1 c,e b,3 c,2 a,4 e,2
a, 4 b, 3 c,e

a
d c b a P

: d : cd : cd(bc)d(bc) : d(bc) (ab) (ac) (abc) = (abc) (d) (e)

2c, 3b 1d

AB 00 a d e a 4 a 01 a a 5 11 d d d 10 a e e X 0 0 1

10 00 01

a/0
01

11 11

d/0
10

00

11

e/1
10

State assignment: Dummy State

00 01
00 / 0 01 / 0

11 11

00

01 10
10 / 0

10

00 10

11 / 1

AB pq 00 01 11 10

00 00 10 00

01 00 00

11 01 01 01

10 00 11 11

AB pq 00 01 11 10

00 0 1 0

01 0 0

11 0 0 0

10 0 1 1

_ P=qB (a) AB pq 00 01 11 10 00 0 0 0 01 0 0 11 1 1 1 10 0 1 1 1 X=PQ (d) 0 1 P 0 Q (b)

0 0

1 0

Q=qA+AB = A (q + B) (c)

Q X P