Analog Devices - Practical Design Techniques For Sensor Signal Conditioning

PRACTICAL DESIGN TECHNIQUES
FOR SENSOR SIGNAL CONDITIONING

INTRODUCTION -
BRIDGE CIRCUITS -
AMPLIFIERS FOR SIGNAL CONDITIONING -
STRAIN, FORCE, PRESSURE, AND FLOW MEASUREMENTS -
HIGH IMPEDANCE SENSORS -
POSITION AND MOTION SENSORS -
TEMPERATURE SENSORS -
ADCs FOR SIGNAL CONDITIONING -
SMART SENSORS -
HARDWARE DESIGN TECHNIQUES -
INDEX -
1
2
3
4
5
6
7
8
I
9
10
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FOR SENSOR
SIGNAL CONDITIONING
a
ACKNOWLEDGMENTS
Thanks are due the many technical staff members of Analog Devices in Engineering and
Marketing who provided invaluable inputs during this project. Particular credit is due the
individual authors whose names appear at the beginning of their material.
Special thanks go to Wes Freeman, Walter G. Jung, Bill Chestnut, and Ed Grokulsky for
thoroughly reviewing the material for content and accuracy.
Judith Douville compiled the index, and printing was done by R. R. Donnelley and Sons, Inc.
Walt Kester
1999
Copyright 1999 by Analog Devices, Inc.
Printed in the United States of America
All rights reserved. This book, or parts thereof, must not be reproduced in any form without
permission of the copyright owner.
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable.
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described herein will not infringe on existing or future patent rights, nor do the descriptions
contained herein imply the granting of licenses to make, use, or sell equipment constructed in
accordance therewith.
Specifications are subject to change without notice.
ISBN-0-916550-20-6
PRACTICAL DESIGN TECHNIQUES FOR
SENSOR SIGNAL CONDITIONING
SECTION 1
INTRODUCTION
SECTION 2
BRIDGE CIRCUITS
n Bridge Configurations
n Amplifying and Linearizing Bridge Outputs
n Driving Bridges
SECTION 3
AMPLIFIERS FOR SIGNAL CONDITIONING
n Precision Op Amp Characteristics
n Amplifier DC Error Budget Analysis
n Single Supply Op Amps
n Instrumentation Amplifiers
n Chopper Stabilized Amplifiers
n Isolation Amplifiers
SECTION 4
STRAIN, FORCE, PRESSURE, AND FLOW MEASUREMENTS
n Strain Gages
n Bridge Signal Conditioning Circuits
SECTION 5
HIGH IMPEDANCE SENSORS
n Photodiode Preamplifier Design
n Compensation of High Speed Photodiode
I/V Converter
n High Impedance Charge Output Sensors
n CCD/CIS Image Processing
SECTION 6
POSITION AND MOTION SENSORS
n Linear Variable Differential Transformers (LVDTs)
n Hall Effect Magnetic Sensors
n Optical Encoders
n Resolvers and Synchros
n Inductosyns
n Vector AC Induction Motor Control
n Accelerometers
SECTION 7
TEMPERATURE SENSORS
n Thermocouple Principles and Cold-Junction
Compensation
n Resistance Temperature Detectors (RTDs)
n Thermistors
n Semiconductor Temperature Sensors
n Microprocessor Temperature Monitoring
SECTION 8
ADCs FOR SIGNAL CONDITIONING
n Successive Approximation ADCs
n SAR ADCs With Multiplexed Inputs
n Complete Data Acquisition Systems on a Chip
n Sigma-Delta Measurement ADCs
n High Resolution, Low-Frequency Sigma-Delta
Measurement ADCs
n Applications of Sigma-Delta ADCs in
Power Meters
SECTION 9
SMART SENSORS
n 4-20mA Control Loops
n Interfacing Sensors to Networks
n MicroConverter
SECTION 10
HARDWARE DESIGN TECHNIQUES
n Resistor and Thermocouple Errors in
High Accuracy Systems
n Grounding in Mixed Signal Systems
n Power Supply Noise Reduction and Filtering
n Preventing RFI Rectification
n Dealing With High Speed Logic
n A Review of Shielding Concepts
n Isolation Techniques
n Overvoltage Protection
n Electrostatic Discharge (ESD)
INDEX
FOR SENSOR SIGNAL CONDITIONING
INTRODUCTION -
BRIDGE CIRCUITS -
AMPLIFIERS FOR SIGNAL CONDITIONING -
STRAIN, FORCE, PRESSURE, AND FLOW MEASUREMENTS -
HIGH IMPEDANCE SENSORS -
POSITION AND MOTION SENSORS -
TEMPERATURE SENSORS -
ADCs FOR SIGNAL CONDITIONING -
SMART SENSORS -
HARDWARE DESIGN TECHNIQUES -
INDEX -
1
2
3
4
5
6
7
8
I
9
10
I NTRODUCTI ON
1.1
SECTI ON 1
I NTRODUCTI ON
Wa l t Kest er
This book deals wit h sensor s and associat ed signal condit ioning cir cuit s. The t opic is
br oad, but t he focus of t his book is t o concent r at e on cir cuit and signal pr ocessing
applicat ions of sensor s r at her t han t he det ails of t he act ual sensor s t hemselves.
St r ict ly speaking, a sensor is a device t hat r eceives a signal or st imulus and
r esponds wit h an elect r ical signal, while a transducer is a conver t er of one t ype of
ener gy int o anot her . In pr act ice, however , t he t er ms ar e oft en used
int er changeably.
Sensor s and t heir associat ed cir cuit s ar e used t o measur e var ious physical pr oper t ies
such as t emper at ur e, for ce, pr essur e, flow, posit ion, light int ensit y, et c. These
pr oper t ies act as t he st imulus t o t he sensor , and t he sensor out put is condit ioned
and pr ocessed t o pr ovide t he cor r esponding measur ement of t he physical pr oper t y.
We will not cover all possible t ypes of sensor s, only t he most popular ones, and
specifically, t hose t hat lend t hemselves t o pr ocess cont r ol and dat a acquisit ion
syst ems.
Sensor s do not oper at e by t hemselves. They ar e gener ally par t of a lar ger syst em
consist ing of signal condit ioner s and var ious analog or digit al signal pr ocessing
cir cuit s. The system could be a measur ement syst em, dat a acquisit ion syst em, or
pr ocess cont r ol syst em, for example.
Sensor s may be classified in a number of ways. Fr om a signal condit ioning viewpoint
it is useful t o classify sensor s as eit her active or passive. An active sensor r equir es an
ext er nal sour ce of excit at ion. Resist or -based sensor s such as t her mist or s, RTDs
(Resist ance Temper at ur e Det ect or s), and st r ain gages ar e examples of act ive
sensor s, because a cur r ent must be passed t hr ough t hem and t he cor r esponding
volt age measur ed in or der t o det er mine t he r esist ance value. An alt er nat ive would
be t o place t he devices in a br idge cir cuit , however in eit her case, an ext er nal
cur r ent or volt age is r equir ed.
On t he ot her hand, passive (or self-generating) sensor s gener at e t heir own elect r ical
out put signal wit hout r equir ing ext er nal volt ages or cur r ent s. Examples of passive
sensor s ar e t her mocouples and phot odiodes which gener at e t her moelect r ic volt ages
and phot ocur r ent s, r espect ively, which ar e independent of ext er nal cir cuit s.
It should be not ed t hat t hese definit ions (active vs. passive) r efer t o t he need (or lack
t her eof) of ext er nal act ive cir cuit r y t o pr oduce t he elect r ical out put signal fr om t he
sensor . It would seem equally logical t o consider a t her mocouple t o be act ive in t he
sense t hat it pr oduces an out put volt age wit h no ext er nal cir cuit r y, however t he
convent ion in t he indust r y is t o classify t he sensor wit h r espect t o t he ext er nal
cir cuit r equir ement as defined above.
I NTRODUCTI ON
1.2
SENSOR OVERVIEW
n Sensors:
Convert a Signal or Stimulus (Representing a Physical
Property) into an Electrical Output
n Transducers:
Convert One Type of Energy into Another
n The Terms are often Interchanged
n Active Sensors Require an External Source of Excitation:
RTDs, Strain-Gages
n Passive (Self-Generating) Sensors do not:
Thermocouples, Photodiodes
Figure 1.1
TYPICAL SENSORS AND THEIR OUTPUTS
PROPERTY SENSOR ACTIVE/
PASSIVE
OUTPUT
Temperature Thermocouple
Silicon
RTD
Thermistor
Passive
Active
Active
Active
Voltage
Voltage/Current
Resistance
Resistance
Force /
Pressure
Strain Gage
Piezoelectric
Active
Passive
Resistance
Voltage
Acceleration Accelerometer Active Capacitance
Position LVDT Active AC Voltage
Light Intensity Photodiode Passive Current
Figure 1.2
I NTRODUCTI ON
1.3
A logical way t o classify sensor s is wit h r espect t o t he physical pr oper t y t he sensor is
designed t o measur e. Thus we have t emper at ur e sensor s, for ce sensor s, pr essur e
sensor s, mot ion sensor s, et c. However , sensor s which measur e differ ent pr oper t ies
may have t he same t ype of elect r ical out put . For inst ance, a Resist ance
Temper at ur e Det ect or (RTD) is a var iable r esist ance, as is a r esist ive st r ain gauge.
Bot h RTDs and st r ain gages ar e oft en placed in br idge cir cuit s, and t he condit ioning
cir cuit s ar e t her efor e quit e similar . In fact , br idges and t heir condit ioning cir cuit s
deser ve a det ailed discussion.
The full-scale out put s of most sensor s (passive or act ive) ar e r elat ively small
volt ages, cur r ent s, or r esist ance changes, and t her efor e t heir out put s must be
pr oper ly condit ioned befor e fur t her analog or digit al pr ocessing can occur . Because of
t his, an ent ir e class of cir cuit s have evolved, gener ally r efer r ed t o as signal
conditioning cir cuit s. Amplificat ion, level t r anslat ion, galvanic isolat ion, impedance
t r ansfor mat ion, linear izat ion, and filt er ing ar e fundament al signal condit ioning
funct ions which may be r equir ed.
What ever for m t he condit ioning t akes, however , t he cir cuit r y and per for mance will
be gover ned by t he elect r ical char act er of t he sensor and it s out put . Accur at e
char act er izat ion of t he sensor in t er ms of par amet er s appr opr iat e t o t he applicat ion,
e.g., sensit ivit y, volt age and cur r ent levels, linear it y, impedances, gain, offset , dr ift ,
t ime const ant s, maximum elect r ical r at ings, and st r ay impedances and ot her
impor t ant consider at ions can spell t he differ ence bet ween subst andar d and
successful applicat ion of t he device, especially in cases wher e high r esolut ion and
pr ecision, or low-level measur ement s ar e involved.
Higher levels of int egr at ion now allow ICs t o play a significant r ole in bot h analog
and digit al signal condit ioning. ADCs specifically designed for measur ement
applicat ions oft en cont ain on-chip pr ogr ammable-gain amplifier s (PGAs) and ot her
useful cir cuit s, such as cur r ent sour ces for dr iving RTDs, t her eby minimizing t he
ext er nal condit ioning cir cuit r equir ement s.
Most sensor out put s ar e non-linear wit h r espect t o t he st imulus, and t heir out put s
must be linear ized in or der t o yield cor r ect measur ement s. Analog t echniques may
be used t o per for m t his funct ion, however t he r ecent int r oduct ion of high
per for mance ADCs now allows linear izat ion t o be done much mor e efficient ly and
accur at ely in soft war e and eliminat es t he need for t edious manual calibr at ion using
mult iple and somet imes int er act ive t r impot s.
The applicat ion of sensor s in a t ypical pr ocess cont r ol syst em is shown in Figur e 1.3.
Assume t he physical pr oper t y t o be cont r olled is t he t emper at ur e. The out put of t he
t emper at ur e sensor is condit ioned and t hen digit ized by an ADC. The
micr ocont r oller or host comput er det er mines if t he t emper at ur e is above or below
t he desir ed value, and out put s a digit al wor d t o t he digit al-t o-analog conver t er
(DAC). The DAC out put is condit ioned and dr ives t he actuator, in t his case - a
heat er . Not ice t hat t he int er face bet ween t he cont r ol cent er and t he r emot e pr ocess
is via t he indust r y-st andar d 4-20mA loop.
I NTRODUCTI ON
1.4
TYPICAL INDUSTRIAL PROCESS CONTROL LOOP
SIGNAL
CONDITIONING
TEMP
SENSOR
PROCESS
HEATER
SIGNAL
CONDITIONING
4 TO 20mA
TRANSMITTER
4 TO 20mA
RECEIVER
SIGNAL
CONDITIONING
ADC
MICRO
CONTROLLER
DAC
SIGNAL
CONDITIONING
HOST
COMPUTER
4 TO 20mA
TRANSMITTER
4 TO 20mA
RECEIVER
CONTROL ROOM REMOTE
Figure 1.3
Digit al t echniques ar e becoming mor e and mor e popular in pr ocessing sensor
out put s in dat a acquisit ion, pr ocess cont r ol, and measur ement . 8-bit
micr ocont r oller s (8051-based, for example) gener ally have sufficient speed and
pr ocessing capabilit y for most applicat ions. By including t he A/D conver sion and t he
micr ocont r oller pr ogr ammabilit y on t he sensor it self, a "smar t sensor " can be
implement ed wit h self cont ained calibr at ion and linear izat ion feat ur es among
ot her s. A smar t sensor can t hen int er face dir ect ly t o an indust r ial net wor k as shown
in Figur e 1.4.
The basic building blocks of a "smar t sensor " ar e shown in Figur e 1.5, const r uct ed
wit h mult iple ICs. The Analog Devices Micr oConver t er -ser ies pr oduct s includes
on-chip high per for mance mult iplexer s, ADCs, and DACs, coupled wit h FLASH
Memor y and an indust r y-st andar d 8052 micr ocont r oller cor e, as well as suppor t
cir cuit r y and sever al st andar d ser ial por t configur at ions. These ar e t he fir st
int egr at ed cir cuit s which ar e t r uly smar t sensor dat a acquisit ion syst ems (high-
per for mance dat a conver sion cir cuit s, micr ocont r oller , FLASH memor y) on a single
chip (see Figur e 1.6).
I NTRODUCTI ON
1.5
STANDARDIZATION AT THE DIGITAL INTERFACE
USING SMART SENSORS
NODE FIELD NETWORK NODE
N
O
D
E
BRANCH
N
O
D
E
S
M
A
R
T

S
E
N
S
O
R
S
M
A
R
T

S
E
N
S
O
R
D
E
V
I
C
E

N
E
T
W
O
R
K
SMART SENSOR
SMART SENSOR
SMART SENSORS OFFER:
n Self-Calibration
n Linearization
n Interchangeability
n Standard Digital Interfaces
Figure 1.4
BASIC ELEMENTS IN A "SMART" SENSOR
Precision Amplifier
High Resolution ADC
Microcontroller Sensor
Pressure Sensor,
RTD,
Thermocouple,
Strain Gage,
etc.
Figure 1.5
I NTRODUCTI ON
1.6
THE EVEN SMARTER SENSOR
Sensor MicroConverter
TM
!
Pressure Sensor,
RTD,
Thermocouple,
Strain Gage,
etc.
Figure 1.6
BRI DGE CI RCUI TS
2.1
SECTI ON 2
BRI DGE CI RCUI TS
Wa l t Kest er
I NTRODUCTI ON
This sect ion discusses t he fundament al concept s of br idge cir cuit s, and is followed by
a sect ion on pr ecision op amps (Sect ion 3). Sect ion 4 focuses on t he det ailed
applicat ion cir cuit s r elat ing t o st r ain gage-based sensor s. Sect ions 2 and 4 can be
r ead sequent ially if t he r eader alr eady under st ands t he design issues r elat ing t o op
amps which ar e cover ed in Sect ion 3.
Resist ive element s ar e some of t he most common sensor s. They ar e inexpensive t o
manufact ur e and r elat ively easy t o int er face wit h signal condit ioning cir cuit s.
Resist ive element s can be made sensit ive t o t emper at ur e, st r ain (by pr essur e or by
flex), and light . Using t hese basic element s, many complex physical phenomena can
be measur ed; such as fluid or mass flow (by sensing t he t emper at ur e differ ence
bet ween t wo calibr at ed r esist ances) and dew-point humidit y (by measur ing t wo
differ ent t emper at ur e point s), et c.
Sensor element s' r esist ances can r ange fr om less t han 100 t o sever al hundr ed k,
depending on t he sensor design and t he physical envir onment t o be measur ed (See
Figur e 2.1). For example, RTDs (Resist ance Temper at ur e Devices) ar e t ypically
100 or 1000. Ther mist or s ar e t ypically 3500 or higher .
RESISTANCE OF POPULAR SENSORS
n Strain Gages 120 , 350 , 3500
n Weigh-Scale Load Cells 350 - 3500
n Pressure Sensors 350 - 3500
n Relative Humidity 100k - 10M
n Resistance Temperature Devices (RTDs) 100 , 1000
n Thermistors 100 - 10M
Figure 2.1
BRI DGE CI RCUI TS
2.2
Resist ive sensor s such as RTDs and st r ain gages pr oduce small per cent age changes
in r esist ance in r esponse t o a change in a physical var iable such as t emper at ur e or
for ce. Plat inum RTDs have a t emper at ur e coefficient of about 0.385%/C. Thus, in
or der t o accur at ely r esolve t emper at ur e t o 1C, t he measur ement accur acy must be
much bet t er t han 0.385 for a 100 RTD.
St r ain gages pr esent a significant measur ement challenge because t he t ypical
change in r esist ance over t he ent ir e oper at ing r ange of a st r ain gage may be less
t han 1% of t he nominal r esist ance value. Accur at ely measur ing small r esist ance
changes is t her efor e cr it ical when applying r esist ive sensor s.
One t echnique for measur ing r esist ance (shown in Figur e 2.2) is t o for ce a const ant
cur r ent t hr ough t he r esist ive sensor and measur e t he volt age out put . This r equir es
bot h an accur at e cur r ent sour ce and an accur at e means of measur ing t he volt age.
Any change in t he cur r ent will be int er pr et ed as a r esist ance change. In addit ion,
t he power dissipat ion in t he r esist ive sensor must be small, in accor dance wit h t he
manufact ur er 's r ecommendat ions, so t hat self-heat ing does not pr oduce er r or s,
t her efor e t he dr ive cur r ent must be small.
MEASURING RESISTANCE INDIRECTLY
USING A CONSTANT CURRENT SOURCE
V
OUT
I R R + + ( )
R + R
I
Figure 2.2
Br idges offer an at t r act ive alt er nat ive for measur ing small r esist ance changes
accur at ely. The basic Wheat st one br idge (act ually developed by S. H. Chr ist ie in
1833) is shown in Figur e 2.3. It consist s of four r esist or s connect ed t o for m a
quadr ilat er al, a sour ce of excit at ion (volt age or cur r ent ) connect ed acr oss one of t he
diagonals, and a volt age det ect or connect ed acr oss t he ot her diagonal. The det ect or
measur es t he differ ence bet ween t he out put s of t wo volt age divider s connect ed
acr oss t he excit at ion.
BRI DGE CI RCUI TS
2.3
THE WHEATSTONE BRIDGE
V
O
R4
R1
R3
R2
V
B
V
O
R
R R
V
B
R
R R
V
B

+ +

+ +
1
1 4
2
2 3

+ +
| |
. .

` `
, ,
+ +
| |
. .

` `
, ,

R
R
R
R
R
R
R
R
V
B
1
4
2
3
1
1
4
1
2
3
AT BALANCE,
V
O
IF
R
R
R
R
0
1
4
2
3
+
-
Figure 2.3
A br idge measur es r esist ance indir ect ly by compar ison wit h a similar r esist ance.
The t wo pr inciple ways of oper at ing a br idge ar e as a null det ect or or as a device
t hat r eads a differ ence dir ect ly as volt age.
When R1/R4 = R2/R3, t he r esist ance br idge is at a null, ir r espect ive of t he mode of
excit at ion (cur r ent or volt age, AC or DC), t he magnit ude of excit at ion, t he mode of
r eadout (cur r ent or volt age), or t he impedance of t he det ect or . Ther efor e, if t he r at io
of R2/R3 is fixed at K, a null is achieved when R1 = KR4. If R1 is unknown and R4
is an accur at ely det er mined var iable r esist ance, t he magnit ude of R1 can be found
by adjust ing R4 unt il null is achieved. Conver sely, in sensor -t ype measur ement s, R4
may be a fixed r efer ence, and a null occur s when t he magnit ude of t he ext er nal
var iable (st r ain, t emper at ur e, et c.) is such t hat R1 = KR4.
Null measur ement s ar e pr incipally used in feedback syst ems involving
elect r omechanical and/or human element s. Such syst ems seek t o for ce t he act ive
element (st r ain gage, RTD, t her mist or , et c.) t o balance t he br idge by influencing t he
par amet er being measur ed.
For t he major it y of sensor applicat ions employing br idges, however , t he deviat ion of
one or mor e r esist or s in a br idge fr om an init ial value is measur ed as an indicat ion
of t he magnit ude (or a change) in t he measur ed var iable. In t his case, t he out put
volt age change is an indicat ion of t he r esist ance change. Because ver y small
r esist ance changes ar e common, t he out put volt age change may be as small as t ens
of millivolt s, even wit h V
B
= 10V (a t ypical excit at ion volt age for a load cell
applicat ion).
BRI DGE CI RCUI TS
2.4
In many br idge applicat ions, t her e may be t wo, or even four element s which var y.
Figur e 2.4 shows t he four commonly used br idges suit able for sensor applicat ions
and t he cor r esponding equat ions which r elat e t he br idge out put volt age t o t he
excit at ion volt age and t he br idge r esist ance values. In t his case, we assume a
const ant volt age dr ive, V
B
. Not e t hat since t he br idge out put is dir ect ly pr opor t ional
t o V
B
, t he measur ement accur acy can be no bet t er t han t hat of t he accur acy of t he
excit at ion volt age.
OUTPUT VOLTAGE AND LINEARITY ERROR FOR
CONSTANT VOLTAGE DRIVE BRIDGE CONFIGURATIONS
R R
R R+ R
R+ R
R+ R R+ R R+ R
R R R+ R R R R R
R R R
V
B
V
B
V
B
V
B
V
O
V
O
V
O
V
O
(A) Single-Element
Varying
(B) Two-Element
Varying (1)
(C) Two-Element
Varying (2)
(D) All-Element
Varying
Linearity
Error:
V
O
:
0.5%/% 0.5%/% 0 0
V
B
4
R
R
2
R +
V
B
2
R
R
2
R +
V
B
2
R
R
V
B
R
R
R
Figure 2.4
In each case, t he value of t he fixed br idge r esist or , R, is chosen t o be equal t o t he
nominal value of t he var iable r esist or (s). The deviat ion of t he var iable r esist or (s)
about t he nominal value is pr opor t ional t o t he quant it y being measur ed, such as
st r ain (in t he case of a st r ain gage) or t emper at ur e ( in t he case of an RTD).
The sensitivity of a br idge is t he r at io of t he maximum expect ed change in t he
out put volt age t o t he excit at ion volt age. For inst ance, if V
B
= 10V, and t he fullscale
br idge out put is 10mV, t hen t he sensit ivit y is 1mV/V.
The single-element varying br idge is most suit ed for t emper at ur e sensing using
RTDs or t her mist or s. This configur at ion is also used wit h a single r esist ive st r ain
gage. All t he r esist ances ar e nominally equal, but one of t hem (t he sensor ) is
var iable by an amount R. As t he equat ion indicat es, t he r elat ionship bet ween t he
br idge out put and R is not linear . For example, if R = 100 and R = 0.1 (0.1%
BRI DGE CI RCUI TS
2.5
change in r esist ance), t he out put of t he br idge is 2.49875mV for V
B
= 10V. The
er r or is 2.50000mV 2.49875mV, or 0.00125mV. Conver t ing t his t o a % of fullscale
by dividing by 2.5mV yields an end-point linear it y er r or in per cent of appr oximat ely
0.05%. (Br idge end-point linear it y er r or is calculat ed as t he wor st er r or in % FS fr om
a st r aight line which connect s t he or igin and t he end point at FS, i.e. t he FS gain
er r or is not included). If R = 1, (1% change in r esist ance), t he out put of t he br idge
is 24.8756mV, r epr esent ing an end-point linear it y er r or of appr oximat ely 0.5%. The
end-point linear it y er r or of t he single-element br idge can be expr essed in equat ion
for m:
Single-Element Var ying
Br idge End-Point Linear it y Er r or % Change in Resist ance 2
It should be noted that the above nonlinearity refers to the nonlinearity of the bridge
itself and not the sensor. In pr act ice, most sensor s exhibit a cer t ain amount of t heir
own nonlinear it y which must be account ed for in t he final measur ement .
In some applicat ions, t he br idge nonlinear it y may be accept able, but t her e ar e
var ious met hods available t o linear ize br idges. Since t her e is a fixed r elat ionship
bet ween t he br idge r esist ance change and it s out put (shown in t he equat ions),
soft war e can be used t o r emove t he linear it y er r or in digit al syst ems. Cir cuit
t echniques can also be used t o linear ize t he br idge out put dir ect ly, and t hese will be
discussed shor t ly.
Ther e ar e t wo possibilit ies t o consider in t he case of t he t wo-element var ying br idge.
In t he fir st , Case (1), bot h element s change in t he same dir ect ion, such as t wo
ident ical st r ain gages mount ed adjacent t o each ot her wit h t heir axes in par allel.
The nonlinear it y is t he same as t hat of t he single-element var ying br idge, however
t he gain is t wice t hat of t he single-element var ying br idge. The t wo-element
var ying br idge is commonly found in pr essur e sensor s and flow met er syst ems.
A second configur at ion of t he t wo-element var ying br idge, Case (2), r equir es t wo
ident ical element s t hat var y in opposite dir ect ions. This could cor r espond t o t wo
ident ical st r ain gages: one mount ed on t op of a flexing sur face, and one on t he
bot t om. Not e t hat t his configur at ion is linear , and like t wo-element Case (1), has
t wice t he gain of t he single-element configur at ion. Anot her way t o view t his
configur at ion is t o consider t he t er ms R+R and RR as compr ising t he t wo
sect ions of a cent er -t apped pot ent iomet er .
The all-element varying br idge pr oduces t he most signal for a given r esist ance
change and is inher ent ly linear . It is an indust r y-st andar d configur at ion for load
cells which ar e const r uct ed fr om four ident ical st r ain gages.
Br idges may also be dr iven fr om const ant cur r ent sour ces as shown in Figur e 2.5.
Cur r ent dr ive, alt hough not as popular as volt age dr ive, has an advant age when t he
br idge is locat ed r emot ely fr om t he sour ce of excit at ion because t he wir ing r esist ance
does not int r oduce er r or s in t he measur ement . Not e also t hat wit h const ant cur r ent
excit at ion, all configur at ions ar e linear wit h t he except ion of t he single-element
var ying case.
BRI DGE CI RCUI TS
2.6
OUTPUT VOLTAGE AND LINEARITY ERROR FOR
CONSTANT CURRENT DRIVE BRIDGE CONFIGURATIONS
R R
R R+ R
R+ R
R+ R R+ R R+ R
R R R+ R R R R R
R R R
V
O
V
O
V
O
V
O
I
B
I
B
I
B
I
B
V
O
:
Linearity
Error:
0.25%/% 0 0 0
I
B
R
4
R
R
4
R +
I
B
2
R
I
B
R
I
B
2
R
(A) Single-Element
Varying
(B) Two-Element
Varying (1)
(C) Two-Element
Varying (2)
(D) All-Element
Varying
R
Figure 2.5
In summar y, t her e ar e many design issues r elat ing t o br idge cir cuit s. Aft er select ing
t he basic configur at ion, t he excit at ion met hod must be det er mined. The value of t he
excit at ion volt age or cur r ent must fir st be det er mined. Recall t hat t he fullscale
br idge out put is dir ect ly pr opor t ional t o t he excit at ion volt age (or cur r ent ). Typical
br idge sensit ivit es ar e 1mV/V t o 10mV/V. Alt hough lar ge excit at ion volt ages yield
pr opor t ionally lar ger fullscale out put volt ages, t hey also r esult in higher power
dissipat ion and t he possibilit y of sensor r esist or self-heat ing er r or s. On t he ot her
hand, low values of excit at ion volt age r equir e mor e gain in t he condit ioning cir cuit s
and incr ease t he sensit ivit y t o noise.
Regar dless of it s value, t he st abilit y of t he excit at ion volt age or cur r ent dir ect ly
affect s t he over all accur acy of t he br idge out put . St able r efer ences and/or r at iomet r ic
t echniques ar e r equir ed t o maint ain desir ed accur acy.
BRI DGE CI RCUI TS
2.7
BRIDGE CONSIDERATIONS
n Selecting Configuration (1, 2, 4 - Element Varying)
n Selection of Voltage or Current Excitation
n Stability of Excitation Voltage or Current
n Bridge Sensitivity: FS Output / Excitation Voltage
1mV / V to 10mV / V Typical
n Fullscale Bridge Outputs: 10mV - 100mV Typical
n Precision, Low Noise Amplification / Conditioning
Techniques Required
n Linearization Techniques May Be Required
n Remote Sensors Present Challenges
Figure 2.6
AMP LI FYI NG AND LI NEARI ZI NG BRI DGE OUTP UTS
The out put of a single-element var ying br idge may be amplified by a single pr ecision
op-amp connect ed in t he inver t ing mode as shown in Figur e 2.7. This cir cuit ,
alt hough simple, has poor gain accur acy and also unbalances t he br idge due t o
loading fr om R
F
and t he op amp bias cur r ent . The R
F
r esist or s must be car efully
chosen and mat ched t o maximize t he common mode r eject ion (CMR). Also it is
difficult t o maximize t he CMR while at t he same t ime allowing differ ent gain
opt ions. In addit ion, t he out put is nonlinear . The key r edeeming feat ur e of t he
cir cuit is t hat it is capable of single supply oper at ion and r equir es a single op amp.
Not e t hat t he R
F
r esist or connect ed t o t he non-inver t ing input is r et ur ned t o V
S
/2
(r at her t han gr ound) so t hat bot h posit ive and negat ive values of R can be
accommodat ed, and t he op amp out put is r efer enced t o V
S
/2.
A much bet t er appr oach is t o use an inst r ument at ion amplifier (in-amp) as shown in
Figur e 2.8. This efficient cir cuit pr ovides bet t er gain accur acy (usually set wit h a
single r esist or , R
G
) and does not unbalance t he br idge. Excellent common mode
r eject ion can be achieved wit h moder n in-amps. Due t o t he br idge's int r insic
char act er ist ics, t he out put is nonlinear , but t his can be cor r ect ed in t he soft war e
(assuming t hat t he in-amp out put is digit ized using an analog-t o-digit al conver t er
and followed by a micr ocont r oller or micr opr ocessor ). Inst r ument at ion amplifier s
such as t he AD620, AD623, and AD627 can be used in single supply applicat ions
pr ovided t he r est r ict ions on t he gain and input and out put volt age swings ar e
obser ved. (For a det ailed discussion of t hese impor t ant consider at ions, see Sect ion
3).
BRI DGE CI RCUI TS
2.8
USING A SINGLE OP AMP AS A BRIDGE AMPLIFIER
FOR A SINGLE-ELEMENT VARYING BRIDGE
V
B
+V
S
R R
R
R+ R
R
F
R
F
+

V
S
2
Figure 2.7
USING AN INSTRUMENTATION AMPLIFIER
WITH A SINGLE-ELEMENT VARYING BRIDGE
V
B
R R
R
+

IN AMP
REF
V
OUT
R
G
+V
S
-V
S
* R+ R
* SEE TEXT REGARDING
SINGLE-SUPPLY OPERATION
V
B
4
R
R
2
R +
V
OUT
= GAIN
Figure 2.8
BRI DGE CI RCUI TS
2.9
Var ious t echniques ar e available t o linear ize br idges, but it is impor t ant t o
dist inguish bet ween t he linear it y of t he br idge equat ion and t he linear it y of t he
sensor r esponse t o t he phenomenon being sensed. For example, if t he act ive element
is an RTD, t he br idge used t o implement t he measur ement might have per fect ly
adequat e linear it y; yet t he out put could st ill be nonlinear due t o t he RTD's
nonlinear it y. Manufact ur er s of sensor s employing br idges addr ess t he nonlinear it y
issue in a var iet y of ways, including keeping t he r esist ive swings in t he br idge small,
shaping compliment ar y nonlinear r esponse int o t he act ive element s of t he br idge,
using r esist ive t r ims for fir st -or der cor r ect ions, and ot her s.
Figur e 2.9 shows a single-element var ying act ive br idge in which an op amp
pr oduces a for ced null, by adding a volt age in ser ies wit h t he var iable ar m. That
volt age is equal in magnit ude and opposit e in polar it y t o t he incr ement al volt age
acr oss t he var ying element and is linear wit h R. Since it is an op amp out put , it
can be used as a low impedance out put point for t he br idge measur ement . This
act ive br idge has a gain of t wo over t he st andar d single-element var ying br idge, and
t he out put is linear , even for lar ge values of R. Because of t he small out put signal,
t his br idge must usually be followed by an second amplifier . The amplifier used in
t his cir cuit r equir es dual supplies because it s out put must go negat ive.
LINEARIZING A SINGLE-ELEMENT VARYING BRIDGE
METHOD 1
V
B
R R
R
R+ R
+

+V
S
-V
S
V
OUT
V
B
R
R

] ]
] ]
] ]

2
Figure 2.9
Anot her cir cuit for linear izing a single-element var ying br idge is shown in Figur e
2.10. The bot t om of t he br idge is dr iven by an op amp, which maint ains a const ant
cur r ent in t he var ying r esist ance element . The out put signal is t aken fr om t he r ight -
hand leg of t he br idge and amplified by a non-inver t ing op amp. The out put is
linear , but t he cir cuit r equir es t wo op amps which must oper at e on dual supplies. In
addit ion, R1 and R2 must be mat ched for accur at e gain.
BRI DGE CI RCUI TS
2.10
LINEARIZING A SINGLE-ELEMENT VARYING BRIDGE
METHOD 2
+

+V
S
-V
S
R
R+ R
R
R
+

+V
S
-V
S
V
B
R2
R1
V
OUT
V
OUT
V
B
R
R
R
R

] ]
] ]
] ]
+ +

] ]
] ]
] ]
2
1
2
1

Figure 2.10
A cir cuit for linear izing a volt age-dr iven t wo-element var ying br idge is shown in
Figur e 2.11. This cir cuit is similar t o Figur e 2.9 and has t wice t he sensit ivit y. A dual
supply op amp is r equir ed. Addit ional gain may be necessar y.
LINEARIZING A TWO-ELEMENT VARYING BRIDGE
METHOD 1 (CONSTANT VOLTAGE DRIVE)
V
B
R
R
R+ R
+

+V
S
-V
S
V
OUT
V
B
R
R

] ]
] ]
] ]

R+ R
Figure 2.11
BRI DGE CI RCUI TS
2.11
The t wo-element var ying br idge cir cuit in Figur e 2.12 uses an op amp, a sense
r esist or , and a volt age r efer ence t o maint ain a const ant cur r ent t hr ough t he br idge
(I
B
= V
REF
/R
SENSE
). The cur r ent t hr ough each leg of t he br idge r emains const ant
(I
B
/2) as t he r esist ances change, t her efor e t he out put is a linear funct ion of R. An
inst r ument at ion amplifier pr ovides t he addit ional gain. This cir cuit can be oper at ed
on a single supply wit h t he pr oper choice of amplifier s and signal levels.
LINEARIZING A TWO-ELEMENT VARYING BRIDGE
METHOD 2 (CONSTANT CURRENT DRIVE)
R
R
+

IN AMP
REF
V
OUT
R
G
+V
S
-V
S
*
R+ R
* SEE TEXT REGARDING
SINGLE-SUPPLY OPERATION
+

R+ R
+V
S
-V
S
*
V
REF
R
SENSE
I
B
I
B
V
OUT
=
I
B
R
2
GAIN
Figure 2.12
DRI VI NG BRI DGES
Wir ing r esist ance and noise pickup ar e t he biggest pr oblems associat ed wit h
r emot ely locat ed br idges. Figur e 2.13 shows a 350 st r ain gage which is connect ed
t o t he r est of t he br idge cir cuit by 100 feet of 30 gage t wist ed pair copper wir e. The
r esist ance of t he wir e at 25C is 0.105/ft , or 10.5 for 100ft . The t ot al lead
r esist ance in ser ies wit h t he 350 st r ain gage is t her efor e 21. The t emper at ur e
coefficient of t he copper wir e is 0.385%/C. Now we will calculat e t he gain and offset
er r or in t he br idge out put due t o a +10C t emper at ur e r ise in t he cable. These
calculat ions ar e easy t o make, because t he br idge out put volt age is simply t he
differ ence bet ween t he out put of t wo volt age divider s, each dr iven fr om a +10V
sour ce.
BRI DGE CI RCUI TS
2.12
ERRORS PRODUCED BY WIRING RESISTANCE
FOR REMOTE RESISTIVE BRIDGE SENSOR
+ -
0 23.45mV
(5.44mV 28.83mV)
V
O
350
350
350
R
COMP
21
350 353.5 FS
+10V
R
LEAD
10.5 ( (10.904) )
R
LEAD
10.5 ( (10.904) )
STRAIN GAGE
100 FEET, 30 GAGE COPPER WIRE = 10.5 @ 25 C
TC = 0.385%/ C
ASSUME +10 C TEMPERATURE CHANGE
NUMBERS IN ( ) ARE @ +35 C
OFFSET ERROR OVER TEMPERATURE = +23%FS
GAIN ERROR OVER TEMPERATURE = 0.26%FS
Figure 2.13
The fullscale var iat ion of t he st r ain gage r esist ance (wit h flex) above it s nominal
350 value is +1% (+3.5), cor r esponding t o a fullscale st r ain gage r esist ance of
353.5 which causes a br idge out put volt age of +23.45mV. Not ice t hat t he addit ion
of t he 21 R
COMP
r esist or compensat es for t he wir ing r esist ance and balances t he
br idge when t he st r ain gage r esist ance is 350. Wit hout R
COMP
, t he br idge would
have an out put offset volt age of 145.63mV for a nominal st r ain gage r esist ance of
350. This offset could be compensat ed for in soft war e just as easily, but for t his
example, we chose t o do it wit h R
COMP
.
Assume t hat t he cable t emper at ur e incr eases +10C above nominal r oom
t emper at ur e. This r esult s in a t ot al lead r esist ance incr ease of +0.404
(10.50.00385/C10C) in each lead. Note: The values in parentheses in the
diagram indicate the values at +35C. The t ot al addit ional lead r esist ance (of t he t wo
leads) is +0.808. Wit h no st r ain, t his addit ional lead r esist ance pr oduces an offset
of +5.44mV in t he br idge out put . Fullscale st r ain pr oduces a br idge out put of
+28.83mV (a change of +23.39mV fr om no st r ain). Thus t he incr ease in t emper at ur e
pr oduces an offset volt age er r or of +5.44mV (+23% fullscale) and a gain er r or of
0.06mV (23.39mV 23.45mV), or 0.26% fullscale. Not e t hat t hese er r or s ar e
pr oduced solely by t he 30 gage wir e, and do not include any t emper at ur e coefficient
er r or s in t he st r ain gage it self.
The effect s of wir ing r esist ance on t he br idge out put can be minimized by t he 3-wir e
connect ion shown in Figur e 2.14. We assume t hat t he br idge out put volt age is
measur ed by a high impedance device, t her efor e t her e is no cur r ent in t he sense
lead. Not e t hat t he sense lead measur es t he volt age out put of a divider : t he t op half
is t he br idge r esist or plus t he lead r esist ance, and t he bot t om half is st r ain gage
r esist ance plus t he lead r esist ance. The nominal sense volt age is t her efor e
BRI DGE CI RCUI TS
2.13
independent of t he lead r esist ance. When t he st r ain gage r esist ance incr eases t o
fullscale (353.5), t he br idge out put incr eases t o +24.15mV.
Incr easing t he t emper at ur e t o +35C incr eases t he lead r esist ance by +0.404 in
each half of t he divider . The fullscale br idge out put volt age decr eases t o +24.13mV
because of t he small loss in sensit ivit y, but t her e is no offset er r or . The gain er r or
due t o t he t emper at ur e incr ease of +10C is t her efor e only 0.02mV, or 0.08% of
fullscale. Compar e t his t o t he +23% fullscale offset er r or and t he 0.26% gain er r or
for t he t wo-wir e connect ion shown in Figur e 2.13.
3-WIRE CONNECTION TO REMOTE
BRIDGE ELEMENT (SINGLE-ELEMENT VARYING)
+ -
0 24.15mV
(0 24.13mV)
V
O
350
350
350
350 353.5 FS
+10V
R
LEAD
10.5 ( (10.904) )
R
LEAD
10.5 ( (10.904) )
STRAIN GAGE
100 FEET, 30 GAGE COPPER WIRE = 10.5 @ 25 C
TC = 0.385%/ C
ASSUME +10 C TEMPERATURE CHANGE
NUMBERS IN ( ) ARE @ +35 C
OFFSET ERROR OVER TEMPERATURE = 0%FS
GAIN ERROR OVER TEMPERATURE = 0.08%FS
I = 0
Figure 2.14
The t hr ee-wir e met hod wor ks well for r emot ely locat ed r esist ive element s which
make up one leg of a single-element var ying br idge. However , all-element var ying
br idges gener ally ar e housed in a complet e assembly, as in t he case of a load cell.
When t hese br idges ar e r emot ely locat ed fr om t he condit ioning elect r onics, special
t echniques must be used t o maint ain accur acy.
Of par t icular concer n is maint aining t he accur acy and st abilit y of t he br idge
excit at ion volt age. The br idge out put is dir ect ly pr opor t ional t o t he excit at ion
volt age, and any dr ift in t he excit at ion volt age pr oduces a cor r esponding dr ift in t he
out put volt age.
For t his r eason, most all-element var ying br idges (such as load cells) ar e six-lead
assemblies: t wo leads for t he br idge out put , t wo leads for t he br idge excit at ion, and
t wo sense leads. This met hod (called Kelvin or 4-wir e sensing) is shown in Figur e
2.15. The sense lines go t o high impedance op amp input s, t hus t her e is minimal
er r or due t o t he bias cur r ent induced volt age dr op acr oss t heir lead r esist ance. The
op amps maint ain t he r equir ed excit at ion volt age t o make t he volt age measur ed
bet ween t he sense leads always equal t o V
B
. Alt hough Kelvin sensing eliminat es
BRI DGE CI RCUI TS
2.14
er r or s due t o volt age dr ops in t he wir ing r esist ance, t he dr ive volt ages must st ill be
highly st able since t hey dir ect ly affect t he br idge out put volt age. In addit ion, t he op
amps must have low offset , low dr ift , and low noise.
KELVIN (4-WIRE) SENSING MINIMIZES ERRORS
DUE TO LEAD RESISTANCE
6-LEAD
BRIDGE
R
LEAD
R
LEAD
+SENSE
SENSE
+FORCE
FORCE
+
+
+V
B
V
O
Figure 2.15
The const ant cur r ent excit at ion met hod shown in Figur e 2.16 is anot her met hod for
minimizing t he effect s of wir ing r esist ance on t he measur ement accur acy. However ,
t he accur acy of t he r efer ence, t he sense r esist or , and t he op amp all influence t he
over all accur acy.
A ver y power ful ratiometric t echnique which includes Kelvin sensing t o minimize
er r or s due t o wir ing r esist ance and also eliminat es t he need for an accur at e
excit at ion volt age is shown in Figur e 2.17. The AD7730 measur ement ADC can be
dr iven fr om a single supply volt age which is also used t o excit e t he r emot e br idge.
Bot h t he analog input and t he r efer ence input t o t he ADC ar e high impedance and
fully differ ent ial. By using t he + and SENSE out put s fr om t he br idge as t he
differ ent ial r efer ence t o t he ADC, t her e is no loss in measur ement accur acy if t he
act ual br idge excit at ion volt age var ies. The AD7730 is one of a family of sigma-delt a
ADCs wit h high r esolut ion (24 bit s) and int er nal pr ogr ammable gain amplifier s
(PGAs) and is ideally suit ed for br idge applicat ions. These ADCs have self- and
syst em calibr at ion feat ur es which allow offset and gain er r or s due t o t he ADC t o be
minimized. For inst ance, t he AD7730 has an offset dr ift of 5nV/C and a gain dr ift of
2ppm/C. Offset and gain er r or s can be r educed t o a few micr ovolt s using t he syst em
calibr at ion feat ur e. (A mor e det ailed discussion of t hese ADCs can be found in
Sect ion 8).
BRI DGE CI RCUI TS
2.15
CONSTANT CURRENT EXCITATION
MINIMIZES WIRING RESISTANCE ERRORS
4-LEAD
BRIDGE
R
LEAD
+
R
LEAD
R
SENSE
V
REF
V
O
I
I
I
I =
V
REF
R
SENSE
Figure 2.16
DRIVING REMOTE BRIDGE USING KELVIN (4-WIRE)
SENSING AND RATIOMETRIC CONNECTION TO ADC
+5V
AV
DD
GND
+ A
IN
A
IN
+ V
REF
V
REF
R
LEAD
R
LEAD
6-LEAD
BRIDGE
AD7730
ADC
24 BITS
+SENSE
SENSE
V
O
+FORCE
FORCE
DV
DD
+5V/+3V
Figure 2.17
BRI DGE CI RCUI TS
2.16
Maint aining an accur acy of 0.1% or bet t er wit h a fullscale br idge out put volt age of
20mV r equir es t hat t he sum of all offset er r or s be less t han 20V. Figur e 2.18 shows
some t ypical sour ces of offset er r or t hat ar e inevit able in a syst em. Par asit ic
t her mocouples whose junct ions ar e at differ ent t emper at ur es can gener at e volt ages
bet ween a few and t ens of micr ovolt s for a 1C t emper at ur e differ ent ial. The
diagr am shows a t ypical par asit ic junct ion for med bet ween t he copper pr int ed cir cuit
boar d t r aces and t he kovar pins of t he IC amplifier . This t her mocouple volt age is
about 35V/C t emper at ur e differ ent ial. The t her mocouple volt age is significant ly
less when using a plast ic package wit h a copper lead fr ame.
The amplifier offset volt age and bias cur r ent ar e ot her sour ces of offset er r or . The
amplifier bias cur r ent must flow t hr ough t he sour ce impedance. Any unbalance in
eit her t he sour ce r esist ances or t he bias cur r ent s pr oduce offset er r or s. In addit ion,
t he offset volt age and bias cur r ent s ar e a funct ion of t emper at ur e. High per for mance
low offset , low offset dr ift , low bias cur r ent , and low noise pr ecision amplifier s such
as t he OP177 or AD707 ar e r equir ed. In some cases, chopper -st abilized amplifier s
such as t he AD8551/AD8552/AD8554 may be t he only solut ion.
TYPICAL SOURCES OF OFFSET VOLTAGE
+ V
B
V
OS
V
O
+
T1
T2
COPPER
TRACES
KOVAR
PINS
I
B
+
I
B
THERMOCOUPLE VOLTAGE
35V/ C (T1 T2)
AMP
Figure 2.18
BRI DGE CI RCUI TS
2.17
AC br idge excit at ion as shown in Figur e 2.19 can effect ively r emove offset volt ages
in ser ies wit h t he br idge out put . The concept is simple. The net br idge out put
volt age is measur ed under t wo condit ions as shown. The fir st measur ement yields a
measur ement V
A
, wher e V
A
is t he sum of t he desir ed br idge out put volt age V
O
and
t he net offset er r or volt age E
OS
. The polar it y of t he br idge excit at ion is r ever sed,
and a second measur ement V
B
is made. Subt r act ing V
B
fr om V
A
yields 2V
O
, and
t he offset er r or t er m E
OS
cancels as shown.
Obviously, t his t echnique r equir es a highly accur at e measur ement ADC (such as t he
AD7730) as well as a micr ocont r oller t o per for m t he subt r act ion. If a r at iomet r ic
r efer ence is desir ed, t he ADC must also accommodat e t he changing polar it y of t he
r efer ence volt age. Again, t he AD7730 includes t his capabilit y.
AC EXCITATION MINIMIZES OFFSET ERRORS
+ V
B
+ V
B
E
OS
E
OS
+
+
V
O
V
O
+
V
A
= V
O
+ E
OS
+
-
+
V
B
= V
O
+ E
OS
V
A
V
B
= (V
O
+ E
OS
) ( V
O
+ E
OS
) = 2 V
O
E
OS
= SUM OF ALL OFFSET ERRORS
REVERSE
DRIVE
VOLTAGES
NORMAL
DRIVE
VOLTAGES
Figure 2.19
P-Channel and N-Channel MOSFETs can be configur ed as an AC br idge dr iver as
shown in Figur e 2.20. Dedicat ed br idge dr iver chips ar e also available, such as t he
Micr el MIC4427. Not e t hat because of t he on-r esist ance of t he MOSFETs, Kelvin
sensing must be used in t hese applicat ions. It is also impor t ant t hat t he dr ive
signals be non-over lapping t o pr event excessive MOSFET swit ching cur r ent s. The
AD7730 ADC has on chip cir cuit r y t o gener at e t he r equir ed non-over lapping dr ive
signals for AC excit at ion.
BRI DGE CI RCUI TS
2.18
SIMPLIFIED AC BRIDGE DRIVE CIRCUIT
+ V
B
V
O
+ V
B
Q1
Q2
Q3
Q4
+ SENSE
SENSE
V
3,4
V
1,2
V
1,2
V
3,4
Q1,Q2 ON Q1,Q2 ON
Q3,Q4 ON Q3,Q4 ON
Figure 2.20
BRI DGE CI RCUI TS
2.19
REFERENCES
1. Ramon Pallas-Ar eny and J ohn G. Webst er , Sen sor s a n d Si gn a l
Con d i t i on i n g, J ohn Wiley, New Yor k, 1991.
2. Dan Sheingold, Edit or , Tr a n sd u cer I n t er fa ci n g Ha n d b ook , Analog
Devices, Inc., 1980.
3. Walt Kest er , Edit or , 1992 Amp li fi er Ap p li ca t i on s Gu i d e, Sect ion 2, 3,
Analog Devices, Inc., 1992.
4. Walt Kest er , Edit or , Syst em Ap p li ca t i on s Gu i d e, Sect ion 1, 6, Analog
5. AD7730 Dat a Sheet , Analog Devices, available at ht t p://www.analog.com.
AMP LI FI ERS FOR SI GNAL CONDI TI ONI NG
3.1
SECTI ON 3
Wa l t Kest er , J a m es Br ya n t , Wa l t J u n g
I NTRODUCTI ON
This sect ion examines t he cr it ical par amet er s of amplifier s for use in pr ecision signal
condit ioning applicat ions. Offset volt ages for pr ecision IC op amps can be as low as
10V wit h cor r esponding t emper at ur e dr ift s of 0.1V/C. Chopper st abilized op amps
pr ovide offset s and offset volt age dr ift s which cannot be dist inguished fr om noise.
Open loop gains gr eat er t han 1 million ar e common, along wit h common mode and
power supply r eject ion r at ios of t he same magnit ude. Applying t hese pr ecision
amplifier s while maint aining t he amplifier per for mance can pr esent significant
challenges t o a design engineer , i.e., ext er nal passive component select ion and PC
boar d layout .
It is impor t ant t o under st and t hat DC open-loop gain, offset volt age, power supply
r eject ion (PSR), and common mode r eject ion (CMR) alone should not be t he only
consider at ions in select ing pr ecision amplifier s. The AC per for mance of t he amplifier
is also impor t ant , even at "low" fr equencies. Open-loop gain, PSR, and CMR all have
r elat ively low cor ner fr equencies, and t her efor e what may be consider ed "low"
fr equency may act ually fall above t hese cor ner fr equencies, incr easing er r or s above
t he value pr edict ed solely by t he DC par amet er s. For example, an amplifier having a
DC open-loop gain of 10 million and a unit y-gain cr ossover fr equency of 1MHz has a
cor r esponding cor ner fr equency of 0.1Hz! One must t her efor e consider t he open loop
gain at t he act ual signal fr equency. The r elat ionship bet ween t he single-pole unit y-
gain cr ossover fr equency, f
u
, t he signal fr equency, f
sig
, and t he open-loop gain
A
VOL(fsig)
(measur ed at t he signal fr equency is given by:
A
VOL f
sig
f
u
f
sig
( )
.
It t he example above, t he open loop gain is 10 at 100kHz, and 100,000 at 10Hz.
Loss of open loop gain at t he fr equency of int er est can int r oduce dist or t ion,
especially at audio fr equencies. Loss of CMR or PSR at t he line fr equency or
har monics t her eof can also int r oduce er r or s.
The challenge of select ing t he r ight amplifier for a par t icular signal condit ioning
applicat ion has been complicat ed by t he sheer pr olifer at ion of var ious t ypes of
amplifier s in var ious pr ocesses (Bipolar , Complement ar y Bipolar , BiFET, CMOS,
BiCMOS, et c.) and ar chit ect ur es (t r adit ional op amps, inst r ument at ion amplifier s,
chopper amplifier s, isolat ion amplifier s, et c.) In addit ion, a wide select ion of
pr ecision amplifier s ar e now available which oper at e on single supply volt ages which
complicat es t he design pr ocess even fur t her because of t he r educed signal swings
and volt age input and out put r est r ict ions. Offset volt age and noise ar e now a mor e
significant por t ion of t he input signal. Select ion guides and par amet r ic sear ch
engines which can simplify t his pr ocess somewhat ar e available on t he wor ld-wide-
web (ht t p://www.analog.com) as well as on CDROM.
3.2
In t his sect ion, we will fir st look at some key per for mance specificat ions for pr ecision
op amps. Ot her amplifier s will t hen be examined such as inst r ument at ion
amplifier s, chopper amplifier s, and isolat ion amplifier s. The implicat ions of single
supply oper at ion will be discussed in det ail because of t heir significance in t oday's
designs, which oft en oper at e fr om bat t er ies or ot her low power sour ces.
AMPLIFIERS FOR SIGNAL CONDITIONING
n Input Offset Voltage <100V
n Input Offset Voltage Drift <1V/C
n Input Bias Current <2nA
n Input Offset Current <2nA
n DC Open Loop Gain >1,000,000
n Unity Gain Bandwidth Product, f
u
500kHz - 5MHz
n Always Check Open Loop Gain at Signal Frequency!
n 1/f (0.1Hz to 10Hz) Noise <1V p-p
n Wideband Noise <10nV/ Hz
n CMR, PSR >100dB
n Single Supply Operation
n Power Dissipation
Figure 3.1
P RECI SI ON OP AMP CHARACTERI STI CS
I n p u t Offset Volt a ge
Input offset volt age er r or is usually one of t he lar gest er r or sour ces for pr ecision
amplifier cir cuit designs. However , it is a syst emic er r or and can usually be dealt
wit h by using a manual offset null t r im or by syst em calibr at ion t echniques using a
micr ocont r oller or micr opr ocessor . Bot h solut ions car r y a cost penalt y, and t oday's
pr ecision op amps offer init ial offset volt ages as low as 10V for bipolar devices, and
far less for chopper st abilized amplifier s. Wit h low offset amplifier s, it is possible t o
eliminat e t he need for manual t r ims or syst em calibr at ion r out ines.
3.3
Measur ing input offset volt ages of a few micr ovolt s r equir es t hat t he t est cir cuit does
not int r oduce mor e er r or t han t he offset volt age it self. Figur e 3.2 shows a cir cuit for
measur ing offset volt age. The cir cuit amplifies t he input offset volt age by t he noise
gain (1001). The measur ement is made at t he amplifier out put using an accur at e
digit al volt met er . The offset r efer r ed t o t he input (RTI) is calculat ed by dividing t he
out put volt age by t he noise gain. The small sour ce r esist ance seen at R1| | R2
r esult s in negligible bias cur r ent cont r ibut ion t o t he measur ed offset volt age. For
example, 2nA bias cur r ent flowing t hr ough t he 10 r esist or pr oduces a 0.02V er r or
r efer r ed t o t he input .
MEASURING INPUT OFFSET VOLTAGE
+
+V
S
V
S
R1, 10
10
R2, 10k
10k
V
OUT
= 1001 V
OS
V
OS
V
OS
=
V
OUT
1001
For OP177A:
V
OS
= 10V maximum
V
OS
DRIFT = 0.1V/C maximum
V
OS
STABILITY = 0.2V/month typical
V
OUT
= 1 +
R2
R1
V
OS
Figure 3.2
As simple as it looks, t his cir cuit may give inaccur at e r esult s. The lar gest pot ent ial
sour ce of er r or comes fr om par asit ic t her mocouple junct ions for med wher e t wo
differ ent met als ar e joined. The t her mocouple volt age for med by t emper at ur e
differ ence bet ween t wo junct ions can r ange fr om 2V/C t o mor e t han 40V/C. Not e
t hat in t he cir cuit addit ional r esist or s have been added t o t he non-inver t ing input in
or der t o exact ly mat ch t he t her mocouple junct ions in t he inver t ing input pat h.
The accur acy of t he measur ement depends on t he mechanical layout of t he
component s and how t hey ar e placed on t he PC boar d. Keep in mind t hat t he t wo
connect ions of a component such as a r esist or cr eat e t wo equal, but opposit e polar it y
t her moelect r ic volt ages (assuming t hey ar e connect ed t o t he same met al, such as t he
copper t r ace on a PC boar d) which cancel each ot her assuming both are at exactly the
3.4
same temperature. Clean connect ions and shor t lead lengt hs help t o minimize
t emper at ur e gr adient s and incr ease t he accur acy of t he measur ement .
Air flow should be minimal so t hat all t he t her mocouple junct ions st abilize at t he
same t emper at ur e. In some cases, t he cir cuit should be placed in a small closed
cont ainer t o eliminat e t he effect s of ext er nal air cur r ent s. The cir cuit should be
placed flat on a sur face so t hat convect ion cur r ent s flow up and off t he t op of t he
boar d, not acr oss t he component s as would be t he case if t he boar d was mount ed
ver t ically.
Measur ing t he offset volt age shift over t emper at ur e is an even mor e demanding
challenge. Placing t he pr int ed cir cuit boar d cont aining t he amplifier being t est ed in
a small box or plast ic bag wit h foam insulat ion pr event s t he t emper at ur e chamber
air cur r ent fr om causing t her mal gr adient s acr oss t he par asit ic t her mocouples. If
cold t est ing is r equir ed, a dr y nit r ogen pur ge is r ecommended. Localized
t emper at ur e cycling of t he amplifier it self using a Ther most r eam-t ype heat er /cooler
may be an alt er nat ive, however t hese unit s t end t o gener at e quit e a bit of air flow
which can be t r oublesome.
In addit ion t o t emper at ur e r elat ed dr ift , t he offset volt age of an amplifier changes as
t ime passes. This aging effect is gener ally specified as long-term stability in
V/mont h, or V/1000 hour s, but t his is misleading. Since aging is a "dr unkar d's
walk" phenomenon, it is pr opor t ional t o t he square root of t he elapsed t ime. An
aging r at e of 1V/1000 hour s becomes about 3V/year , not 9V/year . Long-t er m
st abilit y of t he OP177 and t he AD707 is appr oximat ely 0.3V/mont h. This r efer s t o
a t ime per iod after t he fir st 30 days of oper at ion. Excluding t he init ial hour of
oper at ion, changes in t he offset volt age of t hese devices dur ing t he fir st 30 days of
oper at ion ar e t ypically less t han 2V.
As a gener al r ule of t humb, it is pr udent t o cont r ol amplifier offset volt age by device
select ion whenever possible, bus somet imes t r im may be desir ed. Many pr ecision op
amps have pins available for opt ional offset null. Gener ally, t wo pins ar e joined by a
pot ent iomet er , and t he wiper goes t o one of t he supplies t hr ough a r esist or as shown
in Figur e 3.3. If t he wiper is connect ed t o t he wr ong supply, t he op amp will
pr obably be dest r oyed, so t he dat a sheet inst r uct ions must be car efully obser ved!
The r ange of offset adjust ment in a pr ecision op amp should be no mor e t han t wo or
t hr ee t imes t he maximum offset volt age of t he lowest gr ade device, in or der t o
minimize t he sensit ivit y of t hese pins. The volt age gain of an op amp bet ween it s
offset adjust ment pins and it s out put may act ually be gr eat er t han t he gain at it s
signal input s! It is t her efor e ver y impor t ant t o keep t hese pins fr ee of noise. It is
inadvisable t o have long leads fr om an op amp t o a r emot e pot ent iomet er . To
minimize any offset er r or due t o supply cur r ent , connect R1 dir ect ly t o t he per t inent
device supply pin, such as pin 7 shown in t he diagr am.
3.5
OP177/AD707 OFFSET ADJUSTMENT PINS
n R1 = 10k , R2 = 2k , OFFSET ADJUST RANGE = 200V
n R1 = 0, R1 = 20k , OFFSET ADJUST RANGE = 3mV
R1
R2
2
3
4
7
1
8
6
+

+V
S
V
S
Figure 3.3
It is impor t ant t o not e t hat t he offset dr ift of an op amp wit h t emper at ur e will var y
wit h t he set t ing of it s offset adjust ment . In most cases a bipolar op amp will have
minimum dr ift at minimum offset . The offset adjust ment pins should t her efor e be
used only t o adjust t he op amp's own offset , not t o cor r ect any syst em offset er r or s,
since t his would be at t he expense of incr eased t emper at ur e dr ift . The dr ift penalt y
for a J FET input op amp is much wor se t han for a bipolar input and is in t he or der
of 4V/C for each millivolt of nulled offset volt age. It is gener ally bet t er t o cont r ol
t he offset volt age by pr oper select ion of devices and device gr ades. Dual, t r iple, quad,
and single op amps in small packages do not gener ally have null capabilit y because
of pin count limit at ions, and offset adjust ment s must be done elsewher e in t he
syst em when using t hese devices. This can be accomplished wit h minimal impact on
dr ift by a univer sal t r im, which sums a small volt age int o t he input .
I n p u t Offset Volt a ge a n d I n p u t Bi a s Cu r r en t Mod els
Thus far , we have consider ed only t he op amp input offset volt age. However , t he
input bias cur r ent s also cont r ibut e t o offset er r or as shown in t he gener alized model
of Figur e 3.4. It is useful t o r efer all offset s t o t he op amp input (RTI) so t hat t hey
can be easily compar ed wit h t he input signal. The equat ions in t he diagr am ar e
given for t he t ot al offset volt age r efer r ed t o input (RTI) and r efer r ed t o out put
(RTO).
3.6
OP AMP TOTAL OFFSET VOLTAGE MODEL
+
V
OS
R2 R1
R3
I
B
I
B+
V
OUT
n n
n n
OFFSET (RTO) = V
OS
1 +
R2
R1
+ I
B+
R3
R2
R1
1 + I
B
R2
OFFSET (RTI ) = V
OS
+ I
B+
R3 I
B
R1R2
R1 + R2
FOR BIAS CURRENT CANCELLATION:
OFFSET (RTI) = V
OS
IF I
B+
= I
B
AND R3 =
R1R2
R1 + R2
NOISE GAIN =
1 +
R2
R1
NG =
GAIN FROM
"A" TO OUTPUT
=
GAIN FROM
"B" TO OUTPUT
=
R2
R1
A
B
Figure 3.4
For a pr ecision op amp having a st andar d bipolar input st age using eit her PNPs or
NPNs, t he input bias cur r ent s ar e t ypically 50nA t o 400nA and ar e well mat ched.
By making R3 equal t o t he par allel combinat ion of R1 and R2, t heir effect on t he net
RTI and RTO offset volt age is appr oximat ely canceled, t hus leaving t he offset
cur r ent , i.e., t he differ ence bet ween t he input cur r ent s as an er r or . This cur r ent is
usually an or der of magnit ude lower t han t he bias cur r ent specificat ion. This
scheme, however , does not wor k for bias-cur r ent compensat ed bipolar op amps (such
as t he OP177 and t he AD707) as shown in Figur e 3.5. Bias-cur r ent compensat ed
input st ages have most of t he good feat ur es of t he simple bipolar input st age: low
offset and dr ift , and low volt age noise. Their bias cur r ent is low and fair ly st able
over t emper at ur e. The addit ional cur r ent sour ces r educe t he net bias cur r ent s
t ypically t o bet ween 0.5nA and 10nA. However , t he signs of t he + and input bias
cur r ent s may or may not be t he same, and t hey ar e not well mat ched, but ar e ver y
low. Typically, t he specificat ion for t he offset current (t he differ ence bet ween t he +
and input bias cur r ent s) in bias-cur r ent compensat ed op amps is gener ally about
t he same as t he individual bias cur r ent s. In t he case of t he st andar d bipolar
differ ent ial pair wit h no bias-cur r ent compensat ion, t he offset cur r ent specificat ion is
t ypically five t o t en t imes lower t han t he bias cur r ent specificat ion.
3.7
INPUT BIAS CURRENT COMPENSATED OP AMPS
UNCOMPENSATED COMPENSATED
n n MATCHED BIAS CURRENTS
n n SAME SIGN
n n 50nA - 10A
n n 50pA - 5nA (Super Beta)
n n I
OFFSET
<< I
BIAS
n n LOW, UNMATCHED BIAS CURRENTS
n n CAN HAVE DIFFERENT SIGNS
n n 0.5nA - 10nA
n n HIGHER CURRENT NOISE
n n I
OFFSET
I
BIAS
V
IN
V
IN
Figure 3.5
DC Op en Loop Ga i n Non li n ea r i t y
It is well under st ood t hat in or der t o maint ain accur acy, a pr ecision amplifier 's DC
open loop gain, A
VOL
, should be high. This can be seen by examining t he equat ion
for t he closed loop gain:
Closed Loop Gain A
VCL
NG
NG
A
VOL

+ 1
.
Noise gain (NG) is simply t he gain seen by a small volt age sour ce in ser ies wit h t he
op amp input and is also t he amplifier signal gain in t he noninver t ing mode. If
A
VOL
in t he above equat ion is infinit e, t he closed loop gain is exact ly equal t o t he
noise gain. However , for finit e values of A
VOL
, t her e is a closed loop gain er r or
given by t he equat ion:
%Gain Er r or
NG
NG A
VOL
NG
A
VOL
+
100% 100%, for NG << A
VOL
.
Not ice fr om t he equat ion t hat t he per cent gain er r or is dir ect ly pr opor t ional t o t he
noise gain, t her efor e t he effect s of finit e A
VOL
ar e less for low gain. The fir st
example in Figur e 3.6 wher e t he noise gain is 1000 shows t hat for an open loop gain
of 2 million, t her e is a gain er r or of about 0.05%. If t he open loop gain st ays const ant
over t emper at ur e and for var ious out put loads and volt ages, t he gain er r or can be
calibr at ed out of t he measur ement , and t her e is t hen no over all syst em gain er r or .
If, however , t he open loop gain changes, t he closed loop gain will also change,
t her eby int r oducing a gain uncertainty. In t he second example in t he figur e, an
A
VOL
decr ease t o 300,000 pr oduces a gain er r or of 0.33%, int r oducing a gain
3.8
uncertainty of 0.28% in t he closed loop gain. In most applicat ions, using t he pr oper
amplifier , t he r esist or s ar ound t he cir cuit will be t he lar gest sour ce of gain er r or .
CHANGES IN DC OPEN LOOP GAIN
CAUSE CLOSED LOOP GAIN UNCERTAINTY
"IDEAL" CLOSED LOOP GAIN = NOISE GAIN = NG
ACTUAL CLOSED LOOP GAIN =
NG
NG
A
VOL
1+ +
% CLOSED LOOP GAIN ERROR =
NG
NG A
VOL
+ +
100%
n Assume A
VOL
= 2,000,000, NG = 1,000
%GAIN ERROR 0.05%
n Assume A
VOL
Drops to 300,000
%GAIN ERROR 0.33%
n CLOSED LOOP GAIN UNCERTAINTY
= 0.33% 0.05% = 0.28%
n n
n n
n n
NG
A
VOL
100%
Figure 3.6
Changes in t he out put volt age level and t he out put loading ar e t he most common
causes of changes in t he open loop gain of op amps. A change in open loop gain wit h
signal level pr oduces nonlinearity in t he closed loop gain t r ansfer funct ion which
cannot be r emoved dur ing syst em calibr at ion. Most op amps have fixed loads, so
A
VOL
changes wit h load ar e not gener ally impor t ant . However , t he sensit ivit y of
A
VOL
t o out put signal level may incr ease for higher load cur r ent s.
The sever it y of t he nonlinear it y var ies widely fr om device t ype t o device t ype, and is
gener ally not specified on t he dat a sheet . The minimum A
VOL
is always specified,
and choosing an op amp wit h a high A
VOL
will minimize t he pr obabilit y of gain
nonlinear it y er r or s. Gain nonlinear it y can come fr om many sour ces, depending on
t he design of t he op amp. One common sour ce is t her mal feedback. If t emper at ur e
shift is t he sole cause of t he nonlinear it y er r or , it can be assumed t hat minimizing
t he out put loading will help. To ver ify t his, t he nonlinear it y is measur ed wit h no
load and t hen compar ed t o t he loaded condit ion.
An oscilloscope X-Y display t est cir cuit for measur ing DC open loop gain nonlinear it y
is shown in Figur e 3.7. The same pr ecaut ions pr eviously discussed r elat ing t o t he
offset volt age t est cir cuit must be obser ved in t his cir cuit . The amplifier is configur ed
for a signal gain of 1. The open loop gain is defined as t he change in out put volt age
divided by t he change in t he input offset volt age. However , for lar ge values of
A
VOL
, t he offset may change only a few micr ovolt s over t he ent ir e out put volt age
swing. Ther efor e t he divider consist ing of t he 10 r esist or and R
G
(1M ) for ces t he
volt age V
Y
t o be :
3.9
V
Y
R
G
V
OS
V
OS
+
]
]
]
1
10
100 001
, .
The value of R
G
is chosen t o give measur able volt ages at V
Y
depending on t he
expect ed values of V
OS
.
CIRCUIT MEASURES
OPEN LOOP GAIN NONLINEARITY
10V
RAMP
+V
REF
V
REF
(+10V) (10V)
10k
10k
10k 10k
10
10
1M
OFFSET ADJUST
(Multi-Turn Film-Type)
R
L
R
G
V
Y
V
X
+
V
X
V
Y
= 100001V
OS
A
VOL
=
V
X
V
OS
IDEAL
NONLINEAR
V
OS
+15V
15V
CLOSED LOOP GAIN
NONLINEARITY
NG
OPEN LOOP GAIN
NONLINEARITY
NG
1
A
VOL,MAX
1
A
VOL,MIN
Figure 3.7
The t10V r amp gener at or out put is mult iplied by t he signal gain, 1, and for ces t he
op amp out put volt age V
X
t o swing fr om +10V t o 10V. Because of t he gain fact or
applied t o t he offset volt age, t he offset adjust pot ent iomet er is added t o allow t he
init ial out put offset t o be set t o zer o. The r esist or values chosen will null an input
offset volt age of up t o t10mV. St able 10V volt age r efer ences (AD688) should be used
at each end of t he pot ent iomet er t o pr event out put dr ift . Also, the frequency of the
ramp generator must be quite low, probably no more than a fraction of 1Hz because of
the low corner frequency of the open loop gain (0.1Hz for the OP177).
The plot on t he r ight -hand side of Figur e 3.7 shows V
Y
plot t ed against V
X
. If t her e
is no gain nonlinear it y t he gr aph will have a const ant slope, and A
VOL
is calculat ed
as follows:
A
VOL
V
X
V
OS
R
G
V
X
V
Y
V
X
V
Y
+
]
]
]
]
]
]

]
]
]
1
10
100 001 , .
If t her e is nonlinear it y, A
VOL
will var y as t he out put signal changes. The
appr oximat e open loop gain nonlinear it y is calculat ed based on t he maximum and
minimum values of A
VOL
over t he out put volt age r ange:
3.10
Open Loop Gain Nonlinear it y
A
VOL MIN
A
VOL MAX

1 1
, ,
.
The closed loop gain nonlinear it y is obt ained by mult iplying t he open loop gain
nonlinear it y by t he noise gain, NG:
Closed Loop Gain Nonlinear it y NG
A
VOL MIN
A
VOL MAX

]
]
]
]
1 1
, ,
.
In t he ideal case, t he plot of V
OS
ver sus V
X
would have a const ant slope, and t he
r ecipr ocal of t he slope is t he open loop gain, A
VOL
. A hor izont al line wit h zer o slope
would indicat e infinit e open loop gain. In an act ual op amp, t he slope may change
acr oss t he out put r ange because of nonlinear it y, t her mal feedback, et c. In fact , t he
slope can even change sign.
Figur e 3.8 shows t he V
Y
(and V
OS
) ver sus V
X
plot for t he OP177 pr ecision op amp.
The plot is shown for t wo differ ent loads, 2k and 10k. The r ecipr ocal of t he slope
is calculat ed based on t he end point s, and t he aver age A
VOL
is about 8 million. The
maximum and minimum values of A
VOL
acr oss t he out put volt age r ange ar e
measur ed t o be appr oximat ely 9.1 million, and 5.7 million, r espect ively. This
cor r esponds t o an open loop gain nonlinear it y of about 0.07ppm. Thus, for a noise
gain of 100, t he cor r esponding closed loop gain nonlinear it y is about 7ppm.
OP177 GAIN NONLINEARITY
V
Y
50mV / DIV.
(0.5V / DIV.)
(RTI)
V
X
= OUTPUT VOLTAGE
0 +10V 10V
R
L
= 10k
R
L
= 2k
A
VOL
(AVERAGE) 8 million
A
VOL,MAX
9.1 million, A
VOL,MIN
5.7million
OPEN LOOP GAIN NONLINEARITY 0.07ppm
CLOSED LOOP GAIN NONLINEARITY NG0.07ppm
A
VOL
=
V
X
V
OS
V
OS
Figure 3.8
Op Amp Noi se
The t hr ee noise sour ces in an op amp cir cuit ar e t he volt age noise of t he op amp, t he
cur r ent noise of t he op amp (t her e ar e t wo uncor r elat ed sour ces, one in each input ),
3.11
and t he J ohnson noise of t he r esist ances in t he cir cuit . Op amp noise has t wo
component s - "whit e" noise at medium fr equencies and low fr equency "1/f" noise,
whose spect r al densit y is inver sely pr opor t ional t o t he squar e r oot of t he fr equency.
It should be not ed t hat , t hough bot h t he volt age and t he cur r ent noise may have t he
same char act er ist ic behavior , in a par t icular amplifier t he 1/f cor ner fr equency is not
necessar ily t he same for volt age and cur r ent noise (it is usually specified for t he
volt age noise as shown in Figur e 3.9.
INPUT VOLTAGE NOISE FOR OP177/AD707
v
nw
5
10
15
20
25
30
0.1 1 10 100
FREQUENCY (Hz)
INPUT VOLTAGE NOISE, nV / Hz 0.1Hz to 10Hz VOLTAGE NOISE
V
n rms
F
H
F
L
v
nw
F
C
F
H
F
L
F
H
F
L ,
( , ) ln ( ) = =

+ +
For F
L
= 0.1Hz, F
H
= 10Hz, v
nw
= 10nV/ Hz, F
C
= 0.7Hz:
V
n,rms
= 36nV
V
n,pp
= 6.6 36nV = 238nV
n n
n n
u u
u u
TIME - 1sec/DIV.
200nV
1/F CORNER
F
C
= 0.7Hz
(WHITE)
Figure 3.9
The low fr equency noise is gener ally known as 1/f noise (t he noise power obeys a 1/f
law - t he noise volt age or noise cur r ent is pr opor t ional t o 1/f). The fr equency at
which t he 1/f noise spect r al densit y equals t he whit e noise is known as t he 1/ f
corner frequency, F
C
, and is a figur e of mer it for an op amp, wit h low cor ner
fr equencies indicat ing bet t er per for mance. Values of 1/f cor ner fr equency var y fr om
less t han 1Hz high accur acy bipolar op amps like t he OP177/AD707, sever al
hundr ed Hz for t he AD743/745 FET-input op amps, t o sever al t housands of Hz for
some high speed op amps wher e pr ocess compr omises favor high speed r at her t han
low fr equency noise.
For t he OP177/AD707 shown in Figur e 3.9, t he 1/f cor ner fr equency is 0.7Hz, and
t he whit e noise is 10nV/Hz. The low fr equency 1/f noise is oft en expr essed as t he
peak-t o-peak noise in t he bandwidt h 0.1Hz t o 10Hz as shown in t he scope phot o in
Figur e 3.9. Not e t hat t his noise ult imat ely limit s t he r esolut ion of a pr ecision
measur ement syst em because t he bandwidt h up t o 10Hz is usually t he bandwidt h of
most int er est . The equat ion for t he t ot al r ms noise, V
n,r ms
, in t he bandwidt h F
L
t o
F
H
is given by t he equat ion:
3.12
V
n r ms
F
H
F
L
v
nw
F
C
F
H
F
L
F
H
F
L ,
( , ) ln ( )

]
]
]
+ ,
wher e v
nw
is t he noise spect r al densit y in t he "whit e noise" r egion (usually specified
at a fr equency of 1kHz), F
C
is t he 1/f cor ner fr equency, and F
L
and F
H
is t he
measur ement bandwidt h of int er est . In t he example shown, t he 0.1Hz t o 10Hz noise
is calculat ed t o be 36nV r ms, or appr oximat ely 238nV peak-t o-peak, which closely
agr ees wit h t he scope phot o on t he r ight (a fact or of 6.6 is gener ally used t o conver t
r ms values t o peak-t o-peak values).
It should be not ed t hat at higher fr equencies, t he t er m in t he equat ion cont aining
t he nat ur al logar it hm becomes insignificant , and t he expr ession for t he r ms noise
becomes:
V
n r ms
F
H
F
L
v
nw
F
H
F
L ,
( , ) .
And, if F
H
>> F
L
,
V
n r ms
F
H
v
nw
F
H ,
( ) .
However , some op amps (such as t he OP07 and OP27) have volt age noise
char act er ist ics t hat incr ease slight ly at high fr equencies. The volt age noise ver sus
fr equency cur ve for op amps should t her efor e be examined car efully for flat ness
when calculat ing high fr equency noise using t his appr oximat ion.
At ver y low fr equencies when oper at ing exclusively in t he 1/f r egion,
F
C
>> (F
H
F
L
), and t he expr ession for t he r ms noise r educes t o:
V
n r ms
F
H
F
L
v
nw
F
C
F
H
F
L
,
( , ) ln

]
]
]
.
Not e t hat t her e is no way of r educing t his 1/f noise by filt er ing if oper at ion ext ends
t o DC. Making F
H
=0.1Hz and F
L
= 0.001 st ill yields an r ms 1/f noise of about 18nV
r ms, or 119nV peak-t o-peak.
The point is t hat aver aging t he r esult s of a lar ge number of measur ement s t aken
over a long per iod of t ime has pr act ically no effect on t he er r or pr oduced by 1/f noise.
The only met hod of r educing it fur t her is t o use a chopper st abilized op amp which
does not pass t he low fr equency noise component s.
A gener alized noise model for an op amp is shown in Figur e 3.10. All uncor r elat ed
noise sour ces add as a r oot -sum-of-squar es manner , i.e., noise volt ages V1, V2, and
V3 give a r esult of:
V V V 1
2
2
2
3
2
+ + .
3.13
Thus, any noise volt age which is mor e t han 4 or 5 t imes any of t he ot her s is
dominant , and t he ot her s may gener ally be ignor ed. This simplifies noise analysis.
In t his diagr am, t he t ot al noise of all sour ces is shown r efer r ed t o t he input (RTI).
The RTI noise is useful because it can be compar ed dir ect ly t o t he input signal level.
The t ot al noise r efer r ed t o t he out put (RTO) is obt ained by simply mult iplying t he
RTI noise by t he noise gain.
The diagr am assumes t hat t he feedback net wor k is pur ely r esist ive. If it cont ains
r eact ive element s (usually capacit or s), t he noise gain is not const ant over t he
bandwidt h of int er est , and mor e complex t echniques must be used t o calculat e t he
t ot al noise (see in par t icular , Refer ence 12). However , for pr ecision applicat ions
wher e t he feedback net wor k is most likely t o be r esist ive, t he equat ions ar e valid.
Not ice t hat t he J ohnson noise volt age associat ed wit h t he t hr ee r esist or s has been
included. All r esist or s have a J ohnson noise of 4kTBR , wher e k is Bolt zmann's
Const ant (1.3810
23
J /K), T is t he absolut e t emper at ur e, B is t he bandwidt h in
Hz, and R is t he r esist ance in . A simple r elat ionship which is easy t o r emember is
t hat a 1000 resistor generates a J ohnson noise of 4nV/ Hz at 25C.
OP AMP NOISE MODEL
CLOSED
LOOP BW
= f
CL
+
V
N
R2
R1
R3
I
N
I
N+
V
OUT
NOISE GAIN =
1 +
R2
R1
NG =
V
N,R1
V
N,R3
V
N,R2
RTI NOISE =
V
N
2
+ 4kTR3 + 4kTR1
R2
R1+R2
2
+ I
N+
2
R3
2
+ I
N
2

R1R2
R1+R2
2
+ 4kTR2
R1
R1+R2
2 BW
RTO NOISE = NG RTI NOISE
4kTR1
4kTR3
4kTR2
n n
n n
A
B
GAIN FROM
"A" TO OUTPUT
GAIN FROM
"B" TO OUTPUT
=
R2
R1
=
n n BW = 1.57 f
CL
Figure 3.10
3.14
The volt age noise of var ious op amps may var y fr om under 1nV/Hz t o 20nV/Hz, or
even mor e. Bipolar input op amps t end t o have lower volt age noise t han J FET input
ones, alt hough it is possible t o make J FET input op amps wit h low volt age noise
(such as t he AD743/AD745), at t he cost of lar ge input devices and hence lar ge
(~20pF) input capacit ance. Cur r ent noise can var y much mor e widely, fr om ar ound
0.1fA/Hz (in J FET input elect r omet er op amps) t o sever al pA/Hz (in high speed
bipolar op amps). For bipolar or J FET input devices wher e all t he bias cur r ent flows
int o t he input junct ion, t he cur r ent noise is simply t he Schot t ky (or shot ) noise of t he
bias cur r ent . The shot noise spect r al densit y is simply 2I
B
q amps/Hz, wher e I
B
is t he bias cur r ent (in amps) and q is t he char ge on an elect r on (1.610
19
C). It
cannot be calculat ed for bias-compensat ed or cur r ent feedback op amps wher e t he
ext er nal bias cur r ent is t he differ ence bet ween t wo int er nal cur r ent sour ces.
Cur r ent noise is only impor t ant when it flows t hr ough an impedance and in t ur n
gener at es a noise volt age. The equat ion shown in Figur e 3.10 shows how t he cur r ent
noise flowing in t he r esist or s cont r ibut e t o t he t ot al noise. The choice of a low noise
op amp t her efor e depends on t he impedances ar ound it . Consider an OP27, a bias
compensat ed op amp wit h low volt age noise (3nV/Hz), but quit e high cur r ent noise
(1pA/Hz) as shown in t he schemat ic of Figur e 3.11. Wit h zer o sour ce impedance,
t he volt age noise dominat es. Wit h a sour ce r esist ance of 3k, t he cur r ent noise
(1pA/Hz) flowing in 3k will equal t he volt age noise, but t he J ohnson noise of t he
3k r esist or is 7nV/Hz and so is dominant . Wit h a sour ce r esist ance of 300k, t he
effect of t he cur r ent noise incr eases a hundr edfold t o 300nV/Hz, while t he volt age
noise is unchanged, and t he J ohnson noise (which is pr opor t ional t o t he square root
of t he r esist ance) incr eases t enfold. Her e, t he cur r ent noise dominat es.
DIFFERENT NOISE SOURCES DOMINATE
AT DIFFERENT SOURCE IMPEDANCES
CONTRIBUTION
FROM
AMPLIFIER
VOLTAGE NOISE
AMPLIFIER
CURRENT NOISE
FLOWING IN R
JOHNSON
NOISE OF R
VALUES OF R
0 3k 300k
3 3 3
0
0
3
7
300
70
RTI NOISE (nV / Hz)
Dominant Noise Source is Highlighted
R
+
EXAMPLE: OP27
Voltage Noise = 3nV / Hz
Current Noise = 1pA / Hz
T = 25C
OP27
R2
R1
Neglect R1 and R2
Noise Contribution
Figure 3.11
3.15
The above example shows t hat t he choice of a low noise op amp depends on t he
sour ce impedance of t he input signal, and at high impedances, cur r ent noise always
dominat es. This is shown in Figur e 3.12 for sever al bipolar (OP07, OP27, 741) and
J FET (AD645, AD743, AD744) op amps.
For low impedance cir cuit r y (gener ally < 1k), amplifier s wit h low volt age noise,
such as t he OP27 will be t he obvious choice, and t heir compar at ively lar ge cur r ent
noise will not affect t he applicat ion. At medium r esist ances, t he J ohnson noise of
r esist or s is dominant , while at ver y high r esist ances, we must choose an op amp
wit h t he smallest possible cur r ent noise, such as t he AD549 or AD645.
Unt il r ecent ly, BiFET amplifier s (wit h J FET input s) t ended t o have compar at ively
high volt age noise (t hough ver y low cur r ent noise), and t hus wer e mor e suit able for
low noise applicat ions in high r at her t han low impedance cir cuit r y. The AD645,
AD743, and AD745 have ver y low values of bot h volt age and cur r ent noise. The
AD645 specificat ions at 10kHz ar e 10nV/Hz and 0.6fA/Hz, and t he AD743/AD745
specificat ions at 10kHz ar e 2.0nV/Hz and 6.9fA/Hz. These make possible t he
design of low noise amplifier cir cuit s which have low noise over a wide r ange of
sour ce impedances.
DIFFERENT AMPLIFIERS ARE BEST
AT DIFFERENT SOURCE IMPEDANCE LEVELS
1
10
100
10 100 1k 10k
743
OP27
645
744
OP07
741
1
10
100
10 100 1k 10k
744
OP07, 743
741
OP27, 645
100
1k
10k
10 100 1k 10k
744
743
645
OP07
OP27
741
R
S
= 100 R
S
= 10k
R
S
= 1M
All Vertical Scales
nV / Hz
All Horizontal Scales
Hz
Figure 3.12
3.16
Common Mod e Reject i on a n d P ower Su p p ly Reject i on
If a signal is applied equally t o bot h input s of an op amp so t hat t he differ ent ial
input volt age is unaffect ed, t he out put should not be affect ed. In pr act ice, changes in
common mode volt age will pr oduce changes in t he out put . The common mode
rejection ratio or CMRR is t he r at io of t he common mode gain t o t he differ ent ial-
mode gain of an op amp. For example, if a differ ent ial input change of Y volt s will
pr oduce a change of 1V at t he out put , and a common mode change of X volt s
pr oduces a similar change of 1V, t hen t he CMRR is X/Y. It is nor mally expr essed in
dB, and t ypical LF values ar e bet ween 70 and 120dB. When expr essed in dB, it is
gener ally r efer r ed t o as common mode rejection (CMR). At higher fr equencies, CMR
det er ior at es - many op amp dat a sheet s show a plot of CMR ver sus fr equency as
shown in Figur e 3.13 for t he OP177/AD707 pr ecision op amps.
CMRR pr oduces a cor r esponding out put offset volt age er r or in op amps configur ed in
t he non-inver t ing mode as shown in Figur e 3.14. Op amps configur ed in t he
inver t ing mode have no CMRR out put er r or because bot h input s ar e at gr ound or
vir t ual gr ound, so t her e is no common mode volt age, only t he offset volt age of t he
amplifier if un-nulled.
OP177/AD707 COMMON MODE REJECTION (CMR)
160
140
120
100
80
60
40
20
0
CMR
dB
FREQUENCY - Hz
CMR =
20 log
10
CMRR
0.01 0.1 1 10 100 1k 10k 100k 1M
Figure 3.13
3.17
CALCULATING OFFSET ERROR
DUE TO COMMON MODE REJECTION RATIO (CMRR)
R2
R1
V
IN
= V
CM
+
V
OUT
V
OUT
= 1 +
R2
R1
ERROR (RTI) =
V
CM
CMRR
=
V
IN
CMRR
V
IN
+
V
IN
CMRR
ERROR (RTO) = 1 +
R2
R1
V
IN
CMRR
Figure 3.14
If t he supply of an op amp changes, it s out put should not , but it will. The
specificat ion of power supply rejection ratio or PSRR is defined similar ly t o t he
definit ion of CMRR. If a change of X volt s in t he supply pr oduces t he same out put
change as a differ ent ial input change of Y volt s, t hen t he PSRR on t hat supply is
X/Y. When t he r at io is expr essed in dB, it is gener ally r efer r ed t o as power supply
rejection, or PSR. The definit ion of PSRR assumes t hat bot h supplies ar e alt er ed
equally in opposit e dir ect ions - ot her wise t he change will int r oduce a common mode
change as well as a supply change, and t he analysis becomes consider ably mor e
complex. It is t his effect which causes appar ent differ ences in PSRR bet ween t he
posit ive and negat ive supplies. In t he case of single supply op amps, PSR is
gener ally defined wit h r espect t o t he change in t he posit ive supply. Many single
supply op amps have separ at e PSR specificat ions for t he posit ive and negat ive
supplies. The PSR of t he OP177/AD707 is shown in Figur e 3.15.
The PSRR of op amps is fr equency dependent , t her efor e power supplies must be well
decoupled as shown in Figur e 3.16. At low fr equencies, sever al devices may shar e a
10 - 50F capacit or on each supply, pr ovided it is no mor e t han 10cm (PC t r ack
dist ance) fr om any of t hem. At high fr equencies, each IC must have ever y supply
decoupled by a low induct ance capacit or (0.1F or so) wit h shor t leads and PC
t r acks. These capacit or s must also pr ovide a r et ur n pat h for HF cur r ent s in t he op
amp load. Decoupling capacit or s should be connect ed t o a low impedance lar ge ar ea
gr ound plane wit h minimum lead lengt hs. Sur face mount capacit or s minimize lead
induct ance and ar e a good choice.
3.18
OP177/AD707 POWER SUPPLY REJECTION (PSR)
0.01 0.1 1 10 100 1k 10k 100k 1M
160
140
120
100
80
60
40
20
0
PSR
dB
FREQUENCY - Hz
PSR =
20 log
10
PSRR
Figure 3.15
PROPER LOW AND HIGH-FREQUENCY
DECOUPLING TECHNIQUES FOR OP AMPS
+
C1
C2
+
+
C3
C4
+V
S
V
S
H
H
H
H
LARGE AREA
GROUND PLANE
H
LEAD LENGTH
MINIMUM
C1, C2:
LOCALIZED HF
DECOUPLING,
LOW INDUCTANCE
CERAMIC, 0.1F
C3, C4:
SHARED LF
DECOUPLING,
ELECTROLYTIC,
10 TO 50F
< 10cm
< 10cm
=
=
Figure 3.16
3.19
AMP LI FI ER DC ERROR BUDGET ANALYSI S
A r oom t emper at ur e er r or budget analysis for t he OP177A op amp is shown in
Figur e 3.17. The amplifier is connect ed in t he inver t ing mode wit h a signal gain of
100. The key dat a sheet specificat ions ar e also shown in t he diagr am. We assume an
input signal of 100mV fullscale which cor r esponds t o an out put signal of 10V. The
var ious er r or sour ces ar e nor malized t o fullscale and expr essed in par t s per million
(ppm). Not e: par t s per million (ppm) er r or = fr act ional er r or 10
6
= % er r or 10
4
.
Not e t hat t he offset er r or s due t o V
OS
and I
OS
and t he gain er r or due t o finit e
A
VOL
can be r emoved wit h a syst em calibr at ion. However , t he er r or due t o open
loop gain nonlinear it y cannot be r emoved wit h calibr at ion and pr oduces a r elat ive
accur acy er r or , oft en called resolution error. The second cont r ibut or t o r esolut ion
er r or is t he 1/f noise. This noise is always pr esent and adds t o t he uncer t aint y of t he
measur ement . The over all r elat ive accur acy of t he cir cuit at r oom t emper at ur e is
9ppm which is equivalent t o appr oximat ely 17 bit s of r esolut ion.
PRECISION OP AMP (OP177A) DC ERROR BUDGET
OP177A
+
V
IN
V
OUT
100
10k
99
2k
R
L
SPECS @ +25C:
V
OS
= 10V max
I
OS
= 1nA max
A
VOL
= 510
6
min
A
VOL
Nonlinearity = 0.07ppm
0.1Hz to 10Hz Noise = 200nV
V
OS
I
OS
A
VOL
A
VOL

Nonlinearity
0.1Hz to 10Hz
1/f Noise
Total
Unadjusted
Error
Resolution
Error
10V 100mV
100 1nA 100mV
(100/ 510
6
) 100mV
100 0.07ppm
200nV 100mV
13 Bits Accurate
17 Bits Accurate
100ppm
1ppm
20ppm
7ppm
2ppm
130ppm
9ppm
MAXIMUM ERROR CONTRIBUTION, + 25C
FULLSCALE: V
IN
=100mV, V
OUT
= 10V
Figure 3.17
3.20
SI NGLE SUP P LY OP AMP S
Over t he last sever al year s, single-supply oper at ion has become an incr easingly
impor t ant r equir ement because of mar ket r equir ement s. Aut omot ive, set -t op box,
camer a/cam-cor der , PC, and lapt op comput er applicat ions ar e demanding IC
vendor s t o supply an ar r ay of linear devices t hat oper at e on a single supply r ail,
wit h t he same per for mance of dual supply par t s. Power consumpt ion is now a key
par amet er for line or bat t er y oper at ed syst ems, and in some inst ances, mor e
impor t ant t han cost . This makes low-volt age/low supply cur r ent oper at ion cr it ical; at
t he same t ime, however , accur acy and pr ecision r equir ement s have for ced IC
manufact ur er s t o meet t he challenge of doing mor e wit h less in t heir amplifier
designs.
SINGLE SUPPLY AMPLIFIERS
n Single Supply Offers:
u Lower Power
u Battery Operated Portable Equipment
u Requires Only One Voltage
n Design Tradeoffs:
u Reduced Signal Swing Increases Sensitivity to Errors
Caused by Offset Voltage, Bias Current, Finite Open-
Loop Gain, Noise, etc.
u Must Usually Share Noisy Digital Supply
u Rail-to-Rail Input and Output Needed to Increase Signal
Swing
u Precision Less than the best Dual Supply Op Amps
but not Required for All Applications
u Many Op Amps Specified for Single Supply, but do not
have Rail-to-Rail Inputs or Outputs
Figure 3.18
In a single-supply applicat ion, t he most immediat e effect on t he per for mance of an
amplifier is t he r educed input and out put signal r ange. As a r esult of t hese lower
input and out put signal excur sions, amplifier cir cuit s become mor e sensit ive t o
int er nal and ext er nal er r or sour ces. Pr ecision amplifier offset volt ages on t he or der
of 0.1mV ar e less t han a 0.04 LSB er r or sour ce in a 12-bit , 10V full-scale syst em. In
a single-supply syst em, however , a "r ail-t o-r ail" pr ecision amplifier wit h an offset
volt age of 1mV r epr esent s a 0.8LSB er r or in a 5V fullscale syst em, and 1.6LSB
er r or in a 2.5V fullscale syst em.
3.21
To keep bat t er y cur r ent dr ain low, lar ger r esist or s ar e usually used ar ound t he op
amp. Since t he bias cur r ent flows t hr ough t hese lar ger r esist or s, t hey can gener at e
offset er r or s equal t o or gr eat er t han t he amplifier s own offset volt age.
Gain accur acy in some low volt age single-supply devices is also r educed, so device
select ion needs car eful consider at ion. Many amplifier s having open-loop gains in t he
millions t ypically oper at e on dual supplies: for example, t he OP07 family t ypes.
However , many single-supply/r ail-t o-r ail amplifier s for pr ecision applicat ions
t ypically have open-loop gains bet ween 25,000 and 30,000 under light loading
(>10k). Select ed devices, like t he OP113/213/413 family, do have high open-loop
gains (i.e., > 1M).
Many t r ade-offs ar e possible in t he design of a single-supply amplifier cir cuit : speed
ver sus power , noise ver sus power , pr ecision ver sus speed and power , et c. Even if t he
noise floor r emains const ant (highly unlikely), t he signal-t o-noise r at io will dr op as
t he signal amplit ude decr eases.
Besides t hese limit at ions, many ot her design consider at ions t hat ar e ot her wise
minor issues in dual-supply amplifier s now become impor t ant . For example, signal-
t o-noise (SNR) per for mance degr ades as a r esult of r educed signal swing. "Gr ound
r efer ence" is no longer a simple choice, as one r efer ence volt age may wor k for some
devices, but not ot her s. Amplifier volt age noise incr eases as oper at ing supply
cur r ent dr ops, and bandwidt h decr eases. Achieving adequat e bandwidt h and
r equir ed pr ecision wit h a somewhat limit ed select ion of amplifier s pr esent s
significant syst em design challenges in single-supply, low-power applicat ions.
Most cir cuit designer s t ake "gr ound" r efer ence for gr ant ed. Many analog cir cuit s
scale t heir input and out put r anges about a gr ound r efer ence. In dual-supply
applicat ions, a r efer ence t hat split s t he supplies (0V) is ver y convenient , as t her e is
equal supply headr oom in each dir ect ion, and 0V is gener ally t he volt age on t he low
impedance gr ound plane.
In single-supply/r ail-t o-r ail cir cuit s, however , t he gr ound r efer ence can be chosen
anywher e wit hin t he supply r ange of t he cir cuit , since t her e is no st andar d t o follow.
The choice of gr ound r efer ence depends on t he t ype of signals pr ocessed and t he
amplifier char act er ist ics. For example, choosing t he negat ive r ail as t he gr ound
r efer ence may opt imize t he dynamic r ange of an op amp whose out put is designed t o
swing t o 0V. On t he ot her hand, t he signal may r equir e level shift ing in or der t o be
compat ible wit h t he input of ot her devices (such as ADCs) t hat ar e not designed t o
oper at e at 0V input .
Ear ly single-supply zer o-in, zer o-out amplifier s wer e designed on bipolar pr ocesses
which opt imized t he per for mance of t he NPN t r ansist or s. The PNP t r ansist or s wer e
eit her lat er al or subst r at e PNPs wit h much less bandwidt h t han t he NPNs. Fully
complement ar y pr ocesses ar e now r equir ed for t he new-br eed of single-supply/r ail-
t o-r ail oper at ional amplifier s. These new amplifier designs do not use lat er al or
subst r at e PNP t r ansist or s wit hin t he signal pat h, but incor por at e par allel NPN and
PNP input st ages t o accommodat e input signal swings fr om gr ound t o t he posit ive
supply r ail. Fur t her mor e, r ail-t o-r ail out put st ages ar e designed wit h bipolar NPN
and PNP common-emit t er , or N-channel/P-channel common-sour ce amplifier s whose
3.22
collect or -emit t er sat ur at ion volt age or dr ain-sour ce channel on-r esist ance det er mine
out put signal swing as a funct ion of t he load cur r ent .
The char act er ist ics of a single-supply amplifier input st age (common mode r eject ion,
input offset volt age and it s t emper at ur e coefficient , and noise) ar e cr it ical in
pr ecision, low-volt age applicat ions. Rail-t o-r ail input oper at ional amplifier s must
r esolve small signals, whet her t heir input s ar e at gr ound, or in some cases near t he
amplifier s posit ive supply. Amplifier s having a minimum of 60dB common mode
r eject ion over t he ent ir e input common mode volt age r ange fr om 0V t o t he posit ive
supply ar e good candidat es. It is not necessar y t hat amplifier s maint ain common
mode r eject ion for signals beyond t he supply volt ages: what is required is that they
do not self-destruct for momentary overvoltage conditions. Fur t her mor e, amplifier s
t hat have offset volt ages less t han 1mV and offset volt age dr ift s less t han 2V/C
ar e also ver y good candidat es for pr ecision applicat ions. Since input signal dynamic
r ange and SNR ar e equally if not mor e impor t ant t han output dynamic r ange and
SNR, pr ecision single-supply/r ail-t o-r ail oper at ional amplifier s should have noise
levels r efer r ed-t o-input (RTI) less t han 5Vp-p in t he 0.1Hz t o 10Hz band.
The need for r ail-t o-r ail amplifier out put st ages is dr iven by t he need t o maint ain
wide dynamic r ange in low-supply volt age applicat ions. A single-supply/r ail-t o-r ail
amplifier should have out put volt age swings which ar e wit hin at least 100mV of
eit her supply r ail (under a nominal load). The out put volt age swing is ver y
dependent on out put st age t opology and load cur r ent . The volt age swing of a good
out put st age should maint ain it s r at ed swing for loads down t o 10k. The smaller
t he V
OL
and t he lar ger t he V
OH
, t he bet t er . Syst em par amet er s, such as zer o-
scale or full-scale out put volt age, should be det er mined by an amplifier s V
OL
(for
zer o-scale) and V
OH
(for full-scale).
Since t he major it y of single-supply dat a acquisit ion syst ems r equir e at least 12- t o
14-bit per for mance, amplifier s which exhibit an open-loop gain gr eat er t han 30,000
for all loading condit ions ar e good choices in pr ecision applicat ions.
Si n gle Su p p ly Op Amp I n p u t St a ges
Ther e is some demand for op amps whose input common mode volt age includes both
supply r ails. Such a feat ur e is undoubt edly useful in some applicat ions, but
engineer s should r ecognize t hat t her e ar e r elat ively few applicat ions wher e it is
absolut ely essent ial. These should be car efully dist inguished fr om t he many
applicat ions wher e common mode r ange close t o t he supplies or one t hat includes one
of t he supplies is necessar y, but input r ail-t o-r ail oper at ion is not .
In many single-supply applicat ions, it is r equir ed t hat t he input go t o only one of t he
supply r ails (usually gr ound). High-side or low-side sensing applicat ions ar e good
examples of t his. Amplifier s which will handle zer o-volt input s ar e r elat ively easily
designed using PNP differ ent ial pair s (or N-channel J FET pair s) as shown in Figur e
3.19. The input common mode r ange of such an op amp ext ends fr om about 200mV
below t he negat ive supply t o wit hin about 1V of t he posit ive supply.
3.23
PNP OR N-CHANNEL JFET STAGES
ALLOW INPUT SIGNAL TO GO TO THE NEGATIVE RAIL
PNPs
+V
S
V
S
N-CH
JFETs
+V
S
V
S
Figure 3.19
The input st age could also be designed wit h NPN t r ansist or s (or P-channel J FETs),
in which case t he input common mode r ange would include t he posit ive r ail and t o
wit hin about 1V of t he negat ive r ail. This r equir ement t ypically occur s in
applicat ions such as high-side cur r ent sensing, a low-fr equency measur ement
applicat ion. The OP282/OP482 input st age uses t he P-channel J FET input pair
whose input common mode r ange includes t he posit ive r ail. Ot her cir cuit t opologies
for high-side sensing (such as t he AD626) use t he pr ecision r esist or s t o at t enuat e t he
common mode volt age.
Tr ue r ail-t o-r ail input st ages r equir e t wo long-t ailed pair s (see Figur e 3.20), one of
NPN bipolar t r ansist or s (or N-channel J FETs), t he ot her of PNP t r ansist or s (or
P-channel J FETs). These t wo pair s exhibit different offset s and bias cur r ent s, so
when t he applied input common mode volt age changes, t he amplifier input offset
volt age and input bias cur r ent does also. In fact , when bot h cur r ent sour ces r emain
act ive t hr oughout t he ent ir e input common mode r ange, amplifier input offset
volt age is t he average offset volt age of t he NPN pair and t he PNP pair . In t hose
designs wher e t he cur r ent sour ces ar e alt er nat ively swit ched off at some point along
t he input common mode volt age, amplifier input offset volt age is dominat ed by t he
PNP pair offset volt age for signals near t he negat ive supply, and by t he NPN pair
offset volt age for signals near t he posit ive supply. It should be not ed t hat t r ue r ail-
t o-r ail input st ages can also be const r uct ed fr om CMOS t r ansist or s as in t he case of
t he OP250/450 and t he AD8531/8532/8534.
3.24
TRUE RAIL-TO-RAIL INPUT STAGE
+V
S
V
S
Q1
Q2
Q3 Q4
Figure 3.20
Amplifier input bias cur r ent , a funct ion of t r ansist or cur r ent gain, is also a funct ion
of t he applied input common mode volt age. The r esult is r elat ively poor common
mode r eject ion (CMR), and a changing common mode input impedance over t he
common mode input volt age r ange, compar ed t o familiar dual-supply devices. These
specificat ions should be consider ed car efully when choosing a r ail-r ail input op amp,
especially for a non-inver t ing configur at ion. Input offset volt age, input bias cur r ent ,
and even CMR may be quit e good over part of t he common mode r ange, but much
wor se in t he r egion wher e oper at ion shift s bet ween t he NPN and PNP devices and
vice ver sa.
Tr ue r ail-t o-r ail amplifier input st age designs must t r ansit ion fr om one differ ent ial
pair t o t he ot her differ ent ial pair somewher e along t he input common mode volt age
r ange. Some devices like t he OP191/291/491 family and t he OP279 have a common
mode cr ossover t hr eshold at appr oximat ely 1V below t he posit ive supply. The PNP
differ ent ial input st age is act ive fr om about 200mV below t he negat ive supply t o
wit hin about 1V of t he posit ive supply. Over t his common mode r ange, amplifier
input offset volt age, input bias cur r ent , CMR, input noise volt age/cur r ent ar e
pr imar ily det er mined by t he char act er ist ics of t he PNP differ ent ial pair . At t he
cr ossover t hr eshold, however , amplifier input offset volt age becomes t he aver age
offset volt age of t he NPN/PNP pair s and can change r apidly. Also, amplifier bias
cur r ent s, dominat ed by t he PNP differ ent ial pair over most of t he input common
mode r ange, change polar it y and magnit ude at t he cr ossover t hr eshold when t he
NPN differ ent ial pair becomes act ive.
Op amps like t he OP184/284/484, ut ilize a r ail-t o-r ail input st age design wher e bot h
NPN and PNP t r ansist or pair s ar e act ive t hr oughout t he ent ir e input common mode
volt age r ange, and t her e is no common mode cr ossover t hr eshold. Amplifier input
offset volt age is t he aver age offset volt age of t he NPN and t he PNP st ages. Amplifier
3.25
input offset volt age exhibit s a smoot h t r ansit ion t hr oughout t he ent ir e input
common mode r ange because of car eful laser t r imming of t he r esist or s in t he input
st age. In t he same manner , t hr ough car eful input st age cur r ent balancing and input
t r ansist or design, amplifier input bias cur r ent s also exhibit a smoot h t r ansit ion
t hr oughout t he ent ir e common mode input volt age r ange. The except ion occur s at
t he ext r emes of t he input common mode r ange, wher e amplifier offset volt ages and
bias cur r ent s incr ease shar ply due t o t he slight for war d-biasing of par asit ic p-n
junct ions. This occur s for input volt ages wit hin appr oximat ely 1V of eit her supply
r ail.
When both differ ent ial pair s ar e act ive t hr oughout t he ent ir e input common mode
r ange, amplifier t r ansient r esponse is fast er t hr ough t he middle of t he common
mode r ange by as much as a fact or of 2 for bipolar input st ages and by a fact or of 2
for J FET input st ages. Input st age t r ansconduct ance det er mines t he slew r at e and
t he unit y-gain cr ossover fr equency of t he amplifier , hence r esponse t ime degr ades
slight ly at t he ext r emes of t he input common mode r ange when eit her t he PNP
st age (signals appr oaching t he posit ive supply r ail) or t he NPN st age (signals
appr oaching t he negat ive supply r ail) ar e for ced int o cut off. The t hr esholds at which
t he t r ansconduct ance changes occur ar e appr oximat ely wit hin 1V of eit her supply
r ail, and t he behavior is similar t o t hat of t he input bias cur r ent s.
Applicat ions which r equir e t r ue r ail-r ail input s should t her efor e be car efully
evaluat ed, and t he amplifier chosen t o ensur e t hat it s input offset volt age, input bias
cur r ent , common mode r eject ion, and noise (volt age and cur r ent ) ar e suit able.
Si n gle Su p p ly Op Amp Ou t p u t St a ges
The ear liest IC op amp out put st ages wer e NPN emit t er follower s wit h NPN cur r ent
sour ces or r esist ive pull-downs, as shown in t he left -hand diagr am of Figur e 3.21.
Nat ur ally, t he slew r at es wer e gr eat er for posit ive-going t han for negat ive-going
signals. While all moder n op amps have push-pull out put st ages of some sor t , many
ar e st ill asymmet r ical, and have a gr eat er slew r at e in one dir ect ion t han t he ot her .
Asymmet r y t ends t o int r oduce dist or t ion on AC signals and gener ally r esult s fr om
t he use of IC pr ocesses wit h fast er NPN t han PNP t r ansist or s. It may also r esult in
t he abilit y of t he out put t o appr oach one supply mor e closely t han t he ot her .
In many applicat ions, t he out put is r equir ed t o swing only t o one r ail, usually t he
negat ive r ail (i.e., gr ound in single-supply syst ems). A pulldown r esist or t o t he
negat ive r ail will allow t he out put t o appr oach t hat r ail (pr ovided t he load
impedance is high enough, or is also gr ounded t o t hat r ail), but only slowly. Using
an FET cur r ent sour ce inst ead of a r esist or can speed t hings up, but t his adds
complexit y.
Wit h new complement ar y bipolar pr ocesses (CB), well mat ched high speed PNP and
NPN t r ansist or s ar e available. The complement ar y emit t er follower out put st age
shown in t he r ight -hand diagr am of Figur e 3.21 has many advant ages including low
out put impedance. However , t he out put can only swing wit hin about one V
BE
dr op
of eit her supply r ail. An out put swing of +1V t o +4V is t ypical of such st ages when
oper at ed on a single +5V supply.
3.26
TRADITIONAL OUTPUT STAGES
NPN
NPN
NPN
PNP
+V
S
+V
S
V
S
V
S
V
OUT
V
OUT
NMOS
NMOS
+V
S
V
S
V
OUT
Figure 3.21
The complement ar y common-emit t er /common-sour ce out put st ages shown in Figur e
3.22 allow t he out put volt age t o swing much closer t o t he out put r ails, but t hese
st ages have higher open loop out put impedance t han t he emit t er follower - based
st ages. In pr act ice, however , t he amplifier 's open loop gain and local feedback
pr oduce an appar ent low out put impedance, par t icular ly at fr equencies below 10Hz.
The complement ar y common emit t er out put st age using BJ Ts (left -hand diagr am in
Figur e 3.22) cannot swing complet ely t o t he r ails, but only t o wit hin t he t r ansist or
sat ur at ion volt age (V
CESAT
) of t he r ails. For small amount s of load cur r ent (less
t han 100A), t he sat ur at ion volt age may be as low as 5 t o 10mV, but for higher load
cur r ent s, t he sat ur at ion volt age can incr ease t o sever al hundr ed mV (for example,
500mV at 50mA).
On t he ot her hand, an out put st age const r uct ed of CMOS FETs can pr ovide near ly
t r ue r ail-t o-r ail per for mance, but only under no-load condit ions. If t he out put must
sour ce or sink cur r ent , t he out put swing is r educed by t he volt age dr opped acr oss t he
FETs int er nal "on" r esist ance (t ypically, 100 for pr ecision amplifier s, but can be
less t han 10 for high cur r ent dr ive CMOS amplifier s).
For t hese r easons, it is appar ent t hat t her e is no such t hing as a t r ue r ail-t o-r ail
out put st age, hence t he t it le of Figur e 3.22 ("Almost " Rail-t o-Rail Out put St ages).
3.27
"ALMOST" RAIL-TO-RAIL OUTPUT STRUCTURES
PNP
NPN
PMOS
NMOS
+V
S
+V
S
V
S
V
S
V
OUT
V
OUT
SWINGS LIMITED BY
SATURATION VOLTAGE
SWINGS LIMITED BY
FET "ON" RESISTANCE
Figure 3.22
Figur e 3.23 summar izes t he per for mance char act er ist ics of a number of single-
supply op amps suit able for some pr ecision applicat ions. The devices ar e list ed in
or der of incr easing supply cur r ent . Single, dual, and quad ver sions of each op amp
ar e available, so t he supply cur r ent is t he nor malized I
SY
/amplifier for compar ison.
The input and out put volt age r anges (V
S
= +5V) ar e also supplied in t he t able. The
"0, 4V" input s ar e PNP pair s, wit h t he except ion of t he AD820/822/824 which use N-
Channel J FETs. Out put st ages having volt age r anges designat ed "5mV, 4V" ar e
NPN emit t er -follower s wit h cur r ent sour ce pull-downs (OP193/293/493,
OP113/213/413). Out put st ages designat ed "R/R" use CMOS common sour ce st ages
(OP181/281/481) or CB common emit t er st ages (OP196/296/496, OP191/291/491,
AD820/822/824, OP184/284/484).
In summar y, t he following point s should be consider ed when select ing amplifier s for
single-supply/r ail-t o-r ail applicat ions:
First, input offset voltage and input bias currents are a function of the applied input
common mode voltage (for true rail-to-rail input op amps). Cir cuit s using t his class of
amplifier s should be designed t o minimize r esult ing er r or s. An inver t ing amplifier
configur at ion wit h a false gr ound r efer ence at t he non-inver t ing input pr event s
t hese er r or s by holding t he input common mode volt age const ant . If t he inver t ing
amplifier configur at ion cannot be used, t hen amplifier s like t he OP184/284/OP484
which do not exhibit any common mode cr ossover t hr esholds should be used.
3.28
PRECISION SINGLE-SUPPLY OP AMP
PERFORMANCE CHARACTERISTICS
**PART NO.
OP181/281/481
OP193/293/493
OP196/296/496
OP191/291/491
*AD820/822/824
OP184/284/484
OP113/213/413
V
OS
max
1500V
75V
300V
700V
400V
65V
125V
V
OS
TC
10V/C
0.2V/C
1.5V/C
1.1V/C
2V/C
0.2V/C
0.2V/C
A
VOL
min
5M
200k
150k
25k
500k
50k
2M
NOISE (1kHz)
70nV/ Hz
65nV/ Hz
26nV/ Hz
35nV/ Hz
16nV/ Hz
3.9nV/ Hz
4.7nV/ Hz
INPUT
0, 4V
0, 4V
R/R
R/R
0, 4V
R/R
0, 4V
OUTPUT
"R/R"
5mV, 4V
"R/R"
"R/R"
"R/R"
"R/R"
5mV, 4V
I
SY
/AMP
4A
15A
50A
400A
800A
1250A
1750A
NOTE: Unless Otherwise Stated
Specifications are Typical @ +25C
V
S
= +5V
*JFET INPUT
**LISTED IN ORDER OF INCREASING SUPPLY CURRENT
Figure 3.23
S econd, since input bias currents are not always small and can exhibit different
polarities, source impedance levels should be carefully matched to minimize
additional input bias current-induced offset voltages and increased distortion. Again,
consider using amplifier s t hat exhibit a smoot h input bias cur r ent t r ansit ion
t hr oughout t he applied input common mode volt age.
Third, rail-to-rail amplifier output stages exhibit load-dependent gain which affects
amplifier open-loop gain, and hence closed-loop gain accuracy. Amplifier s wit h open-
loop gains gr eat er t han 30,000 for r esist ive loads less t han 10k ar e good choices in
pr ecision applicat ions. For applicat ions not r equir ing full r ail-r ail swings, device
families like t he OP113/213/413 and OP193/293/493 offer DC gains of 200,000 or
mor e.
Lastly, no matter what claims are made, rail-to-rail output voltage swings are
functions of the amplifiers output stage devices and load current. The sat ur at ion
volt age (V
CESAT
), sat ur at ion r esist ance (R
SAT
) for bipolar out put st ages, and FET
on-r esist ance for CMOS out put st ages, as well as load cur r ent all affect t he amplifier
out put volt age swing.
Op Amp P r ocess Tech n ologi es
The wide var iet y of pr ocesses used t o make op amps ar e shown in Figur e 3.24. The
ear liest op amps wer e made using st andar d NPN-based bipolar pr ocesses. The PNP
t r ansist or s available on t hese pr ocesses wer e ext r emely slow and wer e used
pr imar ily for cur r ent sour ces and level shift ing.
3.29
The abilit y t o pr oduce mat ching high speed PNP t r ansist or s on a bipolar pr ocess
added gr eat flexibilit y t o op amp cir cuit designs. These complement ar y bipolar (CB)
pr ocesses ar e widely used in t oday's pr ecision op amps, as well as t hose r equir ing
wide bandwidt hs. The high-speed PNP t r ansist or s have f
t
s which ar e gr eat er t han
one-half t he f
t
s of t he NPNs.
The addit ion of J FETs t o t he complement ar y bipolar pr ocess (CBFET) allow high
input impedance op amps t o be designed suit able for such applicat ions as phot odiode
or elect r omet er pr eamplifier s.
CMOS op amps, wit h a few except ions, gener ally have r elat ively poor offset volt age,
dr ift , and volt age noise. However , t he input bias cur r ent is ver y low. They offer low
power and cost , however , and impr oved per for mance can be achieved wit h BiFET or
CBFET pr ocesses.
The addit ion of bipolar or complement ar y devices t o a CMOS pr ocess (BiMOS or
CBCMOS) adds gr eat flexibilit y, bet t er linear it y, and low power . The bipolar devices
ar e t ypically used for t he input st age t o pr ovide good gain and linear it y, and CMOS
devices for t he r ail-t o-r ail out put st age.
In summar y, t her e is no single IC pr ocess which is opt imum for all op amps. Pr ocess
select ion and t he r esult ing op amp design depends on t he t ar get ed applicat ions and
ult imat ely should be t r anspar ent t o t he cust omer .
OP AMP PROCESS TECHNOLOGY SUMMARY
n BIPOLAR (NPN-BASED): This is Where it All Started!!
n COMPLEMENTARY BIPOLAR (CB): Rail-to-Rail, Precision, High Speed
n BIPOLAR + JFET (BiFET): High Input Impedance, High Speed
n COMPLEMENTARY BIPOLAR + JFET (CBFET): High Input Impedance,
Rail-to-Rail Output, High Speed
n COMPLEMENTARY MOSFET (CMOS): Low Cost, Non-Critical Op Amps
n BIPOLAR + CMOS (BiCMOS): Bipolar Input Stage adds Linearity,
Low Power, Rail-to-Rail Output
n COMPLEMENTARY BIPOLAR + CMOS (CBCMOS): Rail-to-Rail Inputs,
Rail-to-Rail Outputs, Good Linearity, Low Power
Figure 3.24
3.30
I NSTRUMENTATI ON AMP LI FI ERS (I N-AMP S)
An inst r ument at ion amplifier is a closed-loop gain block which has a differ ent ial
input and an out put which is single-ended wit h r espect t o a r efer ence t er minal (see
Figur e 3.25). The input impedances ar e balanced and have high values, t ypically
10
9
or higher . Unlike an op amp, which has it s closed-loop gain det er mined by
ext er nal r esist or s connect ed bet ween it s inver t ing input and it s out put , an in-amp
employs an int er nal feedback r esist or net wor k which is isolat ed fr om it s signal input
t er minals. Wit h t he input signal applied acr oss t he t wo differ ent ial input s, gain is
eit her pr eset int er nally or is user -set by an int er nal (via pins) or ext er nal gain
r esist or , which is also isolat ed fr om t he signal input s. Typical in-amp gain set t ings
r ange fr om 1 t o 10,000.
INSTRUMENTATION AMPLIFIER
~
COMMON
MODE
VOLTAGE
V
CM
+
_
R
G
IN-AMP
GAIN = G
V
OUT
V
REF
COMMON MODE ERROR (RTI) =
V
CM
CMRR
~
R
S
/2
R
S
/2
R
S
~
~
V
SIG
2
V
SIG
2
+
_
+
_
Figure 3.25
In or der t o be effect ive, an in-amp needs t o be able t o amplify micr ovolt -level signals,
while simult aneously r eject ing volt s of common mode signal at it s input s. This
r equir es t hat in-amps have ver y high common mode r eject ion (CMR): t ypical values
of CMR ar e 70dB t o over 100dB, wit h CMR usually impr oving at higher gains.
It is impor t ant t o not e t hat a CMR specificat ion for DC input s alone is not sufficient
in most pr act ical applicat ions. In indust r ial applicat ions, t he most common cause of
ext er nal int er fer ence is pickup fr om t he 50/60Hz AC power mains. Har monics of t he
power mains fr equency can also be t r oublesome. In differ ent ial measur ement s, t his
t ype of int er fer ence t ends t o be induced equally ont o bot h in-amp input s. The
int er fer ing signal t her efor e appear s as a common mode signal t o t he in-amp.
Specifying CMR over fr equency is mor e impor t ant t han specifying it s DC value.
Imbalance in t he sour ce impedance can degr ade t he CMR of some in-amps. Analog
Devices fully specifies in-amp CMR at 50/60Hz wit h a sour ce impedance imbalance
of 1k.
3.31
Low-fr equency CMR of op amps, connect ed as subt r act or s as shown in Figur e 3.26,
gener ally is a funct ion of t he r esist or s ar ound t he cir cuit , not t he op amp. A
mismat ch of only 0.1% in t he r esist or r at ios will r educe t he DC CMR t o
appr oximat ely 66dB. Anot her pr oblem wit h t he simple op amp subt r act or is t hat t he
input impedances ar e r elat ively low and ar e unbalanced bet ween t he t wo sides. The
input impedance seen by V
1
is R
1
, but t he input impedance seen by V
2
is R1' + R2'.
This configur at ion can be quit e pr oblemat ic in t er ms of CMR, since even a small
sour ce impedance imbalance (~ 10 ) will degr ade t he wor kable CMR.
OP AMP SUBTRACTOR
V
OUT
= (V
2
V
1
)
R2
R1
R1 R2
_
+
V
1
V
2
V
OUT
R1' R2'
R2
R1
=
R2'
R1'
CRITICAL FOR HIGH CMR
0.1% TOTAL MISMATCH YIELDS 66dB CMR FOR R1 = R2
CMR = 20 log
10

1 +
R2
R1
Kr
Where Kr = Total Fractional
Mismatch of R1 - R2
EXTREMELY SENSITIVE TO SOURCE IMPEDANCE IMBALANCE
Figure 3.26
I n st r u men t a t i on Amp li fi er Con fi gu r a t i on s
Inst r ument at ion amplifier configur at ions ar e based on op amps, but t he simple
subt r act or cir cuit descr ibed above lacks t he per for mance r equir ed for pr ecision
applicat ions. An in-amp ar chit ect ur e which over comes some of t he weaknesses of t he
subt r act or cir cuit uses t wo op amps as shown in Figur e 3.27. This cir cuit is t ypically
r efer r ed t o as t he two op amp in-amp. Dual IC op amps ar e used in most cases for
good mat ching. The cir cuit gain may be t r immed wit h an ext er nal r esist or , R
G
. The
input impedance is high, per mit t ing t he impedance of t he signal sour ces t o be high
and unbalanced. The DC common mode r eject ion is limit ed by t he mat ching of
R1/R2 t o R1'/R2'. If t her e is a mismat ch in any of t he four r esist or s, t he DC common
mode r eject ion is limit ed t o:
CMR
GAIN
MISMATCH
]
]
]
20
100
log
%
.
3.32
TWO OP AMP INSTRUMENTATION AMPLIFIER
+
_
+
_
V
2
V
1
A1
A2
R2'
R1'
R2
R1
R
G
V
OUT
V
REF
A
C
V
2
V
1
R2
R1
=
R2'
R1'
V
OUT
= ( V
2
V
1
) 1 +
R2
R1
+
2R2
R
G
+ V
REF
CMR 20log
GAIN 100
% MISMATCH
1 +
R2
R1
+
2R2
R
G
G =
Figure 3.27
Ther e is an implicit advant age t o t his configur at ion due t o t he gain execut ed on t he
signal. This r aises t he CMR in pr opor t ion.
Int egr at ed inst r ument at ion amplifier s ar e par t icular ly well suit ed t o meet ing t he
combined needs of r at io mat ching and t emper at ur e t r acking of t he gain-set t ing
r esist or s. While t hin film r esist or s fabr icat ed on silicon have an init ial t oler ance of
up t o t20%, laser t r imming dur ing pr oduct ion allows t he r at io er r or bet ween t he
r esist or s t o be r educed t o 0.01% (100ppm). Fur t her mor e, t he t r acking bet ween t he
t emper at ur e coefficient s of t he t hin film r esist or s is inher ent ly low and is t ypically
less t han 3ppm/C (0.0003%/C).
When dual supplies ar e used, V
REF
is nor mally connect ed dir ect ly t o gr ound. In
single supply applicat ions, V
REF
is usually connect ed t o a low impedance volt age
sour ce equal t o one-half t he supply volt age. The gain fr om V
REF
t o node "A" is
R1/R2, and t he gain fr om node "A" t o t he out put is R2'/R1'. This makes t he gain
fr om V
REF
t o t he out put equal t o unit y, assuming per fect r at io mat ching. Not e t hat
it is cr it ical t hat t he sour ce impedance seen by V
REF
be low, ot her wise CMR will be
degr aded.
One major disadvant age of t his design is t hat common mode volt age input r ange
must be t r aded off against gain. The amplifier A1 must amplify t he signal at V
1
by
1
1
2
+
R
R
.
3.33
If R1 >> R2 (low gain in Figur e 3.27), A1 will sat ur at e if t he common mode signal is
t oo high, leaving no headr oom t o amplify t he want ed differ ent ial signal. For high
gains (R1<< R2), t her e is cor r espondingly mor e headr oom at node "A" allowing
lar ger common mode input volt ages.
The AC common mode r eject ion of t his configur at ion is gener ally poor because t he
signal fr om V
1
t o V
OUT
has t he addit ional phase shift of A1. In addit ion, t he t wo
amplifier s ar e oper at ing at differ ent closed-loop gains (and t hus at differ ent
bandwidt hs). The use of a small t r im capacit or "C" as shown in t he diagr am can
impr ove t he AC CMR somewhat .
A low gain (G = 2) single supply t wo op amp in-amp configur at ion r esult s when R
G
is not used, and is shown in Figur e 3.28. The input common mode and differ ent ial
signals must be limit ed t o values which pr event sat ur at ion of eit her A1 or A2. In t he
example, t he op amps r emain linear t o wit hin 0.1V of t he supply r ails, and t heir
upper and lower out put limit s ar e designat ed V
OH
and V
OL
, r espect ively. Using t he
equat ions shown in t he diagr am, t he volt age at V
1
must fall bet ween 1.3V and 2.4V
t o pr event A1 fr om sat ur at ing. Not ice t hat V
REF
is connect ed t o t he aver age of
V
OH
and V
OL
(2.5V). This allows for bipolar differ ent ial input signals wit h V
OUT
r efer enced t o +2.5V.
SINGLE SUPPLY RESTRICTIONS: V
S
= +5V, G = 2
+
_
+
_
V
2
V
1
A1
A2
R2
R1
R2
R1
V
OUT
V
REF
A
V
1,MIN

1
G
(G 1)V
OL
+ V
REF 1.3V
V
1,MAX

1
G
(G 1)V
OH
+ V
REF 3.7V
V
2
V
1

MAX

V
OH
V
OL
G
2.4V
10k
10k
10k
10k
V
OH
=4.9V
V
OL
=0.1V V
OH
=4.9V
V
OL
=0.1V
V
REF
=
V
OH
+ V
OL
2
= 2.5V
2.5V
Figure 3.28
A high gain (G = 100) single supply t wo op amp in-amp configur at ion is shown in
Figur e 3.29. Using t he same equat ions, not e t hat t he volt age at V
1
can now swing
bet ween 0.124V and 4.876V. Again, V
REF
is connect ed t o 2.5V t o allow for bipolar
differ ent ial input and out put signals.
3.34
SINGLE SUPPLY RESTRICTIONS: V
S
= +5V, G = 100
+
_
+
_
V
2
V
1
A1
A2
R2
R1
R2
R1
V
OUT
A
10k
990k
10k
990k
V
OH
=4.9V
V
OL
=0.1V V
OH
=4.9V
V
OL
=0.1V
V
REF
=
V
OH
+ V
OL
2
= 2.5V
V
REF
2.5V
V
1,MIN

1
G
(G 1)V
OL
+ V
REF 0.124V
V
1,MAX

1
G
(G 1)V
OH
+ V
REF 4.876V
V
2
V
1

MAX

V
OH
V
OL
G
0.048V
Figure 3.29
The above discussion shows t hat r egar dless of gain, t he basic t wo op amp in-amp
does not allow for zer o-volt common mode input volt ages when oper at ed on a single
supply. This limit at ion can be over come using t he cir cuit shown in Figur e 3.30
which is implement ed in t he AD627 in-amp. Each op amp is composed of a PNP
common emit t er input st age and a gain st age, designat ed Q1/A1 and Q2/A2,
r espect ively. The PNP t r ansist or s not only pr ovide gain but also level shift t he input
signal posit ive by about 0.5V, t her eby allowing t he common mode input volt age t o
go t o 0.1V below t he negat ive supply r ail. The maximum posit ive input volt age
allowed is 1V less t han t he posit ive supply r ail.
The AD627 in-amp deliver s r ail-t o-r ail out put swing and oper at es over a wide
supply volt age r ange (+2.7V t o t18V). Wit hout R
G
, t he ext er nal gain set t ing
r esist or , t he in-amp gain is 5. Gains up t o 1000 can be set wit h a single ext er nal
r esist or . Common mode r eject ion of t he AD627B at 60Hz wit h a 1k sour ce
imbalance is 85dB when oper at ing on a single +3V supply and G = 5. Even t hough
t he AD627 is a t wo op amp in-amp, a pat ent ed cir cuit keeps t he CMR flat out t o a
much higher fr equency t han would be achievable wit h a convent ional discr et e t wo
op amp in-amp. The AD627 dat a sheet (available at ht t p://www.analog.com) has a
det ailed discussion of allowable input /out put volt age r anges as a funct ion of gain
and power supply volt ages. Key specificat ions for t he AD627 ar e summar ized in
Figur e 3.31.
3.35
AD627 IN-AMP ARCHITECTURE
+
_
A1
+
_
A2
+V
S
V
S
V
OUT
V
REF
100k
100k 25k 25k
R
G
V
2
V
1
G

= 5 +
200k
R
G
V
S
+V
S
V
S
V
OUT
= G(V
2
V
1
) + V
REF
Q1 Q2
V
B
+
(+) ()
Figure 3.30
AD627 IN-AMP KEY SPECIFICATIONS
n Wide Supply Range : +2.7V to 18V
n Input Voltage Range: V
S
0.1V to +V
S
1V
n 85A Supply Current
n Gain Range: 5 to 1000
n 75V Maximum Input Offset Volage (AD627B)
n 10ppm/C Maximum Offset Voltage TC (AD627B)
n 10ppm Gain Nonlinearity
n 85dB CMR @ 60Hz, 1k Source Imbalance (G = 5)
n 3V p-p 0.1Hz to 10Hz Input Voltage Noise (G = 5)
Figure 3.31
For t r ue balanced high impedance input s, t hr ee op amps may be connect ed t o for m
t he in-amp shown in Figur e 3.32. This cir cuit is t ypically r efer r ed t o as t he three op
amp in-amp. The gain of t he amplifier is set by t he r esist or , R
G
, which may be
int er nal, ext er nal, or (soft war e or pin-st r ap) pr ogr ammable. In t his configur at ion,
CMR depends upon t he r at io mat ching of R3/R2 t o R3'/R2'. Fur t her mor e, common
mode signals ar e only amplified by a fact or of 1 r egar dless of gain (no common mode
volt age will appear acr oss R
G
, hence, no common mode cur r ent will flow in it
3.36
because t he input t er minals of an op amp will have no significant pot ent ial
differ ence bet ween t hem). Thus, CMR will t heor et ically incr ease in dir ect pr opor t ion
t o gain. Lar ge common mode signals (wit hin t he A1-A2 op amp headr oom limit s)
may be handled at all gains. Finally, because of t he symmet r y of t his configur at ion,
common mode er r or s in t he input amplifier s, if t hey t r ack, t end t o be canceled out by
t he subt r act or out put st age. These feat ur es explain t he popular it y of t he t hr ee op
amp in-amp configur at ion.
THREE OP AMP INSTRUMENTATION AMPLIFIER
V
OUT
R
G
R1'
R1
R2'
R2
R3'
R3
+
_
+
_
+
_
V
REF
V
OUT
= V
SIG
1 +
2R1
R
G
+ V
REF
R3
R2
IF R2 = R3, G = 1 +
2R1
R
G
CMR 20log
GAIN 100
% MISMATCH
~
~
~
V
CM
+
_
+
_
V
SIG
2
V
SIG
2
A1
A2
A3
Figure 3.32
The classic t hr ee op amp configur at ion has been used in a number of monolit hic IC
inst r ument at ion amplifier s. Besides offer ing excellent mat ching bet ween t he t hr ee
int er nal op amps, t hin film laser t r immed r esist or s pr ovide excellent r at io mat ching
and gain accur acy at much lower cost t han using discr et e op amps and r esist or
net wor ks. The AD620 is an excellent example of monolit hic in-amp t echnology, and
a simplified schemat ic is shown in Figur e 3.33.
The AD620 is a highly popular in-amp and is specified for power supply volt ages
fr om t2.3V t o t18V. Input volt age noise is only 9nV/Hz @1kHz. Maximum input
bias cur r ent is only 1nA maximum because of t he Super bet a input st age.
Over volt age pr ot ect ion is pr ovided by t he int er nal 400 t hin-film cur r ent -limit
r esist or s in conjunct ion wit h t he diodes which ar e connect ed fr om t he emit t er -t o-
base of Q1 and Q2. The gain is set wit h a single ext er nal R
G
r esist or . The
appr opr iat e int er nal r esist or s ar e t r immed so t hat st andar d 1% or 0.1% r esist or s can
be used t o set t he AD620 gain t o popular gain values.
3.37
AD620 IN-AMP SIMPLIFIED SCHEMATIC
V
B
400 400
24.7k 24.7k
10k
10k
10k
10k
V
O
V
REF
+IN IN
R
G
+
_
+
_
_
+
+V
S
V
S
A1 A2
A3
Q1 Q2
R
G
=
49.4k
G 1
Figure 3.33
As in t he case of t he t wo op amp in-amp configur at ion, single supply oper at ion of t he
t hr ee op amp in-amp r equir es an under st anding of t he int er nal node volt ages.
Figur e 3.34 shows a gener alized diagr am of t he in-amp oper at ing on a single +5V
supply. The maximum and minimum allowable out put volt ages of t he individual op
amps ar e designat ed V
OH
(maximum high out put ) and V
OL
(minimum low out put )
r espect ively. Not e t hat t he gain fr om t he common mode volt age t o t he out put s of A1
and A2 is unit y, and t hat the sum of the common mode voltage and the signal voltage
at these outputs must fall within the amplifier output voltage range. It is obvious t hat
t his configur at ion cannot handle input common mode volt ages of eit her zer o volt s or
+5V because of sat ur at ion of A1 and A2. As in t he case of t he t wo op amp in-amp,
t he out put r efer ence is posit ioned halfway bet ween V
OH
and V
OL
in or der t o allow
for bipolar differ ent ial input signals.
This chapt er has emphasized t he oper at ion of high per for mance linear cir cuit s fr om
a single, low-volt age supply (5V or less) is a common r equir ement . While t her e ar e
many pr ecision single supply oper at ional amplifier s, such as t he OP213, t he OP291,
and t he OP284, and some good single-supply inst r ument at ion amplifier s, t he
highest per for mance inst r ument at ion amplifier s ar e st ill specified for dual-supply
oper at ion.
3.38
THREE OP AMP IN-AMP
SINGLE +5V SUPPLY RESTRICTIONS
V
OUT
R
G
R1'
R1
R2'
R2
R2'
R2
+
_
+
_
+
_
V
REF
~
~
~
V
CM
+
_
+
_
V
SIG
2
V
SIG
2
V
CM
+
GV
SIG
2
V
CM

GV
SIG
2
V
OH
=4.9V
V
OL
=0.1V
V
OH
=4.9V
V
OL
=0.1V
V
OH
=4.9V
V
OL
=0.1V
= 2.5V
G = 1 +
2R1
R
G
V
OUT
= GV
SIG
+ V
REF
A1
A2
A3
Figure 3.34
One way t o achieve bot h high pr ecision and single-supply oper at ion t akes advant age
of t he fact t hat sever al popular sensor s (e.g. st r ain gauges) pr ovide an out put signal
cent er ed ar ound t he (appr oximat e) mid-point of t he supply volt age (or t he r efer ence
volt age), wher e t he input s of t he signal condit ioning amplifier need not oper at e near
gr ound or t he posit ive supply volt age.
Under t hese condit ions, a dual-supply inst r ument at ion amplifier r efer enced t o t he
supply mid-point followed by a r ail-t o-r ail oper at ional amplifier gain st age pr ovides
ver y high DC pr ecision. Figur e 3.35 illust r at es one such high-per for mance
inst r ument at ion amplifier oper at ing on a single, +5V supply. This cir cuit uses an
AD620 low-cost pr ecision inst r ument at ion amplifier for t he input st age, and an
AD822 J FET-input dual r ail-t o-r ail out put oper at ional amplifier for t he out put
st age.
In t his cir cuit , R3 and R4 for m a volt age divider which split s t he supply volt age in
half t o +2.5V, wit h fine adjust ment pr ovided by a t r imming pot ent iomet er , P1. This
volt age is applied t o t he input of A1, an AD822 which buffer s it and pr ovides a low-
impedance sour ce needed t o dr ive t he AD620s r efer ence pin. The AD620s Refer ence
pin has a 10k input r esist ance and an input signal cur r ent of up t o 200A. The
ot her half of t he AD822 is connect ed as a gain-of-3 inver t er , so t hat it can out put
2.5V, r ail-t o-r ail, wit h only 0.83V r equir ed of t he AD620. This out put volt age
3.39
level of t he AD620 is well wit hin t he AD620s capabilit y, t hus ensur ing high
linear it y for t he dual-supply fr ont end. Note that the final output voltage must be
measured with respect to the +2.5V reference, and not to GND.
A PRECISION SINGLE-SUPPLY COMPOSITE
IN-AMP WITH RAIL-TO-RAIL OUTPUT
A1
A2
AD620
+
_
_
+
+
_
R
G
P1
5k
47k
R3
49.9k
R4
24.9k
75.0k
0.22F
10F
+
0.1F
1F
+5V
V
OUT
V
REF
+2.5V
10mV TO 4.98V
10Hz
NOISE
FILTER
A1, A2 = 1/2 AD822
R2
R1
REF
~
~
+
_
V
SIG
2
~
V
CM
=
+2.5V
V
SIG
2
+
_
Figure 3.35
The gener al gain expr ession for t his composit e inst r ument at ion amplifier is t he
pr oduct of t he AD620 and t he inver t ing amplifier gains:
GAIN
k
R
G
R
R
+
|
.
`
,
|
.
`
,
49 4
1
2
1
.
.
For t his example, an over all gain of 10 is r ealized wit h R
G
= 21.5k (closest
st andar d value). The t able (Figur e 3.36) summar izes var ious R
G
/gain values and
per for mance.
In t his applicat ion, t he allowable input volt age on eit her input t o t he AD620 must
lie bet ween +2V and +3.5V in or der t o maint ain linear it y. For example, at an over all
cir cuit gain of 10, t he common mode input volt age r ange spans 2.25V t o 3.25V,
allowing r oom for t he 0.25V full-scale differ ent ial input volt age r equir ed t o dr ive
t he out put 2.5V about V
REF
.
3.40
The inver t ing configur at ion was chosen for t he out put buffer t o facilit at e syst em
out put offset volt age adjust ment by summing cur r ent s int o t he A2 st age buffer s
feedback summing node. These offset cur r ent s can be pr ovided by an ext er nal DAC,
or fr om a r esist or connect ed t o a r efer ence volt age.
The AD822 r ail-t o-r ail out put st age exhibit s a ver y clean t r ansient r esponse (not
shown) and a small-signal bandwidt h over 100kHz for gain configur at ions up t o 300.
Not e t hat excellent linear it y is maint ained over 0.1V t o 4.9V V
OUT
. To r educe t he
effect s of unwant ed noise pickup, a capacit or is r ecommended acr oss A2s feedback
r esist ance t o limit t he cir cuit bandwidt h t o t he fr equencies of int er est .
PERFORMANCE SUMMARY OF THE +5V SINGLE-SUPPLY
AD620/AD822 COMPOSITE IN-AMP
CIRCUIT
GAIN
10
30
100
300
1000
R
G
( )
21.5k
5.49k
1.53k
499
149
V
OS
, RTI
(V)
1000
430
215
150
150
TC V
OS
, RTI
(V/C)
1000
430
215
150
150
NONLINEARITY
(ppm) *
< 50
< 50
< 50
< 50
< 50
BANDWIDTH
(kHz)**
600
600
300
120
30
* Nonlinearity Measured Over Output Range: 0.1V < V
OUT
< 4.90V
** Without 10Hz Noise Filter
Figure 3.36
In cases wher e zer o-volt input s ar e r equir ed, t he AD623 single supply in-amp
configur at ion shown in Figur e 3.37 offer s an at t r act ive solut ion. The PNP emit t er
follower level shift er s, Q1/Q2, allow t he input signal t o go 150mV below t he negat ive
supply and t o wit hin 1.5V of t he posit ive supply. The AD623 is fully specified for
single power supplies bet ween +3V and +12V and dual supplies bet ween t2.5V and
t6V (see Figur e 3.38). The AD623 dat a sheet (available at ht t p://www.analog.com)
cont ains an excellent discussion of allowable input /out put volt age r anges as a
funct ion of gain and power supply volt ages.
3.41
AD623 SINGLE-SUPPLY IN-AMP ARCHITECTURE
V
OUT
R
G
+
_
+
_
+
_
V
REF
IN
+IN
50k 50k
50k 50k
50k
50k
+V
S
V
S
V
S
+V
S
A1
A2
A3
Q1
Q2
Figure 3.37
AD623 IN-AMP KEY SPECIFICATIONS
n Wide Supply Range: +3V to 6V
n Input Voltage Range: V
S
0.15V to +V
S
1.5V
n 575A Maximum Supply Current
n Gain Range: 1 to 1000
n 100V Maximum Input Offset Voltage (AD623B)
n 1V/C Maximum Offset Voltage TC (AD623B)
n 50ppm Gain Nonlinearity
n 105dB CMR @ 60Hz, 1k Source Imbalance, G 100
n 3V p-p 0.1Hz to 10Hz Input Voltage Noise (G = 1)
Figure 3.38
3.42
I n st r u men t a t i on Amp li fi er DC Er r or Sou r ces
The DC and noise specificat ions for inst r ument at ion amplifier s differ slight ly fr om
convent ional op amps, so some discussion is r equir ed in or der t o fully under st and
t he er r or sour ces.
The gain of an in-amp is usually set by a single r esist or . If t he r esist or is ext er nal t o
t he in-amp, it s value is eit her calculat ed fr om a for mula or chosen fr om a t able on
t he dat a sheet , depending on t he desir ed gain.
Absolut e value laser wafer t r imming allows t he user t o pr ogr am gain accur at ely
wit h t his single r esist or . The absolut e accur acy and t emper at ur e coefficient of t his
r esist or dir ect ly affect s t he in-amp gain accur acy and dr ift . Since t he ext er nal
r esist or will never exact ly mat ch t he int er nal t hin film r esist or t empcos, a low TC
(<25ppm/C) met al film r esist or should be chosen, pr efer ably wit h a 0.1% or bet t er
accur acy.
Oft en specified as having a gain r ange of 1 t o 1000, or 1 t o 10,000, many in-amps
will wor k at higher gains, but t he manufact ur er will not guar ant ee a specific level of
per for mance at t hese high gains. In pr act ice, as t he gain-set t ing r esist or becomes
smaller , any er r or s due t o t he r esist ance of t he met al r uns and bond wir es become
significant . These er r or s, along wit h an incr ease in noise and dr ift , may make higher
single-st age gains impr act ical. In addit ion, input offset volt ages can become quit e
sizable when r eflect ed t o out put at high gains. For inst ance, a 0.5mV input offset
volt age becomes 5V at t he out put for a gain of 10,000. For high gains, t he best
pr act ice is t o use an inst r ument at ion amplifier as a pr eamplifier t hen use a post
amplifier for fur t her amplificat ion.
In a pin-pr ogr ammable gain in-amp such as t he AD621, t he gain set t ing r esist or s
ar e int er nal, well mat ched, and t he gain accur acy and gain dr ift specificat ions
include t heir effect s. The AD621 is ot her wise gener ally similar t o t he ext er nally
gain-pr ogr ammed AD620.
The gain error specificat ion is t he maximum deviat ion fr om t he gain equat ion.
Monolit hic in-amps such as t he AD624C have ver y low fact or y t r immed gain er r or s,
wit h it s maximum er r or of 0.02% at G = 1 and 0.25% at G = 500 being t ypical for
t his high qualit y in-amp. Not ice t hat t he gain er r or incr eases wit h incr easing gain.
Alt hough ext er nally connect ed gain net wor ks allow t he user t o set t he gain exact ly,
t he t emper at ur e coefficient s of t he ext er nal r esist or s and t he t emper at ur e
differ ences bet ween individual r esist or s wit hin t he net wor k all cont r ibut e t o t he
over all gain er r or . If t he dat a is event ually digit ized and pr esent ed t o a digit al
pr ocessor , it may be possible t o cor r ect for gain er r or s by measur ing a known
r efer ence volt age and t hen mult iplying by a const ant .
Nonlinearity is defined as t he maximum deviat ion fr om a st r aight line on t he plot of
out put ver sus input . The st r aight line is dr awn bet ween t he end-point s of t he act ual
t r ansfer funct ion. Gain nonlinear it y in a high qualit y in-amp is usually 0.01%
(100ppm) or less, and is r elat ively insensit ive t o gain over t he r ecommended gain
r ange.
3.43
The t ot al input offset volt age of an in-amp consist s of t wo component s (see Figur e
3.39). Input offset volt age, V
OSI
, is t hat component of input offset which is r eflect ed
t o t he out put of t he in-amp by t he gain G. Out put offset volt age, V
OSO
, is
independent of gain. At low gains, out put offset volt age is dominant , while at high
gains input offset dominat es. The out put offset volt age dr ift is nor mally specified as
dr ift at G=1 (wher e input effect s ar e insignificant ), while input offset volt age dr ift is
given by a dr ift specificat ion at a high gain (wher e out put offset effect s ar e
negligible). The t ot al out put offset er r or , r efer r ed t o t he input (RTI), is equal t o
V
OSI
+ V
OSO
/G. In-amp dat a sheet s may specify V
OSI
and V
OSO
separ at ely or
give t he t ot al RTI input offset volt age for differ ent values of gain.
IN-AMP OFFSET VOLTAGE MODEL
~
V
CM
V
OSI
V
OSO
I
B+
I
B
R
S
/2
R
S
/2
~
IN-AMP
GAIN = G
R
S
I
OS
= I
B+
I
B
OFFSET (RTI) =
V
OSO
G
+ V
OSI
+ I
B
R
S
+ I
OS
(R
S
+ R
S
)
OFFSET (RTO) = V
OSO
+ G V
OSI
+ I
B
R
S
+ I
OS
(R
S
+ R
S
)
R
G
V
REF
V
OUT
V
SIG
2
V
SIG
2
~
~
Figure 3.39
Input bias cur r ent s may also pr oduce offset er r or s in in-amp cir cuit s (see Figur e
3.39). If t he sour ce r esist ance, R
S
, is unbalanced by an amount , R
S
, (oft en t he case
in br idge cir cuit s), t hen t her e is an addit ional input offset volt age er r or due t o t he
bias cur r ent , equal t o I
B
R
S
(assuming t hat I
B+
I
B
= I
B
). This er r or is r eflect ed
t o t he out put , scaled by t he gain G. The input offset cur r ent , I
OS
, cr eat es an input
offset volt age er r or acr oss t he sour ce r esist ance, R
S
+R
S
, equal t o I
OS
( R
S
+R
S
),
which is also r eflect ed t o t he out put by t he gain, G.
In-amp common mode er r or is a funct ion of bot h gain and fr equency. Analog Devices
specifies in-amp CMR for a 1k sour ce impedance unbalance at a fr equency of 60Hz.
The RTI common mode er r or is obt ained by dividing t he common mode volt age,
V
CM
, by t he common mode r eject ion r at io, CMRR.
Power supply r eject ion (PSR) is also a funct ion of gain and fr equency. For in-amps,
it is cust omar y t o specify t he sensit ivit y t o each power supply separ at ely. Now t hat
all DC er r or sour ces have been account ed for , a wor st case DC er r or budget can be
calculat ed by r eflect ing all t he sour ces t o t he in-amp input (Figur e 3.40).
3.44
INSTRUMENTATION AMPLIFIER AMPLIFIER DC
ERRORS REFERRED TO THE INPUT (RTI)
ERROR SOURCE
Gain Accuracy (ppm)
Gain Nonlinearity (ppm)
Input Offset Voltage, V
OSI
Output Offset Voltage, V
OSO
Input Bias Current, I
B
, Flowing in R
S
Input Offset Current, I
OS
, Flowing in R
S
Common Mode Input Voltage, V
CM
Power Supply Variation, V
S
RTI VALUE
Gain Accuracy FS Input
Gain Nonlinearity FS Input
V
OSI
V
OSO
G
I
B
R
S
I
OS
(R
S
+ R
S
)
V
CM
CMRR
V
S
PSRR
Figure 3.40
I n st r u men t a t i on Amp li fi er Noi se Sou r ces
Since in-amps ar e pr imar ily used t o amplify small pr ecision signals, it is impor t ant
t o under st and t he effect s of all t he associat ed noise sour ces. The in-amp noise model
is shown in Figur e 3.41. Ther e ar e t wo sour ces of input volt age noise. The fir st is
r epr esent ed as a noise sour ce, V
NI
,

in ser ies wit h t he input , as in a convent ional op
amp cir cuit . This noise is r eflect ed t o t he out put by t he in-amp gain, G. The second
noise sour ce is t he out put noise, V
NO
, r epr esent ed as a noise volt age in ser ies wit h
t he in-amp out put . The out put noise, shown her e r efer r ed t o V
OUT
, can be r efer r ed
t o t he input by dividing by t he gain, G.
Ther e ar e t wo noise sour ces associat ed wit h t he input noise cur r ent s I
N+
and I
N
.
Even t hough I
N+
and I
N
ar e usually equal (I
N+
I
N
= I
N
), t hey ar e
uncor r elat ed, and t her efor e, t he noise t hey each cr eat e must be summed in a r oot -
sum-squar es (RSS) fashion. I
N+
flows t hr ough one half of R
S
, and I
N
t he ot her
half. This gener at es t wo noise volt ages, each having an amplit ude, I
N
R
S
/2. Each of
t hese t wo noise sour ces is r eflect ed t o t he out put by t he in-amp gain, G.
The t ot al out put noise is calculat ed by combining all four noise sour ces in an RSS
manner :
NOISE RTO BW V
NO
G V
NI
I
N
R
S
I
N
R
S
( ) + +
+
+

|
.
`
,
2 2 2
2 2
4
2 2
4
.
If I
N+
= I
N
= I
N
,
3.45
NOISE RTO BW V
NO
G V
NI
I
N
R
S
( ) + +
|
.
`
,
2 2 2
2 2
2
.
The t ot al noise, r efer r ed t o t he input (RTI) is simply t he above expr ession divided by
t he in-amp gain, G:
NOISE RTI BW
V
NO
G
V
NI
I
N
R
S
( ) + +
|
.
`
,
2
2
2
2 2
2
.
IN-AMP NOISE MODEL
~
~
V
CM
V
NI
V
NO
I
N+
I
N
R
S
/2
R
S
/2
~
IN-AMP
GAIN = G
IF I
N+
= I
N
NOISE (RTI) =
NOISE (RTO) =
BW
V
NO
2
G
2
+ V
NI
2
+
I
N
2
R
S
2
2
BW + G
2
V
NI
2
+
I
N
2
R
S
2
2
V
NO
2
+
_
REF
R
G
V
OUT
V
REF
BW = 1.57 IN-AMP Bandwidth @ Gain = G
~
V
SIG
2
V
SIG
2
Figure 3.41
In-amp dat a sheet s oft en pr esent t he t ot al volt age noise RTI as a funct ion of gain.
This noise spect r al densit y includes bot h t he input (V
NI
) and out put (V
NO
) noise
cont r ibut ions. The input cur r ent noise spect r al densit y is specified separ at ely. As in
t he case of op amps, t he t ot al noise RTI must be int egr at ed over t he in-amp closed-
loop bandwidt h t o comput e t he RMS value. The bandwidt h may be det er mined fr om
dat a sheet cur ves which show fr equency r esponse as a funct ion of gain.
I n -Amp Br i d ge Amp li fi er Er r or Bu d get An a lysi s
It is impor t ant t o under st and in-amp er r or sour ces in a t ypical applicat ion. Figur e
3.42 shows a 350 load cell which has a fullscale out put of 100mV when excit ed
wit h a 10V sour ce. The AD620 is configur ed for a gain of 100 using t he ext er nal
499 gain-set t ing r esist or . The t able shows how each er r or sour ce cont r ibut es t o t he
3.46
t ot al unadjust ed er r or of 2145ppm. The gain, offset , and CMR er r or s can be r emoved
wit h a syst em calibr at ion. The r emaining er r or s - gain nonlinear it y and 0.1Hz t o
10Hz noise - cannot be r emoved wit h calibr at ion and limit t he syst em r esolut ion t o
42.8ppm (appr oximat ely 14-bit accur acy).
AD620B BRIDGE AMPLIFIER DC ERROR BUDGET
+
350, , 100mV FS
LOAD CELL
AD620B SPECS @ +25C, 15V
V
OSI
+ V
OSO
/G = 55V max
I
OS
= 0.5nA max
Gain Error = 0.15%
Gain Nonlinearity = 40ppm
0.1Hz to 10Hz Noise = 280nVp-p
CMR = 120dB @ 60Hz
V
OS
I
OS
Gain Error
Gain
Nonlinearity
CMR Error
0.1Hz to 10Hz
1/f Noise
Total
Unadjusted
Error
Resolution
Error
55V 100mV
350 0.5nA 100mV
0.15%
40ppm
120dB
1ppm 5V 100mV
280nV 100mV
9 Bits Accurate
14 Bits Accurate
550ppm
1.8ppm
1500ppm
40ppm
50ppm
2.8ppm
2145ppm
42.8ppm
MAXIMUM ERROR CONTRIBUTION, +25C
FULLSCALE: V
IN
= 100mV, V
OUT
= 10V
+10V
AD620B
REF
499
R
G
G = 100
V
CM
= 5V
Figure 3.42
I n -Amp P er for ma n ce Ta bles
Figur e 3.43 shows a select ion of pr ecision in-amps designed pr imar ily for oper at ion
on dual supplies. It should be not ed t hat t he AD620 is capable of single +5V supply
oper at ion (see Figur e 3.35), but neit her it s input nor it s out put ar e capable of r ail-t o-
r ail swings.
Inst r ument at ion amplifier s specifically designed for single supply oper at ion ar e
shown in Figur e 3.44. It should be not ed t hat alt hough t he specificat ions in t he
figur e ar e given for a single +5V supply, all of t he amplifier s ar e also capable of dual
supply oper at ion and ar e specified for bot h dual and single supply oper at ion on t heir
dat a sheet s. In addit ion, t he AD623 and AD627 will oper at e on a single +3V supply.
The AD626 is not a t r ue in-amp but is a differ ent ial amplifier wit h a t hin-film input
at t enuat or which allows t he common mode volt age t o exceed t he supply volt ages.
This device is designed pr imar ily for high and low-side cur r ent -sensing applicat ions.
It will also oper at e on a single +3V supply.
3.47
PRECISION IN-AMPS:
DATA FOR V
S
= 15V, G = 1000
AD524C
AD620B
AD621B
1
AD622
AD624C
2
AD625C
AMP01A
AMP02E
Gain
Accuracy
*
0.5% / P
0.5% / R
0.05% / P
0.5% / R
0.25% / R
0.02% / R
0.6% / R
0.5% / R
Gain
Nonlinearity
100ppm
40ppm
10ppm
40ppm
50ppm
50ppm
50ppm
60ppm
V
OS
Max
50V
50V
50V
125V
25V
25V
50V
100V
V
OS
TC
0.5V/C
0.6V/C
1.6V/C
1V/C
0.25V/C
0.25V/C
0.3V/C
2V/C
CMR
Min
120dB
120dB
100dB
103dB
130dB
125dB
125dB
115dB
0.1Hz to 10Hz
p-p Noise
0.3V
0.28V
0.28V
0.3V
0.2V
0.2V
0.12V
0.4V
* / P = Pin Programmable
* / R = Resistor Programmable
1
G = 100
2
G = 500
Figure 3.43
SINGLE SUPPLY IN-AMPS:
DATA FOR V
S
= +5V, G = 1000
AD623B
AD627B
AMP04E
AD626B
1
Gain
Accuracy
*
0.5% / R
0.35% / R
0.4% / R
0.6% / P
Gain
Nonlinearity
50ppm
10ppm
250ppm
200ppm
V
OS
Max
100V
75V
150V
2.5mV
V
OS
TC
1V/C
1V/C
3V/C
6V/C
CMR
Min
105dB
85dB
90dB
80dB
0.1Hz to 10Hz
p-p Noise
1.5V
1.5V
0.7V
2V
* / P = Pin Programmable
* / R = Resistor Programmable
1
Differential Amplifier, G = 100
Supply
Current
575A
85A
290A
700A
Figure 3.44
3.48
I n -Amp I n p u t Over volt a ge P r ot ect i on
As int er face amplifier s for dat a acquisit ion syst ems, inst r ument at ion amplifier s ar e
oft en subject ed t o input over loads, i.e., volt age levels in excess of t he full scale for
t he select ed gain r ange. The manufact ur er 's "absolut e maximum" input r at ings for
t he device should be closely obser ved. As wit h op amps, many in-amps have absolut e
maximum input volt age specificat ions equal t o tV
S
. Ext er nal ser ies r esist or s (for
cur r ent limit ing) and Schot t ky diode clamps may be used t o pr event over load, if
necessar y. Some inst r ument at ion amplifier s have built -in over load pr ot ect ion
cir cuit s in t he for m of ser ies r esist or s (t hin film) or ser ies-pr ot ect ion FETs. In-amps
such as t he AMP-02 and t he AD524 ut ilize ser ies-pr ot ect ion FETs, because t hey act
as a low impedance dur ing nor mal oper at ion, and a high impedance dur ing fault
condit ions.
An addit ional Tr ansient Volt age Suppr esser (TVS) may be r equir ed acr oss t he input
pins t o limit t he maximum differ ent ial input volt age. This is especially applicable t o
t hr ee op amp in-amps oper at ing at high gain wit h low values of R
G
. A mor e det ailed
discussion of input volt age and EMI/RFI pr ot ect ion can be found in Sect ion 10 of t his
book.
INSTRUMENTATION AMPLIFIER
INPUT OVERVOLTAGE CONSIDERATIONS
n Always Observe Absolute Maximum Data Sheet Specs!
n Schottky Diode Clamps to the Supply Rails Will Limit
Input to Approximately V
S
0.3V, TVSs Limit Differential Voltage
n External Resistors (or Internal Thin-Film Resistors) Can Limit
Input Current, but will Increase Noise
n Some In-Amps Have Series-Protection Input FETs for Lower Noise
and Higher Input Over-Voltages (up to 60V, Depending on Device)
R
LIMIT
R
LIMIT
+
+V
S
V
S
IN-AMP INPUTS
OUTPUT
Figure 3.45
3.49
CHOP P ER STABI LI ZED AMP LI FI ERS
For t he lowest offset and dr ift per for mance, chopper -st abilized amplifier s may be t he
only solut ion. The best bipolar amplifier s offer offset volt ages of 10V and 0.1V/C
dr ift . Offset volt ages less t han 5V wit h pr act ically no measur able offset dr ift ar e
obt ainable wit h chopper s, albeit wit h some penalt ies.
The basic chopper amplifier cir cuit is shown in Figur e 3.46. When t he swit ches ar e
in t he "Z" (aut o-zer o) posit ion, capacit or s C2 and C3 ar e char ged t o t he amplifier
input and out put offset volt age, r espect ively. When t he swit ches ar e in t he "S"
(sample) posit ion, V
IN
is connect ed t o V
OUT
t hr ough t he pat h compr ised of R1, R2,
C2, t he amplifier , C3, and R3. The chopping fr equency is usually bet ween a few
hundr ed Hz and sever al kHz, and it should be not ed t hat because t his is a sampling
syst em, t he input fr equency must be much less t han one-half t he chopping
fr equency in or der t o pr event er r or s due t o aliasing. The R1/C1 combinat ion ser ves
as an ant ialiasing filt er . It is also assumed t hat aft er a st eady st at e condit ion is
r eached, t her e is only a minimal amount of char ge t r ansfer r ed dur ing t he swit ching
cycles. The out put capacit or , C4, and t he load, R
L
, must be chosen such t hat t her e is
minimal V
OUT
dr oop dur ing t he aut o-zer o cycle.
CLASSIC CHOPPER AMPLIFIER
CHOPPER
SWITCH
DRIVER
V
IN
V
OUT
AMP
C1
C2 C3
C4
S
Z
S
Z
S = SAMPLE
Z = AUTO-ZERO
R1 R2 R3
R
L
Figure 3.46
3.50
The basic chopper amplifier of Figur e 3.46 can pass only ver y low fr equencies
because of t he input filt er ing r equir ed t o pr event aliasing. The chopper-stabilized
ar chit ect ur e shown in Figur e 3.47 is most oft en used in chopper amplifier
implement at ions. In t his cir cuit , A1 is t he main amplifier , and A2 is t he nulling
amplifier . In t he sample mode (swit ches in "S" posit ion), t he nulling amplifier , A2,
monit or s t he input offset volt age of A1 and dr ives it s out put t o zer o by applying a
suit able cor r ect ing volt age at A1's null pin. Not e, however , t hat A2 also has an input
offset volt age, so it must cor r ect it s own er r or befor e at t empt ing t o null A1's offset .
This is achieved in t he aut o-zer o mode (swit ches in "Z" posit ion) by moment ar ily
disconnect ing A2 fr om A1, shor t ing it s input s t oget her , and coupling it s out put t o it s
own null pin. Dur ing t he aut o-zer o mode, t he cor r ect ion volt age for A1 is
moment ar ily held by C1. Similar ly, C2 holds t he cor r ect ion volt age for A2 dur ing t he
sample mode. In moder n IC chopper -st abilized op amps, t he st or age capacit or s C1
and C2 ar e on-chip.
CHOPPER STABILIZED AMPLIFIER
_
+
+
_
S Z
S
Z
A1
A2
C1
C2
NULL
NULL
IN
+IN
V
OUT
S = SAMPLE
Z = AUTO-ZERO
Figure 3.47
Not e in t his ar chit ect ur e t hat t he input signal is always connect ed t o t he out put
t hr ough A1. The bandwidt h of A1 t hus det er mines t he over all signal bandwidt h,
and t he input signal is not limit ed t o less t han one-half t he chopping fr equency as in
t he case of t he t r adit ional chopper amplifier ar chit ect ur e. However , t he swit ching
act ion does pr oduce small t r ansient s at t he chopping fr equency which can mix wit h
t he input signal fr equency and pr oduce in-band dist or t ion.
3.51
It is int er est ing t o consider t he effect s of a chopper amplifier on low fr equency 1/f
noise. If t he chopping fr equency is consider ably higher t han t he 1/f cor ner fr equency
of t he input noise, t he chopper -st abilized amplifier cont inuously nulls out t he 1/f
noise on a sample-by-sample basis. Theor et ically, a chopper op amp t her efor e has no
1/f noise. However , t he chopping act ion pr oduces wideband noise which is gener ally
much wor se t han t hat of a pr ecision bipolar op amp.
Figur e 3.48 shows t he noise of a pr ecision bipolar amplifier (OP177/AD707) ver sus
t hat of t he AD8551/52/54 chopper -st abilized op amp. The peak-t o-peak noise in
var ious bandwidt hs is calculat ed for each in t he t able below t he gr aphs. Not e t hat as
t he fr equency is lower ed, t he chopper amplifier noise cont inues t o dr op, while t he
bipolar amplifier noise appr oaches a limit det er mined by t he 1/f cor ner fr equency
and it s whit e noise (see Figur e 3.9). At a ver y low fr equency, t he noise per for mance
of t he chopper is super ior t o t hat of t he bipolar op amp.
NOISE: BIPOLAR VS. CHOPPER AMPLIFIER
v
nw
5
10
15
20
25
30
0.1 1 10 100
FREQUENCY (Hz)
Bipolar: OP177/AD707
1/F CORNER
F
C
= 0.7Hz
(WHITE)
30
40
50
60
70
80
0.01 0.1 1 10
FREQUENCY (Hz)
Chopper: AD8551/52/54
BIPOLAR (OP177/AD707)
0.238V p-p
0.135V p-p
0.120V p-p
0.118V p-p
CHOPPER (AD8551/52/54)
1.04 V p-p
0.33V p-p
0.104V p-p
0.033V p-p
NOISE BW
0.1Hz to 10Hz
0.01Hz to 1Hz
0.001Hz to 0.1Hz
0.0001Hz to 0.01Hz
INPUT VOLTAGE NOISE, nV / Hz
Figure 3.48
The AD8551/8552/8554 family of chopper -st abilized op amps offer s r ail-t o-r ail input
and out put single supply oper at ion, low offset volt age, and low offset dr ift . The
st or age capacit or s ar e int er nal t o t he IC, and no ext er nal capacit or s ot her t han
st andar d decoupling capacit or s ar e r equir ed. Key specificat ions for t he devices ar e
given in Figur e 3.49. It should be not ed t hat ext r eme car e must be t aken when
applying t hese devices t o avoid par asit ic t her mocouple effect s in or der t o fully r ealize
t he offset and dr ift per for mance. A fur t her discussion of par asit ic t her mocouples can
be found in Sect ion 10.
3.52
AD8551/52/54 CHOPPER STABILIZED
RAIL-TO-RAIL INPUT/OUTPUT AMPLIFIERS
n Single Supply: +3V to +5V
n 5V Max. Input Offset Voltage
n 0.04V/C Input Offset Voltage Drift
n 120dB CMR, PSR
n 800A Supply Current / Op Amp
n 100s Overload Recovery Time
n 50nV/ Hz Input Voltage Noise
n 1.5MHz Gain-Bandwidth Product
n Single (AD8551), Dual (AD8552) and Quad (AD8554)
Figure 3.49
I SOLATI ON AMP LI FI ERS
Ther e ar e many applicat ions wher e it is desir able, or even essent ial, for a sensor t o
have no dir ect ("galvanic") elect r ical connect ion wit h t he syst em t o which it is
supplying dat a, eit her in or der t o avoid t he possibilit y of danger ous volt ages or
cur r ent s fr om one half of t he syst em doing damage in t he ot her , or t o br eak an
int r act able gr ound loop. Such a syst em is said t o be "isolat ed", and t he ar r angement
which passes a signal wit hout galvanic connect ions is known as an "isolat ion
bar r ier ".
The pr ot ect ion of an isolat ion bar r ier wor ks in bot h dir ect ions, and may be needed in
eit her , or even in bot h. The obvious applicat ion is wher e a sensor may accident ally
encount er high volt ages, and t he syst em it is dr iving must be pr ot ect ed. Or a sensor
may need t o be isolat ed fr om accident al high volt ages ar ising downst r eam, in or der
t o pr ot ect it s envir onment : examples include t he need t o pr event t he ignit ion of
explosive gases by spar ks at sensor s and t he pr ot ect ion fr om elect r ic shock of
pat ient s whose ECG, EEG or EMG is being monit or ed. The ECG case is int er est ing,
as pr ot ect ion may be r equir ed in both dir ect ions: t he pat ient must be pr ot ect ed fr om
accident al elect r ic shock, but if t he pat ient 's hear t should st op, t he ECG machine
must be pr ot ect ed fr om t he ver y high volt ages (>7.5 kV) applied t o t he pat ient by
t he defibr illat or which will be used t o at t empt t o r est ar t it .
3.53
APPLICATIONS FOR ISOLATION AMPLIFIERS
n Sensor is at a High Potential Relative to Other Circuitry
(or may become so under Fault Conditions)
n Sensor May Not Carry Dangerous Voltages, Irrespective
of Faults in Other Circuitry
(e.g. Patient Monitoring and Intrinsically Safe Equipment
for use with Explosive Gases)
n To Break Ground Loops
Figure 3.50
J ust as int er fer ence, or unwanted infor mat ion, may be coupled by elect r ic or
magnet ic fields, or by elect r omagnet ic r adiat ion, t hese phenomena may be used for
t he t r ansmission of wanted infor mat ion in t he design of isolat ed syst ems. The most
common isolat ion amplifier s use t r ansfor mer s, which exploit magnet ic fields, and
anot her common t ype uses small high volt age capacit or s, exploit ing elect r ic fields.
Opt o-isolat or s, which consist of an LED and a phot ocell, pr ovide isolat ion by using
light , a for m of elect r omagnet ic r adiat ion. Differ ent isolat or s have differ ing
per for mance: some ar e sufficient ly linear t o pass high accur acy analog signals acr oss
an isolat ion bar r ier , wit h ot her s t he signal may need t o be conver t ed t o digit al for m
befor e t r ansmission, if accur acy is t o be maint ained, a common applicat ion for V/F
conver t er s.
Tr ansfor mer s ar e capable of analog accur acy of 12-16 bit s and bandwidt hs up t o
sever al hundr ed kHz, but t heir maximum volt age r at ing r ar ely exceeds 10kV, and is
oft en much lower . Capacit ively coupled isolat ion amplifier s have lower accur acy,
per haps 12-bit s maximum, lower bandwidt h, and lower volt age r at ings - but t hey
ar e cheap. Opt ical isolat or s ar e fast and cheap, and can be made wit h ver y high
volt age r at ings (4 -7kV is one of t he mor e common r at ings), but t hey have poor
analog domain linear it y, and ar e not usually suit able for dir ect coupling of pr ecision
analog signals.
Linear it y and isolat ion volt age ar e not t he only issues t o be consider ed in t he choice
of isolat ion syst ems. Power is essent ial. Bot h t he input and t he out put cir cuit r y
must be power ed, and unless t her e is a bat t er y on t he isolat ed side of t he isolat ion
bar r ier (which is possible, but r ar ely convenient ), some for m of isolat ed power must
be pr ovided. Syst ems using t r ansfor mer isolat ion can easily use a t r ansfor mer
(eit her t he signal t r ansfor mer or anot her one) t o pr ovide isolat ed power , but it is
impr act ical t o t r ansmit useful amount s of power by capacit ive or opt ical means.
Syst ems using t hese for ms of isolat ion must make ot her ar r angement s t o obt ain
isolat ed power supplies - t his is a power ful consider at ion in favor of choosing
t r ansfor mer isolat ed isolat ion amplifier s: t hey almost invar iably include an isolat ed
power supply.
The isolat ion amplifier has an input cir cuit t hat is galvanically isolat ed fr om t he
power supply and t he out put cir cuit . In addit ion, t her e is minimal capacit ance
3.54
bet ween t he input and t he r est of t he device. Ther efor e, t her e is no possibilit y for DC
cur r ent flow, and minimum AC coupling. Isolat ion amplifier s ar e int ended for
applicat ions r equir ing safe, accur at e measur ement of low fr equency volt age or
cur r ent (up t o about 100kHz) in t he pr esence of high common-mode volt age (t o
t housands of volt s) wit h high common mode r eject ion. They ar e also useful for line-
r eceiving of signals t r ansmit t ed at high impedance in noisy envir onment s, and for
safet y in gener al-pur pose measur ement s, wher e DC and line-fr equency leakage
must be maint ained at levels well below cer t ain mandat ed minimums. Pr incipal
applicat ions ar e in elect r ical envir onment s of t he kind associat ed wit h medical
equipment , convent ional and nuclear power plant s, aut omat ic t est equipment , and
indust r ial pr ocess cont r ol syst ems.
In t he basic t wo-por t for m, t he out put and power cir cuit s ar e not isolat ed fr om one
anot her . In t he t hr ee-por t isolat or shown in Figur e 3.51, t he input cir cuit s, out put
cir cuit s, and power sour ce ar e all isolat ed fr om one anot her . The figur e shows t he
cir cuit ar chit ect ur e of a self-cont ained isolat or , t he AD210. An isolat or of t his t ype
r equir es power fr om a t wo-t er minal DC power supply. An int er nal oscillat or (50kHz)
conver t s t he DC power t o AC, which is t r ansfor mer -coupled t o t he shielded input
sect ion, t hen conver t ed t o DC for t he input st age and t he auxiliar y power out put .
The AC car r ier is also modulat ed by t he amplifier out put , t r ansfor mer -coupled t o t he
out put st age, demodulat ed by a phase-sensit ive demodulat or (using t he car r ier as
t he r efer ence), filt er ed, and buffer ed using isolat ed DC power der ived fr om t he
car r ier . The AD210 allows t he user t o select gains fr om 1 t o 100 using an ext er nal
r esist or . Bandwidt h is 20kHz, and volt age isolat ion is 2500V RMS (cont inuous) and
t 3500V peak (cont inuous).
AD210 3-PORT ISOLATION AMPLIFIER
MOD
DEMOD
FILTER
+
_ _
+
INPUT
POWER
SUPPLY
OUTPUT
POWER
SUPPLY
POWER
OSCILLATOR
T1
T2
T3
INPUT OUTPUT
POWER
FB
IN
+IN
I
COM
+V
ISS
V
ISS
PWR PWR COM
V
O
O
COM
+V
OSS
V
OSS
Figure 3.51
3.55
The AD210 is a 3-por t isolat ion amplifier : t he power cir cuit r y is isolat ed fr om bot h
t he input and t he out put st ages and may t her efor e be connect ed t o eit her - or t o
neit her . It uses t r ansfor mer isolat ion t o achieve 3500V isolat ion wit h 12-bit
accur acy. Key specificat ions for t he AD210 ar e summar ized in Figur e 3.52.
AD210 ISOLATION AMPLIFIER KEY FEATURES
n Transformer Coupled
n High Common Mode Voltage Isolation:
u 2500V RMS Continuous
u 3500V Peak Continuous
n Wide Bandwidth: 20kHz (Full Power)
n 0.012% Maximum Linearity Error
n Input Amplifier: Gain 1 to 100
n Isolated Input and Output Power Supplies, 15V, 5mA
Figure 3.52
A t ypical isolat ion amplifier applicat ion using t he AD210 is shown in Figur e 3.53.
The AD210 is used wit h an AD620 inst r ument at ion amplifier in a cur r ent -sensing
syst em for mot or cont r ol. The input of t he AD210, being isolat ed, can be connect ed
t o a 110 or 230 V power line wit hout any pr ot ect ion, and t he isolat ed 15 V power s
t he AD620, which senses t he volt age dr op in a small cur r ent sensing r esist or . The
110 or 230V RMS common-mode volt age is ignor ed by t he isolat ed syst em. The
AD620 is used t o impr ove syst em accur acy: t he V
OS
of t he AD210 is 15mV, while
t he AD620 has V
OS
of 30V and cor r espondingly lower dr ift . If higher DC offset and
dr ift ar e accept able, t he AD620 may be omit t ed, and t he AD210 used dir ect ly at a
closed loop gain of 100.
3.56
MOTOR CONTROL CURRENT SENSING
MOD
DEMOD
FILTER
+
_ _
+
INPUT
POWER
SUPPLY
OUTPUT
POWER
SUPPLY
POWER
OSCILLATOR
T1
T2
T3
INPUT OUTPUT
POWER
FB
IN
+IN
I
COM
+V
ISS
V
ISS
PWR PWR COM
V
O
O
COM
+V
OSS
V
OSS
REF
+15V
15V
HIGH VOLAGE
AC INPUT < 2500V RMS
M
R
G
0.01
AD620
AD210
+15V
+
_
R
G
= 499
FOR G = 100
OUTPUT
Figure 3.53
3.57
REFERENCES
1. Walt er G. J ung, I C Op a mp Cook book , Th i r d Ed i t i on ,
Pr ent ice-Hall, 1986, ISBN: 0-672-22453-4.
3. Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1992.
4. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1994.
5. Li n ea r Desi gn Semi n a r , An a log Devi ces, Inc., 1995.
6. P r a ct i ca l An a log Desi gn Tech n i qu es, Analog Devices, Inc., 1995.
7. Hi gh Sp eed Desi gn Tech n i qu es, Analog Devices, Inc., 1996.
8. J ames L. Melsa and Donald G. Schult z, Li n ea r Con t r ol Syst ems,
McGr aw-Hill, 1969, pp. 196-220.
9. Thomas M. Fr edr ickson, I n t u i t i ve Op er a t i on a l Amp li fi er s, McGr aw-Hill,
1988.
10. Paul R. Gr ay and Rober t G. Meyer , An a lysi s a n d Desi gn of An a log
I n t egr a t e d Ci r cu i t s, Se con d Ed i t i on , J ohn Wiley, 1984.
11. J . K. Rober ge, Op er a t i on a l Amp li fi er s-Th eor y a n d P r a ct i ce,
J ohn Wiley, 1975.
12. Lewis Smit h and Dan Sheingold, Noise and Operational Amplifier Circuits,
An a log Di a logu e 25t h An n i ver sa r y I ssu e, pp. 19-31, 1991. (Also AN358)
13. D. St out , M. Kaufman, Ha n d book of Op er a t i on a l Amp li fi er Ci r cu i t
Desi gn , New Yor k, McGr aw-Hill, 1976.
14. J oe Buxt on, Careful Design Tames High-S peed Op Amps, Elect r on i c
Desi gn , Apr il 11, 1991.
15. J . Dost al, Op er a t i on a l Amp li fi er s, Elsevier Scient ific Publishing,
New Yor k, 1981.
16. Ser gio Fr anco, Desi gn wi t h Op er a t i on a l Amp li fi er s a n d An a log
I n t egr a t ed Ci r cu i t s, Second Edit ion, McGr aw-Hill, 1998.
17. Char les Kit chin and Lew Count s, I n st r u men t a t i on Amp li fi er
Ap p li ca t i on Gu i d e, Analog Devices, 1991.
18. AD623 and AD627 Inst r ument at ion Amplifier Dat a Sheet s,
3.58
Analog Devices, ht t p://www.analog.com
19. Eamon Nash, A Practical Review of Common Mode and
Instrumentation Amplifiers, Sen sor s Ma ga zi n e, J uly 1998, pp.26 - 33.
20. Eamon Nash, Errors and Error Budget Analysis in Instrumentation
Amplifiers, Ap p li ca t i on Not e AN-539, Analog Devices.
STRAI N, FORCE, P RESSURE, AND FLOW MEASUREMENTS
4.1
SECTI ON 4
STRAI N, FORCE, P RESSURE, AND FLOW
MEASUREMENTS
Wa l t Kest er
STRAI N GAGES
The most popular elect r ical element s used in for ce measur ement s include t he
r esist ance st r ain gage, t he semiconduct or st r ain gage, and piezoelect r ic t r ansducer s.
The st r ain gage measur es for ce indir ect ly by measur ing t he deflect ion it pr oduces in
a calibr at ed car r ier . Pr essur e can be conver t ed int o a for ce using an appr opr iat e
t r ansducer , and st r ain gage t echniques can t hen be used t o measur e pr essur e. Flow
r at es can be measur ed using differ ent ial pr essur e measur ement s which also make
use of st r ain gage t echnology.
STRAIN GAGE BASED MEASUREMENTS
n Strain: Strain Gage, PiezoElectric Transducers
n Force: Load Cell
n Pressure: Diaphragm to Force to Strain Gage
n Flow: Differential Pressure Techniques
Figure 4.1
The r esist ance st r ain gage is a r esist ive element which changes in lengt h, hence
r esist ance, as t he for ce applied t o t he base on which it is mount ed causes st r et ching
or compr ession. It is per haps t he most well known t r ansducer for conver t ing for ce
int o an elect r ical var iable.
Unbonded st r ain gages consist of a wir e st r et ched bet ween t wo point s as shown in
Figur e 4.2. For ce act ing on t he wir e (ar ea = A, lengt h = L, r esist ivit y = ) will cause
t he wir e t o elongat e or shor t en, which will cause t he r esist ance t o incr ease or
decr ease pr opor t ionally accor ding t o:
R = L/A
and R/R = GFL/L,
wher e GF = Gage fact or (2.0 t o 4.5 for met als, and mor e t han 150 for
semiconduct or s).
4.2
The dimensionless quant it y L/L is a measur e of t he for ce applied t o t he wir e and is
expr essed in microstrains (1 = 10
6
cm/cm) which is t he same as par t s-per -million
(ppm). Fr om t his equat ion, not e t hat lar ger gage fact or s r esult in pr opor t ionally
lar ger r esist ance changes, hence, mor e sensit ivit y.
UNBONDED WIRE STRAIN GAGE
STRAIN
SENSING
WIRE
AREA = A
LENGTH = L
RESISTIVITY =
RESISTANCE = R
FORCE
FORCE
R =
L
A
R
R
L
L
= GF
GF = GAGE FACTOR
2 TO 4.5 FOR METALS
>150 FOR SEMICONDUCTORS
L
L
= MICROSTRAINS ( )
1 = 110
6
cm / cm = 1 ppm
Figure 4.2
Bonded st r ain gages consist of a t hin wir e or conduct ing film ar r anged in a coplanar
pat t er n and cement ed t o a base or car r ier . The gage is nor mally mount ed so t hat as
much as possible of t he lengt h of t he conduct or is aligned in t he dir ect ion of t he
st r ess t hat is being measur ed. Lead wir es ar e at t ached t o t he base and br ought out
for int er connect ion. Bonded devices ar e consider ably mor e pr act ical and ar e in much
wider use t han unbonded devices.
Per haps t he most popular ver sion is t he foil-t ype gage, pr oduced by phot o-et ching
t echniques, and using similar met als t o t he wir e t ypes (alloys of copper -nickel
(Const ant an), nickel-chr omium (Nichr ome), nickel-ir on, plat inum-t ungst en, et c. (see
Figur e 4.4). Gages having wir e sensing element s pr esent a small sur face ar ea t o t he
specimen; t his r educes leakage cur r ent s at high t emper at ur es and per mit s higher
isolat ion pot ent ials bet ween t he sensing element and t he specimen. Foil sensing
element s, on t he ot her hand, have a lar ge r at io of sur face ar ea t o cr oss-sect ional
ar ea and ar e mor e st able under ext r emes of t emper at ur e and pr olonged loading. The
lar ge sur face ar ea and t hin cr oss sect ion also per mit t he device t o follow t he
specimen t emper at ur e and facilit at e t he dissipat ion of self-induced heat .
4.3
BONDED WIRE STRAIN GAGE
n n SMALL SURFACE AREA
n n LOW LEAKAGE
n n HIGH ISOLATION
FORCE
FORCE
Figure 4.3
METAL FOIL STRAIN GAGE
n n PHOTO ETCHING TECHNIQUE
n n LARGE AREA
n n STABLE OVER TEMPERATURE
n n THIN CROSS SECTION
n n GOOD HEAT DISSIPATION
FORCE
FORCE
Figure 4.4
4.4
Semiconduct or st r ain gages make use of t he piezor esist ive effect in cer t ain
semiconduct or mat er ials such as silicon and ger manium in or der t o obt ain gr eat er
sensit ivit y and higher -level out put . Semiconduct or gages can be pr oduced t o have
eit her posit ive or negat ive changes when st r ained. They can be made physically
small while st ill maint aining a high nominal r esist ance. Semiconduct or st r ain gage
br idges may have 30 t imes t he sensit ivit y of br idges employing met al films, but ar e
t emper at ur e sensit ive and difficult t o compensat e. Their change in r esist ance wit h
st r ain is also nonlinear . They ar e not in as widespr ead use as t he mor e st able met al-
film devices for pr ecision wor k; however , wher e sensit ivit y is impor t ant and
t emper at ur e var iat ions ar e small, t hey may have some advant age. Inst r ument at ion
is similar t o t hat for met al-film br idges but is less cr it ical because of t he higher
signal levels and decr eased t r ansducer accur acy.
COMPARISON BETWEEN METAL AND
SEMICONDUCTOR STRAIN GAGES
PARAMETER
Measurement Range
Gage Factor
Resistance,
Resistance
Tolerance
Size, mm
METAL
STRAIN GAGE
0.1 to 40,000
2.0 to 4.5
120, 350, 600, , 5000
0.1% to 0.2%
0.4 to 150
Standard: 3 to 6
SEMICONDUCTOR
STRAIN GAGE
0.001 to 3000
50 to 200
1000 to 5000
1% to 2%
1 to 5
Figure 4.5
Piezoelect r ic for ce t r ansducer s ar e employed wher e t he for ces t o be measur ed ar e
dynamic (i.e., cont inually changing over t he per iod of int er est - usually of t he or der
of milliseconds). These devices ut ilize t he effect t hat changes in char ge ar e pr oduced
in cer t ain mat er ials when t hey ar e subject ed t o physical st r ess. In fact , piezoelect r ic
t r ansducer s ar e displacement t r ansducer s wit h quit e lar ge char ge out put s for ver y
small displacement s, but t hey ar e invar iably used as for ce t r ansducer s on t he
assumpt ion t hat in an elast ic mat er ial, displacement is pr opor t ional t o for ce.
Piezoelect r ic devices pr oduce subst ant ial out put volt age in inst r ument s such as
acceler omet er s for vibr at ion st udies. Out put impedance is high, and char ge amplifier
configur at ions, wit h low input capacit ance, ar e r equir ed for signal condit ioning.
Condit ioning a piezoelect r ic sensor out put is discussed in fur t her det ail in Sect ion 5.
4.5
St r ain gages can be used t o measur e for ce, as in Figur e 4.6 wher e a cant ilever beam
is slight ly deflect ed by t he applied for ce. Four st r ain gages ar e used t o measur e t he
flex of t he beam, t wo on t he t op side, and t wo on t he bot t om side. The gages ar e
connect ed in an all-element br idge configur at ion. Recall fr om Sect ion 2 t hat t his
configur at ion gives maximum sensit ivit y and is inher ent ly linear . This configur at ion
also offer s fir st -or der cor r ect ion for t emper at ur e dr ift in t he individual st r ain gages.
STRAIN GAGE BEAM FORCE SENSOR
R1
R2
R3
R4
FORCE
V
O
R1
R2
R4
R3
V
B
+
_
RIGID BEAM
Figure 4.6
St r ain gages ar e low-impedance devices; t hey r equir e significant excit at ion power t o
obt ain r easonable levels of out put volt age. A t ypical st r ain-gage based load cell
br idge will have (t ypically) a 350 impedance and is specified as having a sensit ivit y
in t er ms of millivolt s full scale per volt of excit at ion. The load cell is composed of four
individual st r ain gages ar r anged as a br idge as shown in Figur e 4.7. For a 10V
br idge excit at ion volt age wit h a r at ing of 3mV/V, 30 millivolt s of signal will be
available at full scale loading. The out put can be incr eased by incr easing t he dr ive t o
t he br idge, but self-heat ing effect s ar e a significant limit at ion t o t his appr oach: t hey
can cause er r oneous r eadings or even device dest r uct ion. Many load cells have
"sense" connect ions t o allow t he signal condit ioning elect r onics t o compensat e for DC
dr ops in t he wir es. Some load cells have addit ional int er nal r esist or s which ar e
select ed for t emper at ur e compensat ion.
4.6
6-LEAD LOAD CELL
+V
B
+SENSE
V
B
+V
OUT
SENSE
V
OUT
FORCE
Figure 4.7
Pr essur es in liquids and gases ar e measur ed elect r ically by a var iet y of pr essur e
t r ansducer s. A var iet y of mechanical conver t er s (including diaphr agms, capsules,
bellows, manomet er t ubes, and Bour don t ubes) ar e used t o measur e pr essur e by
measur ing an associat ed lengt h, dist ance, or displacement , and t o measur e pr essur e
changes by t he mot ion pr oduced.
The out put of t his mechanical int er face is t hen applied t o an elect r ical conver t er
such as a st r ain gage or piezoelect r ic t r ansducer . Unlike st r ain gages, piezoelect r ic
pr essur e t r ansducer s ar e t ypically used for high-fr equency pr essur e measur ement s
(such as sonar applicat ions or cr yst al micr ophones).
4.7
PRESSURE SENSORS
PRESSURE
SOURCE
PRESSURE
SENSOR
(DIAPHRAGM)
STRAIN GAGE
SIGNAL
CONDITIONING
ELECTRONICS
MECHANICAL
OUTPUT
Figure 4.8
Ther e ar e many ways of defining flow (mass flow, volume flow, laminar flow,
t ur bulent flow). Usually t he amount of a subst ance flowing (mass flow) is t he most
impor t ant , and if t he fluid's densit y is const ant , a volume flow measur ement is a
useful subst it ut e t hat is gener ally easier t o per for m. One commonly used class of
t r ansducer s, which measur e flow r at e indir ect ly, involves t he measur ement of
pr essur e.
Flow can be der ived by t aking t he differ ent ial pr essur e acr oss t wo point s in a
flowing medium - one at a st at ic point and one in t he flow st r eam. Pitot tubes ar e
one for m of device used t o per for m t his funct ion. The flow r at e is obt ained by
measur ing t he differ ent ial pr essur e wit h st andar d pr essur e t r ansducer s as shown in
Figur e 4.9. Differ ent ial pr essur e can also be used t o measur e flow r at e using t he
venturi effect by placing a r est r ict ion in t he flow as shown in Figur e 4.10. Figur e
4.11 shows a bending vane wit h an at t ached st r ain gage placed in t he flow t o
measur e flow r at e.
4.8
PITOT TUBE USED TO MEASURE FLOW RATE
DIFFERENTIAL
PRESSURE
TRANSDUCER
STRAIN
GAGES
CONDITIONING
ELECTRONICS
FLOW
PITOT
TUBE
MECHANICAL
OUTPUT
P1
P2
Figure 4.9
MEASURING FLOW RATE USING THE VENTURI EFFECT
DIFFERENTIAL
PRESSURE
TRANSDUCER
STRAIN
GAGES
CONDITIONING
ELECTRONICS
MECHANICAL
OUTPUT
RESTRICTION
FLOW
P1
P2
Figure 4.10
4.9
BENDING VANE WITH STRAIN GAGE
USED TO MEASURE FLOW RATE
FLOW
BENDING VANE
WITH STRAIN GAGE
CONDITIONING
ELECTRONICS
"R"
Figure 4.11
BRI DGE SI GNAL CONDI TI ONI NG CI RCUI TS
An example of an all-element var ying br idge cir cuit is a fat igue monit or ing st r ain
sensing cir cuit as shown in Figur e 4.12. The full br idge is an int egr at ed unit t hat
can be at t ached t o t he sur face on which t he st r ain or flex is t o be measur ed. In or der
t o facilit at e r emot e sensing, cur r ent excit at ion is used. The OP177 ser vos t he br idge
cur r ent t o 10mA ar ound a r efer ence volt age of 1.235V. The st r ain gauge pr oduces an
out put of 10.25mV/1000. The signal is amplified by t he AD620 inst r ument at ion
amplifier which is configur ed for a gain of 100. Full-scale st r ain volt age may be set
by adjust ing t he 100 gain pot ent iomet er such t hat , for a st r ain of 3500, t he
out put r eads 3.500V; and for a st r ain of +5000, t he out put r egist er s a +5.000V.
The measur ement may t hen be digit ized wit h an ADC which has a 10V fullscale
input r ange. The 0.1F capacit or acr oss t he AD620 input pins ser ves as an EMI/RFI
filt er in conjunct ion wit h t he br idge r esist ance of 1k. The cor ner fr equency of t he
filt er is appr oximat ely 1.6kHz.
4.10
PRECISION STRAIN GAGE SENSOR AMPLIFIER
OP177
AD620
AD589
STRAIN SENSOR:
Columbia Research Labs 2682
Range: 3500 to +5000
Output: 10.25mV/1000
+15V
+1.235V
499
100
100
1.7k
8.2k
2N2907A
30.1k
124
27.4k
+15V
+15V 15V
15V
0.1F
+15V
10mA
+1.235V
7
1
8
6
5
4
2
3
2 3
7 4
6
+
+
V
OUT
3.500V = 3500
+5.000V = +5000
1k
1k
1k
1k
Figure 4.12
Anot her example is a load cell amplifier cir cuit shown in Figur e 4.13. A t ypical load
cell has a br idge r esist ance of 350. A 10.000V br idge excit at ion is der ived fr om an
AD588 pr ecision volt age r efer ence wit h an OP177 and 2N2219A used as a buffer .
The 2N2219A is wit hin t he OP177 feedback loop and supplies t he necessar y br idge
dr ive cur r ent (28.57mA). To ensur e t his linear it y is pr eser ved, an inst r ument at ion
amplifier is used. This design has a minimum number of cr it ical r esist or s and
amplifier s, making t he ent ir e implement at ion accur at e, st able, and cost effect ive.
The only r equir ement is t hat t he 475 r esist or and t he 100 pot ent iomet er have
low t emper at ur e coefficient s so t hat t he amplifier gain does not dr ift over
t emper at ur e.
4.11
PRECISION LOAD CELL AMPLIFIER
350
350
350
350
AD620
AD588
2
1
3
9
4 6 8 10
13
12
11
16
15V
+15V
+15V
1k
+10.000V
2N2219A
6
7
3
2
4
+15V
15V
+
15V
+15
2
3
4
5
6
8
1
7
475 100
V
OUT
0 TO +10.000V FS
+
+10.000V
350 LOAD CELL
100mV FS
OP177
Figure 4.13
As has been pr eviously shown, a pr ecision load cell is usually configur ed as a 350
br idge. Figur e 4.14 shows a pr ecision load-cell amplifier t hat is power ed fr om a
single supply. The excit at ion volt age t o t he br idge must be pr ecise and st able,
ot her wise it int r oduces an er r or in t he measur ement . In t his cir cuit , a pr ecision
REF195 5V r efer ence is used as t he br idge dr ive. The REF195 r efer ence can supply
mor e t han 30mA t o a load, so it can dr ive t he 350 br idge wit hout t he need of a
buffer . The dual OP213 is configur ed as a t wo op amp in-amp wit h a gain of 100.
The r esist or net wor k set s t he gain accor ding t o t he for mula:
G
k k
= + +
+
= 1
10
1k
20
196 28 7
100
.
.
For opt imum common-mode r eject ion, t he r esist or r at ios must be pr ecise. High
t oler ance r esist or s (0.5% or bet t er ) should be used.
For a zer o volt br idge out put signal, t he amplifier will swing t o wit hin 2.5mV of 0V.
This is t he minimum out put limit of t he OP213. Ther efor e, if an offset adjust ment is
r equir ed, t he adjust ment should st ar t fr om a posit ive volt age at V
REF
and adjust
V
REF
downwar d unt il t he out put (V
OUT
) st ops changing. This is t he point wher e
t he amplifier limit s t he swing. Because of t he single supply design, t he amplifier
cannot sense signals which have negat ive polar it y. If linear it y at zer o volt s input is
r equir ed, or if negat ive polar it y signals must be pr ocessed, t he V
REF
connect ion can
be connect ed t o a volt age which is mid-supply (2.5V) r at her t han gr ound. Not e t hat
when V
REF
is not at gr ound, t he out put must be r efer enced t o V
REF
.
4.12
SINGLE SUPPLY LOAD CELL AMPLIFIER
350
350
350
350
1/2
OP213
1/2
OP213
REF195
+5.000V
+V
S
2
4
6
10k
1k
28.7 196
1k 10k

+ +
G = 100
V
OUT
1F
2
8
3
4
1 7
6
5
(V
REF
)
Figure 4.14
The AD7730 24-bit sigma-delt a ADC is ideal for dir ect condit ioning of br idge out put s
and r equir es no int er face cir cuit r y. The simplified connect ion diagr am is shown in
Figur e 4.15. The ent ir e cir cuit oper at es on a single +5V supply which also ser ves as
t he br idge excit at ion volt age. Not e t hat t he measur ement is r at iomet r ic because t he
sensed br idge excit at ion volt age is also used as t he ADC r efer ence. Var iat ions in t he
+5V supply do not affect t he accur acy of t he measur ement .
The AD7730 has an int er nal pr ogr ammable gain amplifier which allows a fullscale
br idge out put of 10mV t o be digit ized t o 16-bit accur acy. The AD7730 has self and
syst em calibr at ion feat ur es which allow offset and gain er r or s t o be minimized wit h
per iodic r ecalibr at ions. A "chop" mode opt ion minimizes t he offset volt age and dr ift
and oper at es similar ly t o a chopper -st abilized amplifier . The effect ive input volt age
noise RTI is appr oximat ely 40nV r ms, or 264nV peak-t o-peak. This cor r esponds t o a
r esolut ion of 13 ppm, or appr oximat ely 16.5-bit s . Gain linear it y is also
appr oximat ely 16-bit s. Fur t her discussion of t his t ype of ADC can be found in
Sect ion 8.
4.13
LOAD CELL APPLICATION USING THE AD7730 ADC
+5V
AV
DD
GND
+ A
IN
A
IN
+ V
REF
V
REF
R
LEAD
R
LEAD
6-LEAD
LOAD
CELL
AD7730
ADC
24 BITS
+SENSE
SENSE
V
O
+FORCE
FORCE
DV
DD
+5V/+3V
Figure 4.15
PERFORMANCE OF AD7730 LOAD CELL ADC
n Assume:
u Fullscale Bridge Output of 10mV, +5V Excitation
u "Chop Mode" Activated
u System Calibration Performed: Zero and Fullscale
n Performance:
u Noise RTI: 40nV rms, 264nV p-p
u Noise-Free Resolution: 80,000 Counts (16.5 bits)
u Gain Nonlinearity: 18ppm
u Gain Accuracy: < 1V
u Offset Voltage: <1V
u Offset Drift: 0.5 V/C
u Gain Drift: 2ppm/C
u Note: Gain and Offset Drift Removable with System Recalibration
Figure 4.16
4.14
REFERENCES
5. Har r y L. Tr iet ley, Tr a n sd u cer s i n Mech a n i ca l a n d Elect r on i c
Desi gn , Mar cel Dekker , Inc., 1986.
6. J acob Fr aden, Ha n d b ook of Mod er n Sen sor s, Secon d Ed i t i on ,
Spr inger -Ver lag, New Yor k, NY, 1996.
7. Th e P r essu r e, St r a i n , a n d F or ce Ha n d book , Vol. 29, Omega
Engineer ing, One Omega Dr ive, P.O. Box 4047, St amfor d CT,
06907-0047, 1995. (ht t p://www.omega.com)
8. Th e Flow a n d Level Ha n d book , Vol. 29, Omega Engineer ing,
One Omega Dr ive, P.O. Box 4047, St amfor d CT, 06907-0047, 1995.
(ht t p://www.omega.com)
9. Er nest O. Doebelin, Mea su r emen t Syst ems Ap p li ca t i on s a n d
Desi gn , Four t h Edit ion, McGr aw-Hill, 1990.
10. AD7730 Dat a Sheet , Analog Devices, ht t p://www.analog.com.
HI GH I MP EDANCE SENSORS
5.1
SECTI ON 5
Wa l t Kest er , S cot t Wu r cer , Ch u ck Ki t ch i n
Many popular sensor s have out put impedances gr eat er t han sever al M, and t he
associat ed signal condit ioning cir cuit r y must be car efully designed t o meet t he
challenges of low bias cur r ent , low noise, and high gain. A lar ge por t ion of t his
sect ion is devot ed t o t he analysis of a phot odiode pr eamplifier . This applicat ion
point s out many of t he pr oblems associat ed wit h high impedance sensor signal
condit ioning cir cuit s and offer s pr act ical solut ions which can be applied t o pr act ically
all such sensor s. Ot her examples of high impedance sensor s discussed ar e
piezoelect r ic sensor s, char ge out put sensor s, and char ge coupled devices (CCDs).
HIGH IMPEDANCE SENSORS
n Photodiode Preamplifiers
n Piezoelectric Sensors
u Accelerometers
u Hydrophones
n Humidity Monitors
n pH Monitors
n Chemical Sensors
n Smoke Detectors
n Charge Coupled Devices and
Contact Image Sensors for Imaging
Figure 5.1
P HOTODI ODE P REAMP LI FI ER DESI GN
Phot odiodes gener at e a small cur r ent which is pr opor t ional t o t he level of
illuminat ion. They have many applicat ions r anging fr om pr ecision light met er s t o
high-speed fiber opt ic r eceiver s.
The equivalent cir cuit for a phot odiode is shown in Figur e 5.3. One of t he st andar d
met hods for specifying t he sensit ivit y of a phot odiode is t o st at e it s shor t cir cuit
phot ocur r ent (I
sc
) at a given light level fr om a well defined light sour ce. The most
commonly used sour ce is an incandescent t ungst en lamp r unning at a color
5.2
t emper at ur e of 2850K. At 100 fc (foot -candles) illuminat ion (appr oximat ely t he light
level on an over cast day), t he shor t cir cuit cur r ent is usually in t he picoamps t o
hundr eds of micr oamps r ange for small ar ea (less t han 1mm
2
) diodes.
PHOTODIODE APPLICATIONS
n Optical: Light Meters, Auto-Focus, Flash Controls
n Medical: CAT Scanners (X-Ray Detection), Blood Particle Analyzers
n Automotive: Headlight Dimmers, Twilight Detectors
n Communications: Fiber Optic Receivers
n Industrial: Bar Code Scanners, Position Sensors, Laser Printers
Figure 5.2
PHOTODIODE EQUIVALENT CIRCUIT
PHOTO
CURRENT
IDEAL
DIODE
INCIDENT
LIGHT
R
SH
(T)
100k -
100G
C
J
NOTE: R
SH
HALVES EVERY 10C TEMPERATURE RISE
Figure 5.3
The shor t cir cuit cur r ent is ver y linear over 6 t o 9 decades of light int ensit y, and is
t her efor e oft en used as a measur e of absolut e light levels. The open cir cuit for war d
volt age dr op acr oss t he phot odiode var ies logar it hmically wit h light level, but ,
5.3
because of it s lar ge t emper at ur e coefficient , t he diode volt age is seldom used as an
accur at e measur e of light int ensit y.
The shunt r esist ance R
SH
is usually in t he or der of 1000M at r oom t emper at ur e,
and decr eases by a fact or of 2 for ever y 10C r ise in t emper at ur e. Diode capacit ance
C
J
is a funct ion of junct ion ar ea and t he diode bias volt age. A value of 50pF at zer o
bias is t ypical for small ar ea diodes.
Phot odiodes may eit her be oper at ed wit h zer o bias (photovoltaic mode, left ) or
r ever se bias (photoconductive mode, r ight ) as shown in Figur e 5.4. The most pr ecise
linear oper at ion is obt ained in t he phot ovolt aic mode, while higher swit ching speeds
ar e r ealizable when t he diode is oper at ed in t he phot oconduct ive mode at t he
expense of linear it y. Under t hese r ever se bias condit ions, a small amount of cur r ent
called dark current will flow even when t her e is no illuminat ion. Ther e is no dar k
cur r ent in t he phot ovolt aic mode. In t he phot ovolt aic mode, t he diode noise is
basically t he t her mal noise gener at ed by t he shunt r esist ance. In t he
phot oconduct ive mode, shot noise due t o conduct ion is an addit ional sour ce of noise.
Phot odiodes ar e usually opt imized dur ing t he design pr ocess for use in eit her t he
phot ovolt aic mode or t he phot oconduct ive mode, but not bot h. Figur e 5.5 shows t he
phot osensit ivit y for a small phot odiode (Silicon Det ect or Par t Number SD-020-12-
001), and specificat ions for t he diode ar e summar ized in Figur e 5.6. This diode was
chosen for t he design example t o follow.
PHOTODIODE MODES OF OPERATION
PHOTOVOLTAIC
n Zero Bias
n No "Dark" Current
n Linear
n Low Noise (Johnson)
n Precision Applications
PHOTOCONDUCTIVE
n Reverse Bias
n Has "Dark" Current
n Nonlinear
n Higher Noise (Johnson + Shot)
n High Speed Applications
V
BIAS
+
Figure 5.4
5.4
PHOTODIODE SPECIFICATIONS
Silicon Detector Part Number SD-020-12-001
n Area: 0.2mm
2
n Capacitance: 50pF
n Shunt Resistance @ 25C: 1000M
n Maximum Linear Output Current: 40A
n Response Time: 12ns
n Photosensitivity: 0.03A / foot candle (fc)
Figure 5.5
SHORT CIRCUIT CURRENT VERSUS
LIGHT INTENSITY FOR PHOTODIODE
(PHOTOVOLTAIC MODE)
ENVIRONMENT
Direct Sunlight
Overcast Day
Twilight
Full Moonlit Night
Clear Night / No Moon
ILLUMINATION (fc)
1000
100
1
0.1
0.001
SHORT CIRCUIT CURRENT
30A
3A
0.03A
3000pA
30pA
Figure 5.6
A convenient way t o conver t t he phot odiode cur r ent int o a usable volt age is t o use
an op amp as a cur r ent -t o-volt age conver t er as shown in Figur e 5.7. The diode bias
is maint ained at zer o volt s by t he vir t ual gr ound of t he op amp, and t he shor t cir cuit
cur r ent is conver t ed int o a volt age. At maximum sensit ivit y, t he amplifier must be
able t o det ect a diode cur r ent of 30pA. This implies t hat t he feedback r esist or must
be ver y lar ge, and t he amplifier bias cur r ent ver y small. For example, 1000M will
5.5
yield a cor r esponding volt age of 30mV for t his amount of cur r ent . Lar ger r esist or
values ar e impr act ical, so we will use 1000M for t he most sensit ive r ange. This will
give an out put volt age r ange of 10mV for 10pA of diode cur r ent and 10V for 10nA of
diode cur r ent . This yields a r ange of 60dB. For higher values of light int ensit y, t he
gain of t he cir cuit must be r educed by using a smaller feedback r esist or . For t his
r ange of maximum sensit ivit y, we should be able t o easily dist inguish bet ween t he
light int ensit y on a clear moonless night (0.001fc) and t hat of a full moon (0.1fc)!
CURRENT-TO-VOLTAGE CONVERTER
(SIMPLIFIED)
I
SC
= 30pA
(0.001 fc)
+
_
R = 1000M
V
OUT
= 30mV
Sensitivity: 1mV / pA
Figure 5.7
Not ice t hat we have chosen t o get as much gain as possible fr om one st age, r at her
t han cascading t wo st ages. This is in or der t o maximize t he signal-t o-noise r at io
(SNR). If we halve t he feedback r esist or value, t he signal level decr eases by a fact or
of 2, while t he noise due t o t he feedback r esist or ( 4kTR
.
Bandwidt h) decr eases by
only 2. This r educes t he SNR by 3dB, assuming t he closed loop bandwidt h r emains
const ant . Lat er in t he analysis, we will see t hat t he r esist or s ar e one of t he lar gest
cont r ibut or s t o t he over all out put noise.
To accur at ely measur e phot odiode cur r ent s in t he t ens of picoamps r ange, t he bias
cur r ent of t he op amp should be no mor e t han a few picoamps. This nar r ows t he
choice consider ably. The indust r y-st andar d OP07 is an ult r a-low offset volt age
(10V) bipolar op amp , but it s bias cur r ent is 4nA (4000pA!). Even super -bet a
bipolar op amps wit h bias cur r ent compensat ion (such as t he OP97) have bias
cur r ent s on t he or der of 100pA at r oom t emper at ur e, but may be suit able for ver y
high t emper at ur e applicat ions, as t hese cur r ent s do not double ever y 10C r ise like
FETs. A FET-input elect r omet er -gr ade op amp is chosen for our phot odiode pr eamp,
since it must oper at e only over a limit ed t emper at ur e r ange. Figur e 5.8 summar izes
t he per for mance of sever al popular "elect r omet er gr ade" FET input op amps. These
devices ar e fabr icat ed on a BiFET pr ocess and use P-Channel J FETs as t he input
st age (see Figur e 5.9). The r est of t he op amp cir cuit is designed using bipolar
devices. The BiFET op amps ar e laser t r immed at t he wafer level t o minimize offset
volt age and offset volt age dr ift . The offset volt age dr ift is minimized by fir st
t r imming t he input st age for equal cur r ent s in t he t wo J FETs which compr ise t he
5.6
differ ent ial pair . A second t r im of t he J FET sour ce r esist or s minimizes t he input
offset volt age. The AD795 was select ed for t he phot odiode pr eamplifier , and it s key
specificat ions ar e summar ized in Figur e 5.10.
LOW BIAS CURRENT PRECISION BiFET OP AMPS
(ELECTROMETER GRADE)
PART #
AD549
AD645
AD795
V
OS
,
MAX*
250V
250V
250V
I
B
,
MAX*
100fA
1.5pA
1pA
0.1Hz TO 10Hz
NOISE
4V p-p
2V p-p
2.5V p-p
PACKAGE
TO-99
TO-99, DIP
SOIC, DIP
TC V
OS
,
MAX
5V/C
1V/C
3V/C
* 25C SPECIFICATION
Figure 5.8
BiFET OP AMP INPUT STAGE
1 5
2
3
_
+
NULL NULL
6
REST OF
AMPLIFIER
OFFSET VOLTAGE
TRIM RESISTORS
DRIFT TRIM
RESISTORS
+V
S
V
S
V
BIAS
Figure 5.9
5.7
AD795 BiFET OP AMP KEY SPECIFICATIONS
n Offset Voltage: 250V Max. @ 25C (K Grade)
n Offset Voltage Drift: 3V / C Max (K Grade)
n Input Bias Current: 1pA Max @ 25C (K Grade)
n 0.1Hz to 10Hz Voltage Noise: 2.5V p-p
n 1/f Corner Frequency: 12Hz
n Voltage Noise: 10nV / Hz @ 100Hz
n Current Noise: 0.6fA / Hz @ 100Hz
n 40mW Power Dissipation @ 15V
n 1MHz Gain Bandwidth Product
Figure 5.10
Since t he diode cur r ent is measur ed in t er ms of picoamper es, ext r eme at t ent ion
must be given t o pot ent ial leakage pat hs in t he act ual cir cuit . Two par allel
conduct or st r ipes on a high-qualit y well-cleaned epoxy-glass PC boar d 0.05 inches
apar t r unning par allel for 1 inch have a leakage r esist ance of appr oximat ely 10
11
ohms at +125
o
C. If t her e is 15 volt s bet ween t hese r uns, t her e will be a cur r ent flow
of 150pA.
The cr it ical leakage pat hs for t he phot odiode cir cuit ar e enclosed by t he dot t ed lines
in Figur e 5.11. The feedback r esist or should be t hin film on cer amic or glass wit h
glass insulat ion. The compensat ion capacit or acr oss t he feedback r esist or should
have a polypr opylene or polyst yr ene dielect r ic. All connect ions t o t he summing
junct ion should be kept shor t . If a cable is used t o connect t he phot odiode t o t he
pr eamp, it should be kept as shor t as possible and have Teflon insulat ion.
Guar ding t echniques can be used t o r educe par asit ic leakage cur r ent s by isolat ing
t he amplifier 's input fr om lar ge volt age gr adient s acr oss t he PC boar d. Physically, a
guar d is a low impedance conduct or t hat sur r ounds an input line and is r aised t o t he
line's volt age. It ser ves t o buffer leakage by diver t ing it away fr om t he sensit ive
nodes.
5.8
LEAKAGE CURRENT PATHS
+
_
C2
R2
6
7
2
3
4
+V
S
V
S
Figure 5.11
The t echnique for guar ding depends on t he mode of oper at ion, i.e., inver t ing or non-
inver t ing. Figur e 5.12 shows a PC boar d layout for guar ding t he input s of t he
AD795 op amp in t he DIP ("N") package. Not e t hat t he pin spacing allows a t r ace t o
pass bet ween t he pins of t his package. In t he inver t ing mode, t he guar d t r aces
sur r ound t he inver t ing input (pin 2) and r un par allel t o t he input t r ace. In t he
follower mode, t he guar d volt age is t he feedback volt age t o pin 2, t he inver t ing
input . In bot h modes, t he guar d t r aces should be locat ed on bot h sides of t he PC
boar d if at all possible and connect ed t oget her .
Things ar e slight ly mor e complicat ed when using guar ding t echniques wit h t he
SOIC sur face mount ("R") package because t he pin spacing does not allow for PC
boar d t r aces bet ween t he pins. Figur e 5.13 shows t he pr efer r ed met hod. In t he SOIC
"R" package, pins 1, 5, and 8 ar e "no connect " pins and can be used t o r out e signal
t r aces as shown. In t he case of t he follower , t he guar d t r ace must be r out ed ar ound
t he V
S
pin.
For ext r emely low bias cur r ent applicat ions (such as using t he AD549 wit h an input
bias cur r ent of 100fA), all connect ions t o t he input of t he op amp should be made t o
a vir gin Teflon st andoff insulat or ("Vir gin" Teflon is a solid piece of new Teflon
mat er ial which has been machined t o shape and has not been welded t oget her fr om
powder or gr ains). If mechanical and manufact ur ing consider at ions allow, t he
inver t ing input pin of t he op amp should be solder ed dir ect ly t o t he Teflon st andoff
(see Figur e 5.14) r at her t han going t hr ough a hole in t he PC boar d. The PC boar d
it self must be cleaned car efully and t hen sealed against humidit y and dir t using a
high qualit y confor mal coat ing mat er ial.
5.9
PCB LAYOUT FOR GUARDING DIP PACKAGE
4
8
7
6
5
3
GUARD
INPUT
1
2
4
8
7
6
5
3 INPUT
GUARD
GUARD
GUARD
AD795
"N"
PACKAGE
AD795
"N"
PACKAGE
AD795
2
3
6
_
+
AD795
+
_
3
2
6
INVERTER
FOLLOWER
1
2
Figure 5.12
PCB LAYOUT FOR GUARDING SOIC PACKAGE
GUARD
INPUT
INPUT
GUARD
GUARD
GUARD
AD795
"R"
PACKAGE
AD795
"R"
PACKAGE
AD795
2
3
6
_
+
AD795
+
_
3
2
6
INVERTER
FOLLOWER
V
S
1
2
3
4 5
6
7
8
V
S
1
2
3
4 5
6
7
8
PINS 1, 5, 8 ARE
OPEN ON "R"
PACKAGE
Figure 5.13
5.10
INPUT PIN CONNECTED TO
"VIRGIN" TEFLON INSULATED STANDOFF
BENT INPUT PIN:
PIN 2 FOR INVERTER
PIN 3 FOR FOLLOWER
PC
BOARD
INPUT SIGNAL
LEAD
"VIRGIN" TEFLON INSULATED STANDOFF
AD795
"N" PACKAGE
Figure 5.14
In addit ion t o minimizing leakage cur r ent s, t he ent ir e cir cuit should be well shielded
wit h a gr ounded met al shield t o pr event st r ay signal pickup.
P REAMP LI FI ER OF F SET VOLTAGE AND DRI F T ANALYSI S
An offset volt age and bias cur r ent model for t he phot odiode pr eamp is shown in
Figur e 5.15. Ther e ar e t wo impor t ant consider at ions in t his cir cuit . Fir st , t he diode
shunt r esist ance (R1) is a funct ion of t emper at ur e - it halves ever y t ime t he
t emper at ur e incr eases by 10C. At r oom t emper at ur e (+25C) , R1 = 1000M, but at
+70C it decr eases t o 43M. This has a dr ast ic impact on t he cir cuit DC noise gain
and hence t he out put offset volt age. In t he example, at +25C t he DC noise gain is
2, but at +70C it incr eases t o 24.
The second difficult y wit h t he cir cuit is t hat t he input bias cur r ent doubles ever y
10C r ise in t emper at ur e. The bias cur r ent pr oduces an out put offset er r or equal t o
I
B
R2. At +70C t he bias cur r ent incr eases t o 24pA compar ed t o it s r oom
t emper at ur e value of 1pA. Nor mally, t he addit ion of a r esist or (R3) bet ween t he non-
inver t ing input of t he op amp and gr ound having a value of R1| | R2 would yield a
fir st -or der cancellat ion of t his effect . However , because R1 changes wit h
t emper at ur e, t his met hod is not effect ive. In addit ion, t he bias cur r ent develops a
volt age acr oss t he R3 cancellat ion r esist or , which in t ur n is applied t o t he
phot odiode, t her eby causing t he diode r esponse t o become nonlinear .
The t ot al r efer r ed t o out put (RTO) offset volt age er r or s ar e summar ized in Figur e
5.16. Not ice t hat at +70C t he t ot al er r or is 33.24mV. This er r or is accept able for t he
design under consider at ion. The pr imar y cont r ibut or t o t he er r or at high
t emper at ur e is of cour se t he bias cur r ent . Oper at ing t he amplifier at r educed supply
volt ages, minimizing out put dr ive r equir ement s, and heat sinking ar e some ways t o
5.11
r educe t his er r or sour ce. The addit ion of an ext er nal offset nulling cir cuit would
minimize t he er r or due t o t he init ial input offset volt age.
AD795 PREAMPLIFIER DC OFFSET ERRORS
~
V
OS
I
B
I
B
AD795K
R1
R2
1000M
+
_
I
B
DOUBLES EVERY 10C TEMPERATURE RISE
R1 = 1000M @ 25C (DIODE SHUNT RESISTANCE)
R1 HALVES EVERY 10C TEMPERATURE RISE
DC NOISE GAIN = 1 +
R2
R1
OFFSET
RTO
R3
R3 CANCELLATION RESISTOR NOT EFFECTIVE
Figure 5.15
AD795K PREAMPLIFIER
TOTAL OUTPUT OFFSET ERROR
V
OS
Noise Gain
V
OS
Error
RTO
I
B
I
B
Error
RTO
Total Error
RTO
0C
0.325mV
1.1
0.358mV
0.2pA
0.2mV
0.558mV
25C
0.250mV
2
0.500mV
1.0pA
1mV
1.50mV
50C
0.325mV
7
2.28mV
6.0pA
6.0mV
8.28mV
70C
0.385mV
24
9.24mV
24pA
24mV
33.24mV
Figure 5.16
5.12
THERMOELECTRI C VOLTAGES AS SOURCES OF I NP UT OF F SET VOLTAGE
Ther moelect r ic pot ent ials ar e gener at ed by elect r ical connect ions which ar e made
bet ween differ ent met als at differ ent t emper at ur es. For example, t he copper PC
boar d elect r ical cont act s t o t he kovar input pins of a TO-99 IC package can cr eat e an
offset volt age of 40V/
o
C when t he t wo met als ar e at differ ent t emper at ur es.
Common lead-t in solder , when used wit h copper , cr eat es a t her moelect r ic volt age of
1 t o 3V/
o
C. Special cadmium-t in solder s ar e available t hat r educe t his t o 0.3V/
o
C.
(Refer ence 8, p. 127). The solut ion t o t his pr oblem is t o ensur e t hat t he connect ions
t o t he inver t ing and non-inver t ing input pins of t he IC ar e made wit h t he same
mat er ial and t hat t he PC boar d t her mal layout is such t hat t hese t wo pins r emain
at t he same t emper at ur e. In t he case wher e a Teflon st andoff is used as an insulat ed
connect ion point for t he inver t ing input (as in t he case of t he phot odiode pr eamp),
pr udence dict at es t hat connect ions t o t he non-inver t ing input s be made in a similar
manner t o minimize possible t her moelect r ic effect s.
P REAMP LI FI ER AC DESI GN, BANDWI DTH, AND STABI LI TY
The key t o t he pr eamplifier AC design is an under st anding of t he cir cuit noise gain
as a funct ion of fr equency. Plot t ing gain ver sus fr equency on a log-log scale makes
t he analysis r elat ively simple (see Figur e 5.17). This t ype of plot is also r efer r ed t o
as a Bode plot . The noise gain is t he gain seen by a small volt age sour ce in ser ies
wit h t he op amp input t er minals. It is also t he same as t he non-inver t ing signal gain
(t he gain fr om "A" t o t he out put ). In t he phot odiode pr eamplifier , t he signal cur r ent
fr om t he phot odiode passes t hr ough t he C2/R2 net wor k. It is impor t ant t o
dist inguish bet ween t he signal gain and t he noise gain, because it is t he noise gain
char act er ist ic which det er mines st abilit y r egar dless of wher e t he act ual signal is
applied.
St abilit y of t he syst em is det er mined by t he net slope of t he noise gain and t he open
loop gain wher e t hey int er sect . For uncondit ional st abilit y, t he noise gain cur ve
must int er sect t he open loop r esponse wit h a net slope of less t han 12dB/oct ave
(20dB per decade). The dot t ed line shows a noise gain which int er sect s t he open loop
gain at a net slope of 12dB/oct ave, indicat ing an unst able condit ion. This is what
would occur in our phot odiode cir cuit if t her e wer e no feedback capacit or (i.e. C2 =
0).
5.13
GENERALIZED NOISE GAIN (NG) BODE PLOT
0.1 1 10 100 1k 10k 100k 1M 10M
100k
10k
1k
100
10
1
Open Loop
Gain
FREQUENCY (Hz)
1 +
R2
R1
1 +
C1
C2
f
U
f
CL
= Closed Loop BW
+
_
C1
R1
C2
R2
NG = 1 +
R2 ( R1 C1s + 1 )
R1 ( R2 C2s + 1 )
= 1 +
R2
R1

1
s + 1

2
s + 1

1
=
R1 R2
R1+R2
C1 + C2

2
= R2 C2
f
1
=
1
2
1
f
2
=
1
2
2
C2 = 0
GAIN
A
B
Figure 5.17
The gener al equat ions for det er mining t he br eak point s and gain values in t he Bode
plot ar e also given in Figur e 5.17. A zer o in t he noise gain t r ansfer funct ion occur s at
a fr equency of 1/2
1
, wher e
1
= R1| | R2(C1 + C2). The pole of t he t r ansfer funct ion
occur s at a cor ner fr equency of 1/2
2
, wher e
2
= R2C2 which is also equal t o t he
signal bandwidt h if t he signal is applied at point "B". At low fr equencies, t he noise
gain is 1 + R2/R1. At high fr equencies, it is 1 + C1/C2. Plot t ing t he cur ve on t he log-
log gr aph is a simple mat t er of connect ing t he br eakpoint s wit h a line having a slope
of 45. The point at which t he noise gain int er sect s t he op amp open loop gain is
called t he closed loop bandwidth. Not ice t hat t he signal bandwidth for a signal
applied at point "B" is much less, and is 1/2R2C2.
Figur e 5.18 shows t he noise gain plot for t he phot odiode pr eamplifier using t he
act ual cir cuit values. The choice of C2 det er mines t he act ual signal bandwidt h and
also t he phase mar gin. In t he example, a signal bandwidt h of 16Hz was chosen.
Not ice t hat a smaller value of C2 would r esult in a higher signal bandwidt h and a
cor r esponding r educt ion in phase mar gin. It is also int er est ing t o not e t hat alt hough
t he signal bandwidt h is only 16Hz, t he closed loop bandwidt h is 167kHz. This will
have impor t ant implicat ions wit h r espect t o t he out put noise volt age analysis t o
follow.
5.14
NOISE GAIN OF AD795 PREAMPLIFIER @ 25C
0.1 1 10 100 1k 10k 100k 1M 10M
100k
10k
1k
100
10
1
NG = 2
NG = 6
5.3Hz
16Hz = Signal BW
167kHz = f
cl
Closed Loop BW
Open Loop
Gain
FREQUENCY (Hz)
+
_
C1
R1
C2
R2
R1 = 1000M @ +25C
R2 = 1000M
C1 = 50pF
C2 = 10pF
f
u
= 1MHz
Signal BW =
1
2 R2 C2
A
B
AD795
I
D
f
u
=1MHz
GAIN
Figure 5.18
It is impor t ant t o not e t hat t emper at ur e changes do not significant ly affect t he
st abilit y of t he cir cuit . Changes in R1 (t he phot odiode shunt r esist ance) only affect
t he low fr equency noise gain and t he fr equency at which t he zer o in t he noise gain
r esponse occur s. The high fr equency noise gain is det er mined by t he C1/C2 r at io.
P HOTODI ODE P REAMP LI FI ER NOI SE ANALYSI S
To begin t he analysis, we consider t he AD795 input volt age and cur r ent noise
spect r al densit ies shown in Figur e 5.19. The AD795 per for mance is t r uly impr essive
for a J FET input op amp: 2.5V p-p 0.1Hz t o 10Hz noise, and a 1/f cor ner fr equency
of 12Hz, compar ing favor ably wit h all but t he best bipolar op amps. As shown in t he
figur e, t he cur r ent noise is much lower t han bipolar op amps, making it an ideal
choice for high impedance applicat ions.
5.15
The complet e noise model for an op amp is shown in Figur e 5.20. This model
includes t he r eact ive element s C1 and C2. Each individual out put noise cont r ibut or
is calculat ed by int egr at ing t he squar e of it s spect r al densit y over t he appr opr iat e
fr equency bandwidt h and t hen t aking t he squar e r oot :
RMS OUTPUT NOISE DUE TO V V f df
1 1
2
( ) .
In most cases, t his int egr at ion can be done by inspect ion of t he gr aph of t he
individual spect r al densit ies super imposed on a gr aph of t he noise gain. The t ot al
out put noise is t hen obt ained by combining t he individual component s in a r oot -sum-
squar es manner . The t able below t he diagr am in Figur e 5.20 shows how each
individual sour ce is r eflect ed t o t he out put and t he cor r esponding bandwidt h for
int egr at ion. The fact or of 1.57 (/2) is r equir ed t o conver t t he single pole bandwidt h
int o it s equivalent noise bandwidt h. The r esist or J ohnson noise spect r al densit y is
given by:
V
R
kTR 4 ,
wher e k is Bolt zmann's const ant (1.3810
-23
J /K) and T is t he absolut e t emper at ur e
in K. A simple way t o comput e t his is t o r emember t hat t he noise spect r al densit y of
a 1k r esist or is 4nV/Hz at +25C. The J ohnson noise of anot her r esist or value can
be found by mult iplying by t he squar e r oot of t he r at io of t he r esist or value t o
1000. J ohnson noise is br oadband, and it s spect r al densit y is const ant wit h
fr equency.
VOLTAGE AND CURRENT NOISE OF AD795
0
10
100
1k
0.1
1.0
10
100
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M
nV
Hz
fA
Hz
1 / f Corner = 12Hz
8 nV/ Hz
0.6 fA / Hz
VOTAGE NOISE DENSITY CURRENT NOISE DENSITY
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 5.19
5.16
AMPLIFIER NOISE MODEL
+
V
N
(f)
R2
R1
R3
I
N
I
N+
V
ON
V
N,R1
V
N,R3
V
N,R2
A
B
C1
C2
TOTAL NOISE RTO =
V
1
(f)
2
df + V
2
(f)
2
df + ...
1k @ +25C has 4nV/ Hz Noise
NOISE SOURCE
V
N
(f)
I
N+
I
N
R1
R2
R3
RTO
V
N
(f)Noise Gain
I
N+
R3 Noise Gain
I
N
R2
V
N,R1
(R2/R1)
V
N,R2
V
N,R3
Noise Gain
INTEGRATION BW
1.57Closed Loop BW
1.57Closed Loop BW
1.57 Signal BW
1.57 Signal BW
1.57 Signal BW
1.57Closed Loop BW
Figure 5.20
I n p u t Volt a ge Noi se
In or der t o obt ain t he out put volt age noise spect r al densit y plot due t o t he input
volt age noise, t he input volt age noise spect r al densit y plot is mult iplied by t he noise
gain plot . This is easily accomplished using t he Bode plot on a log-log scale. The
t ot al RMS out put volt age noise due t o t he input volt age noise is t hen obt ained by
int egr at ing t he squar e of t he out put volt age noise spect r al densit y plot and t hen
t aking t he squar e r oot . In most cases, t his int egr at ion may be appr oximat ed. A
lower fr equency limit of 0.01Hz in t he 1/f r egion is nor mally used. If t he bandwidt h
of int egr at ion for t he input volt age noise is gr eat er t han a few hundr ed Hz, t he input
volt age noise spect r al densit y may be assumed t o be const ant . Usually, t he value of
t he input volt age noise spect r al densit y at 1kHz will pr ovide sufficient accur acy.
It is impor t ant t o not e t hat t he input volt age noise cont r ibut ion must be int egr at ed
over t he ent ir e closed loop bandwidt h of t he cir cuit (t he closed loop bandwidt h, f
cl
, is
t he fr equency at which t he noise gain int er sect s t he op amp open loop r esponse).
This is also t r ue of t he ot her noise cont r ibut or s which ar e r eflect ed t o t he out put by
t he noise gain (namely, t he non-inver t ing input cur r ent noise and t he non-inver t ing
input r esist or noise).
The inver t ing input noise cur r ent flows t hr ough t he feedback net wor k t o pr oduce a
noise volt age cont r ibut ion at t he out put The input noise cur r ent is appr oximat ely
const ant wit h fr equency, t her efor e, t he int egr at ion is accomplished by mult iplying
t he noise cur r ent spect r al densit y (measur ed at 1kHz) by t he noise bandwidt h
which is 1.57 t imes t he signal bandwidt h (1/2R2C2). The fact or of 1.57 (/2) ar ises
when single-pole 3dB bandwidt h is conver t ed t o equivalent noise bandwidt h.
J oh n son Noi se Du e t o Feed for wa r d Resi st or R1
5.17
The noise cur r ent pr oduced by t he feedfor war d r esist or R1 also flows t hr ough t he
feedback net wor k t o pr oduce a cont r ibut ion at t he out put . The noise bandwidt h for
int egr at ion is also 1.57 t imes t he signal bandwidt h.
Non -I n ver t i n g I n p u t Cu r r en t Noi se
The non-inver t ing input cur r ent noise, I
N+
, develops a volt age noise acr oss R3
which is r eflect ed t o t he out put by t he noise gain of t he cir cuit . The bandwidt h for
int egr at ion is t her efor e t he closed loop bandwidt h of t he cir cuit . However , t her e is no
cont r ibut ion at t he out put if R3 = 0 or if R3 is bypassed wit h a lar ge capacit or which
is usually desir able when oper at ing t he op amp in t he inver t ing mode.
J oh n son Noi se Du e t o Resi st or i n Non -I n ver t i n g I n p u t
The J ohnson volt age noise due t o R3 is also r eflect ed t o t he out put by t he noise gain
of t he cir cuit . If R3 is bypassed sufficient ly, it makes no significant cont r ibut ion t o
t he out put noise.
Su mma r y of P h ot od i od e Ci r cu i t Noi se P er for ma n ce
Figur e 5.21 shows t he out put noise spect r al densit ies for each of t he cont r ibut or s at
+25C. Not e t hat t her e is no cont r ibut ion due t o I
N+
or R3 since t he non-inver t ing
input of t he op amp is gr ounded.
OUTPUT VOLTAGE NOISE COMPONENTS
SPECTRAL DENSITIES (nV / Hz) @ +25C
0.1 1 10 100 1k 10k 100k 1M 10M
0.1
1
10
100
1k
10k
4000
600
40
48
16Hz = Signal BW
5.3Hz
12Hz
16Hz
f
CL
= 167kHz
= Closed Loop BW
V
N
(f)
R1, R2
I
N
TOTAL AREAS:
R1 : 20V RMS
R2 : 20V RMS
I
N
: 3V RMS
V
N
(f ) : 24.6V RMS
TOTAL = 37.6V RMS
nV
Hz
FREQUENCY (Hz)
R1 = 1000M @ +25C
R2 = 1000M
C1 = 50pF
C2 = 10pF
f
u
= 1MHz
+
_
C1
R1
C2
R2
A
B
AD795
I
D
Figure 5.21
5.18
Noi se Red u ct i on Usi n g Ou t p u t F i lt er i n g
Fr om t he above analysis, t he lar gest cont r ibut or t o t he out put noise volt age at
+25
o
C is t he input volt age noise of t he op amp r eflect ed t o t he out put by t he noise
gain. This cont r ibut or is lar ge pr imar ily because t he noise gain over which t he
int egr at ion is per for med ext ends t o a bandwidt h of 167kHz (t he int er sect ion of t he
noise gain cur ve wit h t he open-loop r esponse of t he op amp). If t he op amp out put is
filt er ed by a single pole filt er (as shown in Figur e 5.22) wit h a 20Hz cut off fr equency
(R = 80M, C = 0.1F), t his cont r ibut ion is r educed t o less t han 1V r ms. Not ice
t hat t he same r esult s would not be achieved simply by incr easing t he feedback
capacit or , C2. Incr easing C2 lower s t he high fr equency noise gain, but t he
int egr at ion bandwidt h becomes pr opor t ionally higher . Lar ger values of C2 may also
decr ease t he signal bandwidt h t o unaccept able levels. The addit ion of t he simple
filt er r educes t he out put noise t o 28.5V r ms; appr oximat ely 75% of it s for mer value.
Aft er inser t ing t he filt er , t he r esist or noise and cur r ent noise ar e now t he lar gest
cont r ibut or s t o t he out put noise.
AD795 PHOTODIODE PREAMP
WITH OFFSET NULL ADJUSTMENT
AD795K
100
1M
100k
+15V
15V
0.1F
10pF
1000M
20Hz
LOWPASS
FILTER
INPUT OFFSET
NULL RANGE:
1.5mV
+
_
GAIN:
1mV / pA
NOISE:
28.5V RMS
I
D
NOISE:
37.6V RMS
Figure 5.22
SUMMARY OF CI RCUI T P ERFORMANCE
The diagr am for t he final opt imized design of t he phot odiode cir cuit is shown in
Figur e 5.22. Per for mance char act er ist ics ar e summar ized in Figur e 5.23. The t ot al
out put volt age dr ift over 0 t o +70C is 33mV. This cor r esponds t o 33pA of diode
cur r ent , or appr oximat ely 0.001 foot -candles. (The level of illuminat ion on a clear
moonless night ). The offset nulling cir cuit shown on t he non-inver t ing input can be
used t o null out t he r oom t emper at ur e offset . Not e t hat t his met hod is bet t er t han
5.19
using t he offset null pins because using t he offset null pins will incr ease t he offset
volt age TC by about 3V/C for each millivolt nulled. In addit ion, t he AD795 SOIC
package does not have offset nulling pins.
The input sensit ivit y based on a t ot al out put volt age noise of 44V is obt ained by
dividing t he out put volt age noise by t he value of t he feedback r esist or R2. This
yields a minimum det ect able diode cur r ent of 44fA. If a 12 bit ADC is used t o
digit ize t he 10V fullscale out put , t he weight of t he least significant bit (LSB) is
2.5mV. The out put noise level is much less t han t his.
AD795 PHOTODIODE CIRCUIT
PERFORMANCE SUMMARY
n Output Offset Error (0C to +70C) : 33mV
n Output Sensitivity: 1mV / pA
n Output Photosensitivity: 30V / foot-candle
n Total Output Noise @ +25C : 28.5V RMS
n Total Noise RTI @ +25C : 44fA RMS, or 26.4pA p-p
n Range with R2 = 1000M : 0.001 to 0.33 foot-candles
n Bandwidth: 16Hz
Figure 5.23
P HOTODI ODE CI RCUI T TRADEOFFS
Ther e ar e many t r adeoffs which could be made in t he basic phot odiode cir cuit design
we have descr ibed. Mor e signal bandwidt h can be achieved in exchange for a lar ger
out put noise level. Reducing t he feedback capacit or C2 t o 1pF incr eases t he signal
bandwidt h t o appr oximat ely 160Hz. Fur t her r educt ions in C2 ar e not pr act ical
because t he par asit ic capacit ance is pr obably in t he or der of 1 t o 2pF. A small
amount of feedback capacit ance is also r equir ed t o maint ain st abilit y.
If t he cir cuit is t o be oper at ed at higher levels of illuminat ion (gr eat er t han
appr oximat ely 0.3 fc), t he value of t he feedback r esist or can be r educed t her eby
r esult ing in fur t her incr eases in cir cuit bandwidt h and less r esist or noise. If gain-
r anging is t o be used t o measur e t he higher light levels, ext r eme car e must be t aken
in t he design and layout of t he addit ional swit ching net wor ks t o minimize leakage
pat hs.
5.20
COMP ENSATI ON OF A HI GH SP EED P HOTODI ODE I /V
CONVERTER
A classical I/V conver t er is shown in Figur e 5.24. Not e t hat it is t he same as t he
phot odiode pr eamplifier if we assume t hat R1 >> R2. The t ot al input capacit ance,
C1, is t he sum of t he diode capacit ance and t he op amp input capacit ance. This is a
classical second-or der syst em, and t he following guidelines can be applied in or der t o
det er mine t he pr oper compensat ion.
COMPENSATING FOR INPUT CAPACITANCE
IN A CURRENT-TO-VOLTAGE CONVERTER
C2
R2
C1 I
+
_
1
f
2
f
1
f
u
f
NOISE
GAIN
OPEN LOOP
GAIN
UNCOMPENSATED
COMPENSATED
f
1
=
f
2
=
f
2
= f
1
f
u
C2 =
1
2 R2 C1
1
2 R2 C2
C1
2 R2 f
u
FOR 45PHASE MARGIN
GAIN
f
u
= OP AMP UNITY
GAIN BW PRODUCT
f
2
= SIGNAL BW
f
u
Total Input
Capacitance
f
2
=
f
u
2 R2 C1
V
B
Figure 5.24
The net input capacit ance, C1, for ms a zer o at a fr equency f
1
in t he noise gain
t r ansfer funct ion as shown in t he Bode plot .
f
R C
1
1
2 2 1
.
Not e t hat we ar e neglect ing t he effect s of t he compensat ion capacit or C2 and ar e
assuming t hat it is small r elat ive t o C1 and will not significant ly affect t he zer o
fr equency f
1
when it is added t o t he cir cuit . In most cases, t his appr oximat ion yields
r esult s which ar e close enough, consider ing t he ot her var iables in t he cir cuit .
If left uncompensat ed, t he phase shift at t he fr equency of int er sect ion, f
2
, will cause
inst abilit y and oscillat ion. Int r oducing a pole at f
2
by adding t he feedback capacit or
C2 st abilizes t he cir cuit and yields a phase mar gin of about 45 degr ees.
5.21
f
R C
2
1
2 2 2
.
Since f
2
is t he geomet r ic mean of f
1
and t he unit y-gain bandwidt h fr equency of t he
op amp, f
u
,
f f f
u 2 1
.
These equat ions can be combined and solved for C2:
C
C
R f
u
2
1
2 2

.
This value of C2 will yield a phase mar gin of about 45 degr ees. Incr easing t he
capacit or by a fact or of 2 incr eases t he phase mar gin t o about 65 degr ees.
In pr act ice, t he opt imum value of C2 should be det er mined exper iment ally by
var ying it slight ly t o opt imize t he out put pulse r esponse.
SELECTI ON OF THE OP AMP FOR WI DEBAND P HOTODI ODE I /V CONVERTERS
The op amp in t he high speed phot odiode I/V conver t er should be a wideband FET-
input one in or der t o minimize t he effect s of input bias cur r ent and allow low values
of phot ocur r ent s t o be det ect ed. In addit ion, if t he equat ion for t he 3dB bandwidt h,
f
2
, is r ear r anged in t er ms of f
u
, R2, and C1, t hen
f
f
u
R C
2
2 2 1
,
wher e C1 is t he sum of t he diode capacit ance ,C
D
, and t he op amp input
capacit ance, C
IN
. In a high speed applicat ion, t he diode capacit ance will be much
smaller t han t hat of t he low fr equency pr eamplifier design pr eviously discussed -
per haps as low as a few pF.
By inspect ion of t his equat ion, it is clear t hat in or der t o maximize f
2
, t he FET-input
op amp should have bot h a high unit y gain-bandwidt h pr oduct , f
u
, and a low input
capacit ance, C
IN
. In fact , t he r at io of f
u
t o C
IN
is a good figur e-of-mer it when
evaluat ing differ ent op amps for t his applicat ion.
Figur e 5.25 compar es a number of FET-input op amps suit able for phot odiode
pr eamps. By inspect ion, t he AD823 op amp has t he highest r at io of unit y gain-
bandwidt h pr oduct t o input capacit ance, in addit ion t o r elat ively low input bias
cur r ent . For t hese r easons, it was chosen for t he wideband phot odiode pr eamp
design.
5.22
FET-INPUT OP AMP COMPARISON TABLE
FOR WIDE BANDWIDTH PHOTODIODE PREAMPS
*Stable for Noise Gains 5, Usually the Case,
Since High Frequency Noise Gain = 1 + C1/C2,
and C1 Usually 4C2
AD823
AD843
AD744
AD845
OP42
AD745*
AD795
AD820
AD743
Unity GBW
Product
fu (MHz)
16
34
13
16
10
20
1
1.9
4.5
Input
Capacitance
C
IN
(pF)
1.8
6
5.5
8
6
20
1
2.8
20
f
u
/C
IN
(MHz/pF)
8.9
5.7
2.4
2
1.6
1
1
0.7
0.2
Input Bias
Current
I
B
(pA)
3
600
100
500
100
250
1
2
250
Voltage Noise
@ 10kHz
(nV/Hz)
16
19
16
18
12
2.9
8
13
2.9
Figure 5.25
HI GH SP EED P HOTODI ODE P REAMP DESI GN
The HP 5082-4204 PIN Phot odiode will be used as an example for our discussion. It s
char act er ist ics ar e given in Figur e 5.26. It is t ypical of many commer cially available
PIN phot odiodes. As in most high-speed phot odiode applicat ions, t he diode is
oper at ed in t he r ever se-biased or photoconductive mode. This gr eat ly lower s t he
diode junct ion capacit ance, but causes a small amount of dark current t o flow even
when t he diode is not illuminat ed (we will show a cir cuit which compensat es for t he
dar k cur r ent er r or lat er in t he sect ion).
This phot odiode is linear wit h illuminat ion up t o appr oximat ely 50 t o 100A of
out put cur r ent . The dynamic r ange is limit ed by t he t ot al cir cuit noise and t he diode
dar k cur r ent (assuming no dar k cur r ent compensat ion).
5.23
HP 5082-4204 PHOTODIODE
n Sensitivity: 350A @ 1mW, 900nm
n Maximum Linear Output Current: 100A
n Area: 0.002cm
2
(0.2mm
2
)
n Capacitance: 4pF @ 10V Reverse Bias
n Shunt Resistance: 10
11

n Risetime: 10ns
n Dark Current: 600pA @ 10V Reverse Bias
Figure 5.26
Using t he cir cuit shown in Figur e 5.27, assume t hat we wish t o have a full scale
out put of 10V for a diode cur r ent of 100A. This det er mines t he value of t he
feedback r esist or R2 t o be 10V/100A = 100k.
Using t he diode capacit ance, C
D
=4pF, and t he AD823 input capacit ance, C
IN
=1.8pF, t he value of C1 = C
D
+C
IN
= 5.8pF. Solving t he above equat ions using
C1=5.8pF, R2=100k, and f
u
=16MHz, we find t hat :
f
1
= 274kHz
C2 = 0.76pF
f
2
= 2.1MHz.
In t he final design (Figur e 5.27), not e t hat t he 100k r esist or is r eplaced wit h t hr ee
33.2k film r esist or s t o minimize st r ay capacit ance. The feedback capacit or , C2, is a
var iable 1.5pF cer amic and is adjust ed in t he final cir cuit for best bandwidt h/pulse
r esponse. The over all cir cuit bandwidt h is appr oximat ely 2MHz.
The full scale out put volt age of t he pr eamp for 100A diode cur r ent is 10V, and t he
er r or (RTO) due t o t he phot odiode dar k cur r ent of 600pA is 60mV. The dar k cur r ent
er r or can be canceled using a second phot odiode of t he same t ype in t he non-
inver t ing input of t he op amp as shown in Figur e 5.27.
5.24
2MHz BANDWIDTH PHOTODIODE PREAMP
WITH DARK CURRENT COMPENSATION
AD823
D1
D2
C1
5.8pF
C2 0.8pF
33.2k 33.2k 33.2k
D1, D2: HP-5082-4204
+15V
15V
100k 0.1F
LOW LEAKAGE
POLYPROPYLENE
10V
R2 = 100k
C
D
= 4pF, C
IN
= 1.8pF
C1 = C
D
+ C
IN
= 5.8pF
+
_
Figure 5.27
HI GH SP EED P HOTODI ODE P REAMP NOI SE ANALYSI S
As in most noise analyses, only t he key cont r ibut or s need be ident ified. Because t he
noise sour ces combine in an RSS manner , any single noise sour ce t hat is at least
t hr ee or four t imes as lar ge as any of t he ot her s will dominat e.
In t he case of t he wideband phot odiode pr eamp, t he dominant sour ces of out put
noise ar e t he input volt age noise of t he op amp, V
N
, and t he r esist or noise due t o R2,
V
N,R2
(see Figur e 5.28). The input cur r ent noise of t he FET-input op amp is
negligible. The shot noise of t he phot odiode (caused by t he r ever se bias) is negligible
because of t he filt er ing effect of t he shunt capacit ance C1. The r esist or noise is easily
calculat ed by knowing t hat a 1k r esist or gener at es about 4nV/Hz, t her efor e, a
100k r esist or gener at es 40nV/Hz. The bandwidt h for int egr at ion is t he signal
bandwidt h, 2.1MHz, yielding a t ot al out put r ms noise of:
V
N R
RTO NOISE
Vr ms
,
. .
2
40 1 57 21 10
6
73 .
The fact or of 1.57 conver t s t he appr oximat e single-pole bandwidt h of 2.1MHz int o
t he equivalent noise bandwidth.
5.25
The out put noise due t o t he input volt age noise is obt ained by mult iplying t he noise
gain by t he volt age noise and int egr at ing t he ent ir e funct ion over fr equency. This
would be t edious if done r igor ously, but a few r easonable appr oximat ions can be
made which gr eat ly simplify t he mat h. Obviously, t he low fr equency 1/f noise can be
neglect ed in t he case of t he wideband cir cuit . The pr imar y sour ce of out put noise is
due t o t he high-fr equency noise-gain peaking which occur s bet ween f
1
and f
u
. If we
simply assume t hat t he out put noise is const ant over t he ent ir e r ange of fr equencies
and use t he maximum value for AC noise gain [1+(C1/C2)], t hen
V
N
RTO NOISE V
N
C
C
f Vr ms +
|
.
`
,
1
1
2
1 57
2
250 . .
The t ot al r ms noise r efer r ed t o t he out put is t hen t he RSS value of t he t wo
component s:
( ) ( ) TOTAL RTO NOISE Vr ms + 73
2
250
2
260 .
The t ot al out put dynamic r ange can be calculat ed by dividing t he full scale out put
signal (10V) by t he t ot al out put r ms noise, 260Vr ms, and conver t ing t o dB, yielding
appr oximat ely 92dB.
EQUIVALENT CIRCUIT FOR OUTPUT NOISE ANALYSIS
~
~
V
N
V
BIAS
= 10V
V
N
= 16nV/ Hz
C2
R2
V
N,R2
C1
AD823
+
_
C1 = 5.8pF
C2 = 0.76pF
R2 = 100k
1
NOISE GAIN
f
1
274kHz
f
2
2.1MHz
fu
16MHz
1 +
C1
C2
V
N
RTO NOISE V
N
1 +
C1
C2
1.57 f
2
= 250V RMS
V
N,R2
RTO NOISE 4kTR2 1.57f
2
= 73V RMS
TOTAL RTO NOISE = 250
2
+ 73
2
= 260V RMS
DYNAMIC RANGE = 20 log
10V
260V
= 92dB
Figure 5.28
5.26
HI GH I MP EDANCE CHARGE OUTP UT SENSORS
High impedance t r ansducer s such as piezoelect r ic sensor s, hydr ophones, and some
acceler omet er s r equir e an amplifier which conver t s a t r ansfer of char ge int o a
change of volt age. Because of t he high DC out put impedance of t hese devices,
appr opr iat e buffer s ar e r equir ed. The basic cir cuit for an inver t ing char ge sensit ive
amplifier is shown in Figur e 5.29. Ther e ar e basically t wo t ypes of char ge
t r ansducer s: capacit ive and char ge-emit t ing. In a capacit ive t r ansducer , t he volt age
acr oss t he capacit or (V
C
) is held const ant . The change in capacit ance, C, pr oduces a
change in char ge, Q = CV
C
. This char ge is t r ansfer r ed t o t he op amp out put as a
volt age, V
OUT
= Q/C2 = CV
C
/C2.
CHARGE AMPLIFIER FOR CAPACITIVE SENSOR
C2
R2
+
V
C
C1 C
R1
V
OUT
Q = C V
C
+
_
FOR CAPACITIVE SENSORS: V
OUT
=
V
C
C
C2
FOR CHARGE-EMITTING SENSORS: V
OUT
=
Q
C2
UPPER CUTOFF FREQUENCY = f
2
=
1
2 R2 C2
LOWER CUTOFF FREQUENCY = f
1
=
1
2 R1 C1
Figure 5.29
Char ge-emit t ing t r ansducer s pr oduce an out put char ge, Q, and t heir out put
capacit ance r emains const ant . This char ge would nor mally pr oduce an open-cir cuit
out put volt age at t he t r ansducer out put equal t o Q/C. However , since t he volt age
acr oss t he t r ansducer is held const ant by t he vir t ual gr ound of t he op amp (R1 is
usually small), t he char ge is t r ansfer r ed t o capacit or C
2
pr oducing an out put volt age
V
OUT
= Q/C2.
In an act ual applicat ion, t he char ge amplifier only r esponds t o AC input s. The upper
cut off fr equency is given by f
2
= 1/2R2C2, and t he lower by f
1
= 1/2R1C1.
5.27
LOW NOI SE CHARGE AMP LI FI ER CI RCUI T CONFI GURATI ONS
Figur e 5.30 shows t wo ways t o buffer and amplify t he out put of a char ge out put
t r ansducer . Bot h r equir e using an amplifier which has a ver y high input impedance,
such as t he AD745. The AD745 pr ovides bot h low volt age and low cur r ent noise.
This combinat ion makes t his device par t icular ly suit able in applicat ions r equir ing
ver y high char ge sensit ivit y, such as capacit ive acceler omet er s and hydr ophones.
BALANCING SOURCE IMPEDANCES MINIMIZES EFFECTS
OF BIAS CURRENTS AND REDUCES INPUT NOISE
R
S
C
S
C
B
R
B
C
F
R
F
SOURCE
+
_
AD745
C
B
= C
F
|| C
S
R
B
= R
F
|| R
S
R1
C
S
R
S
R2
SOURCE
+
_
AD745
C
B
= C
S
R
B
= R
S
FOR
R
S
>> R1, R2
C
B
R
B
CHARGE OUTPUT MODE VOLTAGE OUTPUT MODE
0
10
20
30
10 100 1000
INPUT CAPACITANCE (pF)
RTI
NOISE
nV
Hz
UNBALANCED
BALANCED
2.9 nV / Hz
Figure 5.30
The fir st cir cuit (left ) in Figur e 5.30 uses t he op amp in t he inver t ing mode.
Amplificat ion depends on t he pr inciple of conser vat ion of char ge at t he inver t ing
input of t he amplifier . The char ge on capacit or C
S
is t r ansfer r ed t o capacit or C
F
,
t hus yielding an out put volt age of Q/C
F
. The amplifier 's input volt age noise will
appear at t he out put amplified by t he AC noise gain of t he cir cuit , 1 + C
S
/C
F
.
The second cir cuit (r ight ) shown in Figur e 5.30 is simply a high impedance follower
wit h gain. Her e t he noise gain (1 + R2/R1) is t he same as t he gain fr om t he
t r ansducer t o t he out put . Resist or R
B
, in bot h cir cuit s, is r equir ed as a DC bias
cur r ent r et ur n.
To maximize DC per for mance over t emper at ur e, t he sour ce r esist ances should be
balanced on each input of t he amplifier . This is r epr esent ed by t he r esist or R
B
shown in Figur e 5.30. For best noise per for mance, t he sour ce capacit ance should
also be balanced wit h t he capacit or C
B
. In gener al, it is good pr act ice t o balance t he
sour ce impedances (bot h r esist ive and r eact ive) as seen by t he input s of a pr ecision
low noise BiFET amplifier s such as t he AD743/AD745. Balancing t he r esist ive
5.28
component s will opt imize DC per for mance over t emper at ur e because balancing will
mit igat e t he effect s of any bias cur r ent er r or s. Balancing t he input capacit ance will
minimize AC r esponse er r or s due t o t he amplifier 's non-linear common mode input
capacit ance, and as shown in Figur e 5.30, noise per for mance will be opt imized. In
any FET input amplifier , t he cur r ent noise of t he int er nal bias cir cuit r y can be
coupled t o t he input s via t he gat e-t o-sour ce capacit ances (20pF for t he AD743 and
AD745) and appear s as excess input volt age noise. This noise component is
cor r elat ed at t he input s, so sour ce impedance mat ching will t end t o cancel out it s
effect . Figur e 5.30 shows t he r equir ed ext er nal component s for bot h inver t ing and
noninver t ing configur at ions. For values of C
B
gr eat er t han 300pF, t her e is a
diminishing impact on noise, and C
B
can t hen be simply a lar ge mylar bypass
capacit or of 0.01F or gr eat er .
A 40d B GAI N P I EZOELECTRI C TRANSDUCER AMP LI FI ER OP ERATES ON
REDUCED SUP P LY VOLTAGES FOR LOWER BI AS CURRENT
Figur e 5.31 shows a piezoelect r ic t r ansducer amplifier connect ed in t he volt age-
out put mode. Reducing t he power supplies t o +5V r educes t he effect s of bias cur r ent
in t wo ways: fir st , by lower ing t he t ot al power dissipat ion and, second, by r educing
t he basic gat e-t o-junct ion leakage cur r ent . The addit ion of a clip-on heat sink such
as t he Aavid #5801will fur t her limit t he int er nal junct ion t emper at ur e r ise.
Wit hout t he AC coupling capacit or C1, t he amplifier will oper at e over a r ange of
0C t o +85C. If t he opt ional AC coupling capacit or C1 is used, t he cir cuit will
oper at e over t he ent ir e 55C t o +125C t emper at ur e r ange, but DC infor mat ion is
lost .
GAIN OF 100 PIEZOELECTRIC SENSOR AMPLIFIER
R1
C
S
R
S

10
8

R2, 10k
SOURCE +
_
AD745
C
B
R
B
,10
8

100
C1*
+5V
5V,
5V Power Supplies Reduce
I
B
for 0C to +85C Operation, P
D
= 80mW
C1 Allows 55C to +125C Operation
C
B
= C
S
I
Q
= 8mA
Figure 5.31
5.29
HYDROP HONES
Int er facing t he out put s of highly capacit ive t r ansducer s such as hydr ophones, some
acceler omet er s, and condenser micr ophones t o t he out side wor ld pr esent s many
design challenges. Pr eviously designer s had t o use cost ly hybr id amplifier s
consist ing of discr et e low-noise J FETs in fr ont of convent ional op amps t o achieve
t he low levels of volt age and cur r ent noise r equir ed by t hese applicat ions. Now,
using t he AD743 and AD745, designer s can achieve almost t he same level of
per for mance of t he hybr id appr oach in a monolit hic solut ion.
In sonar applicat ions, a piezo-cer amic cylinder is commonly used as t he act ive
element in t he hydr ophone. A t ypical cylinder has a nominal capacit ance of ar ound
6,000pF wit h a ser ies r esist ance of 10. The out put impedance is t ypically 10
8
or
100M.
Since t he hydr ophone signals of int er est ar e inher ent ly AC wit h wide dynamic
r ange, noise is t he over r iding concer n among sonar syst em designer s. The noise floor
of t he hydr ophone and t he hydr ophone pr eamplifier t oget her limit t he sensit ivit y of
t he syst em and t her efor e t he over all usefulness of t he hydr ophone. Typical
hydr ophone bandwidt hs ar e in t he 1kHz t o 10kHz r ange. The AD743 and AD745 op
amps, wit h t heir low noise figur es of 2.9nV/ Hz and high input impedance of 10
10
(or 10G) ar e ideal for use as hydr ophone amplifier s.

The AD743 and AD745 ar e companion amplifier s wit h differ ent levels of int er nal
compensat ion. The AD743 is int er nally compensat ed for unit y gain st abilit y. The
AD745, st able for noise gains of 5 or gr eat er , has a much higher bandwidt h and slew
r at e. This makes t he AD745 especially useful as a high-gain pr eamplifier wher e it
pr ovides bot h high gain and wide bandwidt h. The AD743 and AD745 also oper at e
wit h ext r emely low levels of dist or t ion: less t han 0.0003% and 0.0002% (at 1kHz),
r espect ively.
OP AMP P ERFORMANCE: J FET VERSUS BI P OLAR
The AD743 and AD745 op amps ar e t he fir st monolit hic J FET devices t o offer t he
low input volt age noise compar able t o a bipolar op amp wit hout t he high input bias
cur r ent s t ypically associat ed wit h bipolar op amps. Figur e 5.32 shows input volt age
noise ver sus input sour ce r esist ance of t he bias-cur r ent compensat ed OP27 and t he
J FET-input AD745 op amps. Not e t hat t he noise levels of t he AD743 and t he AD745
ar e ident ical. Fr om t his figur e, it is clear t hat at high sour ce impedances, t he low
cur r ent noise of t he AD745 also pr ovides lower over all noise t han a high
per for mance bipolar op amp. It is also impor t ant t o not e t hat , wit h t he AD745, t his
noise r educt ion ext ends all t he way down t o low sour ce impedances. At high sour ce
impedances, t he lower DC cur r ent er r or s of t he AD745 also r educe er r or s due t o
offset and dr ift as shown in Figur e 5.32.
5.30
EFFECTS OF SOURCE RESISTANCE
ON NOISE AND OFFSET VOLTAGE FOR
OP27(BIPOLAR) AND AD745 (BiFET) OP AMPS
100 1k 10k 100k 1M 10M
1k
100
10
1
100 1k 10k 100k 1M 10M
100
10
1
0.1
nV
Hz
mV
SOURCE RESISTANCE ( ) SOURCE RESISTANCE ( )
INPUT VOLTAGE NOISE INPUT OFFSET VOLTAGE
R
S
R
S
+
_
AD745
OP27
AD745
OP27
R
S
NOISE ONLY
OP27
AD745
Figure 5.32
A P H P ROBE BUFFER AMP LI FI ER
A t ypical pH pr obe r equir es a buffer amplifier t o isolat e it s 10
6
t o 10
9
sour ce
r esist ance fr om ext er nal cir cuit r y. Such an amplifier is shown in Figur e 5.33. The
low input cur r ent of t he AD795 allows t he volt age er r or pr oduced by t he bias cur r ent
and elect r ode r esist ance t o be minimal. The use of guar ding, shielding, high
insulat ion r esist ance st andoffs, and ot her such st andar d picoamp met hods used t o
minimize leakage ar e all needed t o maint ain t he accur acy of t his cir cuit .
The slope of t he pH pr obe t r ansfer funct ion, 50mV per pH unit at r oom t emper at ur e,
has an appr oximat e +3500ppm/C t emper at ur e coefficient . The buffer shown in
Figur e 5.33 pr ovides a gain of 20 and yields an out put volt age equal t o 1volt /pH
unit . Temper at ur e compensat ion is pr ovided by r esist or RT which is a special
t emper at ur e compensat ion r esist or ,1k, 1%, +3500ppm/C, #PT146 available fr om
Pr ecision Resist or Co., Inc. (Refer ence 18).
5.31
A pH PROBE BUFFER AMPLIFIER WITH A GAIN OF 20
USING THE AD795 PRECISION BiFET OP AMP
+V
S
V
S
+
_
GUARD
3
2
4
1
5
6
7
V
OS
ADJUST
100k
19.6k
RT
1k
+3500ppm / C
Precision Resistor Co, Inc.
#PT146
pH PROBE AD795
OUTPUT
1V / pH UNIT
50mV / pH
TC = +3500ppm / C
Output Impedance:
1M to 1G
8
Figure 5.33
CCD/CI S I MAGE P ROCESSI NG
The charge-coupled-device (CCD) and contact-image-sensor (CIS) ar e widely used in
consumer imaging syst ems such as scanner s and digit al camer as. A gener ic block
diagr am of an imaging syst em is shown in Figur e 5.34. The imaging sensor (CCD,
CMOS, or CIS) is exposed t o t he image or pict ur e much like film is exposed in a
camer a. Aft er exposur e, t he out put of t he sensor under goes some analog signal
pr ocessing and t hen is digit ized by an ADC. The bulk of t he act ual image pr ocessing
is per for med using fast digit al signal pr ocessor s. At t his point , t he image can be
manipulat ed in t he digit al domain t o per for m such funct ions as cont r ast or color
enhancement /cor r ect ion, et c.
The building blocks of a CCD ar e t he individual light sensing element s called pixels
(see Figur e 5.35). A single pixel consist s of a phot o sensit ive element , such as a
phot odiode or phot ocapacit or , which out put s a char ge (elect r ons) pr opor t ional t o t he
light (phot ons) t hat it is exposed t o. The char ge is accumulat ed dur ing t he exposur e
or int egr at ion t ime, and t hen t he char ge is t r ansfer r ed t o t he CCD shift r egist er t o
be sent t o t he out put of t he device. The amount of accumulat ed char ge will depend
on t he light level, t he int egr at ion t ime, and t he quant um efficiency of t he phot o
sensit ive element . A small amount of char ge will accumulat e even wit hout light
pr esent ; t his is called dar k signal or dar k cur r ent and must be compensat ed for
dur ing t he signal pr ocessing.
The pixels can be ar r anged in a linear or ar ea configur at ion as shown in Figur e 5.36.
Clock signals t r ansfer t he char ge fr om t he pixels int o t he analog shift r egist er s, and
t hen mor e clocks ar e applied t o shift t he individual pixel char ges t o t he out put st age
5.32
of t he CCD. Scanner s gener ally use t he linear configur at ion, while digit al camer as
use t he ar ea configur at ion. The analog shift r egist er t ypically oper at es at
fr equencies bet ween 1 and 10MHz for linear sensor s, and 5 t o 25MHz for ar ea
sensor s.
GENERIC IMAGING SYSTEM FOR
SCANNERS OR DIGITAL CAMERAS
LIGHT
LENS
IMAGING
SENSOR
(CCD, CIS, CMOS)
ANALOG
SIGNAL
CONDITIONING
ADC
DIGITAL
SIGNAL
PROCESSING
SCENE
DIGITIZED IMAGE
Figure 5.34
LIGHT SENSING ELEMENT
PHOTO SENSITIVE
ELEMENT
POTENTIAL WELL
LIGHT (PHOTONS)
ACCUMULATED CHARGE (ELECTRONS)
e
e
e e
e
e
e e
e
e
e e
ONE PHOTOSITE OR "PIXEL"
Figure 5.35
5.33
LINEAR AND AREA CCD ARRAYS
LINEAR CCD CONFIGURATION
VERTICAL
SHIFT
REGISTERS
PIXELS
AREA CCD CONFIGURATION
OUTPUT
STAGE
PHOTOSITES (PIXELS)
HORIZONTAL SHIFT REGISTER
OUTPUT
STAGE
HORIZONTAL SHIFT REGISTER
Figure 5.36
A t ypical CCD out put st age is shown in Figur e 5.37 along wit h t he associat ed
volt age wavefor ms. The out put st age of t he CCD conver t s t he char ge of each pixel t o
a volt age via t he sense capacit or , C
S
. At t he st ar t of each pixel per iod, t he volt age on
C
S
is r eset t o t he r efer ence level, V
REF
causing a r eset glit ch t o occur . The amount
of light sensed by each pixel is measur ed by t he differ ence bet ween t he r efer ence
and t he video level, V. CCD char ges may be as low as 10 elect r ons, and a t ypical
CCD out put has a sensit ivit y of 0.6V/elect r on. Most CCDs have a sat ur at ion out put
volt age of about 500mV t o 1V for ar ea sensor s and 2V t o 4V for linear sensor s. The
DC level of t he wavefor m is bet ween 3 t o 7V.
Since CCDs ar e gener ally fabr icat ed on CMOS pr ocesses, t hey have limit ed
capabilit y t o per for m on-chip signal condit ioning. Ther efor e t he CCD out put is
gener ally pr ocessed by ext er nal condit ioning cir cuit s. The nat ur e of t he CCD out put
r equir es t hat it be clamped befor e being digit ized by t he ADC. In addit ion, offset and
gain funct ions ar e gener ally par t of t he analog signal pr ocessing.
CCD out put volt ages ar e small and quit e oft en bur ied in noise. The lar gest sour ce of
noise is t he t her mal noise in t he r esist ance of t he FET r eset swit ch. This noise may
have a t ypical value of 100 t o 300 elect r ons r ms (appr oximat ely 60 t o 180mV r ms).
This noise, called "kT/C" noise, is illust r at ed in Figur e 5.38. Dur ing t he r eset
int er val, t he st or age capacit or C
S
is connect ed t o V
REF
via a CMOS swit ch. The on-
r esist ance of t he swit ch (R
ON
) pr oduces t her mal noise given by t he well known
equat ion:
Ther mal Noise = 4kT BW R
ON
.
5.34
The noise occur s over a finit e bandwidt h det er mined by t he R
ON
C
S
t ime const ant .
This bandwidt h is t hen conver t ed int o equivalent noise bandwidt h by mult iplying
t he single-pole bandwidt h by /2 (1.57):
Noise BW =
2
1
2
1
4 R
ON
C
S
R
ON
C
S
]
]
]
.
Subst it ut ing int o t he for mula for t he t her mal noise, not e t hat t he R
ON
fact or
cancels, and t he final expr ession for t he t her mal noise becomes:
Ther mal Noise =
kT
C
.
This is somewhat int uit ive, because smaller values of R
ON
decr ease t he t her mal
noise but incr ease t he noise bandwidt h, so only t he capacit or value det er mines t he
noise.
Not e t hat when t he r eset swit ch opens, t he kT/C noise is st or ed on C
S
and r emains
const ant unt il t he next r eset int er val. It t her efor e occur s as a sample-to-sample
var iat ion in t he CCD out put level and is common t o bot h t he r eset level and t he
video level for a given pixel per iod.
OUTPUT STAGE AND WAVEFORMS
V
REF
C
S
R
L
+V
S
RESET
PIXEL CHARGE, Q
FROM HORIZONTAL
SHIFT REGISTER
SENSE
CAPACITOR
BUFFER
CCD OUTPUT
VOLTAGE
PIXEL PERIOD
REFERENCE
LEVEL
VIDEO
LEVEL
RESET
GLITCH
V
RESET
SWITCH
=
Q
C
S
V 1V TO 4V FS
DC LEVEL 3V TO 7V
V
Figure 5.37
5.35
kT/C NOISE
V
REF
RESET
SWITCH
R
ON
C
S
Q
THERMAL NOISE = 4kTBWR
ON
NOISE BW =

2
1
2 R
ON
C
S
=
1
4 R
ON
C
S
THERMAL NOISE =
kT
C
S
SAME VALUE PRESENT DURING
REFERENCE AND VIDEO LEVELS
WHILE RESET SWITCH IS OPEN
Figure 5.38
A t echnique called correlated double sampling (CDS) is oft en used t o r educe t he
effect of t his noise. Figur e 5.39 shows one cir cuit implement at ion of t he CDS
scheme, t hough many ot her implement at ions exist . The CCD out put dr ives bot h
SHAs. At t he end of t he r eset int er val, SHA1 holds t he r eset volt age level plus t he
kT/C noise. At t he end of t he video int er val, SHA2 holds t he video level plus t he
kT/C noise. The SHA out put s ar e applied t o a differ ence amplifier which subt r act s
one fr om t he ot her . In t his scheme, t her e is only a shor t int er val dur ing which bot h
SHA out put s ar e st able, and t heir differ ence r epr esent s V, so t he differ ence
amplifier must set t le quickly. Not e t hat t he final out put is simply t he differ ence
bet ween t he r efer ence level and t he video level, V, and t hat t he kT/C noise is
r emoved.
Cont act Image Sensor s (CIS) ar e linear sensor s oft en used in facsimile machines and
low-end document scanner s inst ead of CCDs. Alt hough a CIS does not offer t he same
pot ent ial image qualit y as a CCD, it does offer lower cost and a mor e simplified
opt ical pat h. The out put of a CIS is similar t o t he CCD out put except t hat it is
r efer enced t o or near gr ound (see Figur e 5.40), eliminat ing t he need for a clamping
funct ion. Fur t her mor e, t he CIS out put does not cont ain cor r elat ed r eset noise wit hin
each pixel per iod, eliminat ing t he need for a CDS funct ion. Typical CIS out put
volt ages r ange fr om a few hundr ed mV t o about 1V fullscale. Not e t hat alt hough a
clamp and CDS is not r equir ed, t he CIS wavefor m must be sampled by a sample-
and-hold befor e digit izat ion.
5.36
CORRELATED DOUBLE SAMPLING (CDS)
SHA 1
SHA 2
+
_
REFERENCE CLOCK
VIDEO CLOCK
OUTPUT
REFERENCE + NOISE
VIDEO + NOISE
CCD
OUTPUT
OUTPUT = V =
REFERENCE VIDEO
Figure 5.39
CONTACT IMAGE SENSOR (CIS) WAVEFORMS
0 V
LINE
START
PULSE
CIS CLOCK
CIS OUTPUT
SAMPLE COMMAND
1V FS
Figure 5.40
Analog Devices offer s sever al analog-front-end (AFE) int egr at ed solut ions for t he
scanner , digit al camer a, and camcor der mar ket s. They all compr ise t he signal
pr ocessing st eps descr ibed above. Advances in pr ocess t echnology and cir cuit
t opologies have made t his level of int egr at ion possible in foundr y CMOS wit hout
sacr ificing per for mance. By combining successful ADC ar chit ect ur es wit h high
per for mance CMOS analog cir cuit r y, it is possible t o design complet e low cost
CCD/CIS signal pr ocessing ICs.
5.37
The AD9816 int egr at es an analog-fr ont -end (AFE) t hat int egr at es a 12-bit , 6MSPS
ADC wit h t he analog cir cuit r y needed for t hr ee-channel (RGB) image pr ocessing and
sampling (see Figur e 5.41). The AD9816 can be pr ogr ammed t hr ough a ser ial
int er face, and includes offset and gain adjust ment s t hat gives user s t he flexibilit y t o
per for m all t he signal pr ocessing necessar y for applicat ions such as mid- t o high-end
deskt op scanner s, digit al st ill camer as, medical x-r ays, secur it y camer as, and any
inst r ument at ion applicat ions t hat must "r ead" images fr om CIS or CCD sensor s.
The signal chain of t he AD9816 consist s of an input clamp, cor r elat ed double
sampler (CDS), offset adjust DAC, pr ogr ammable gain amplifier (PGA), and t he 12-
bit ADC cor e wit h ser ial int er facing t o t he ext er nal DSP. The CDS and clamp
funct ions can be disabled for CIS applicat ions.
The AD9814, Analog Devices' lat est AFE pr oduct , t akes t he level of per for mance a
st ep higher . For t he most demanding applicat ions, t he AD9814 offer s t he same basic
funct ionalit y as t he AD9816 but wit h 14-bit per for mance. As wit h t he AD9816, t he
signal pat h includes t hr ee input channels, each wit h input clamping, CDS, offset
adjust ment , and pr ogr ammable gain. The t hr ee channels ar e mult iplexed int o a
high per for mance 14-bit 6MSPS ADC. High-end document and film scanner s can
benefit fr om t he AD9814's combinat ion of per for mance and int egr at ion.
AD9816 ANALOG FRONT END CCD/CIS PROCESSOR
DAC
DAC
DAC
+
+
+
MUX
12-BIT
ADC
BANDGAP
REFERENCE
DIGITAL
CONTROL
PORT
MUX
REGISTER
CONFIG.
REGISTER
R
G
B
R
G
B
CLAMP/CDS
CLAMP/CDS
CLAMP/CDS
AVDD AVSS CAPT CAPB CML PGAOUT VREF DVDD DVSS DRVDD DRVSS
DOUT
SCLK
SLOAD
SDATA
CDSCLK1 CDSCLK2 ADCCLK
VINR
VING
VINB
OFFSET
12
8
8
PGA
PGA
PGA
OFFSET
REGISTERS
GAIN
REGISTERS
0-15dB
100mV
OEB
Figure 5.41
5.38
AD9816 KEY SPECIFICATIONS
n Complete 12-Bit 6MSPS CCD/CIS Signal Processor
n 3-Channel or 1-Channel Operation
n On-Chip Correlated Double Sampling (CDS)
n 8-Bit Programmable Gain and 8-Bit Offset Adjustment
n Internal Voltage Reference
n Good Linearity: DNL = 0.4LSB Typical, INL = 1.5 LSB Typical
n Low Output Noise: 0.5 LSB RMS
n Coarse Offset Removal for CIS Applications
n 3-Wire Serial Interface
n Single +5V Supply, 420mW Power Dissipation
n 44-Lead MQFP Package
Figure 5.42
5.39
REFERENCES
3. Walt Kest er , Edit or , 1992 Amp li fi er Ap p li ca t i on s Gu i d e, Sect ion 3,
4. Walt Kest er , Edit or , Syst em Ap p li ca t i on s Gu i d e, Analog Devices, Inc.,
1993.
5. Walt Kest er , Edit or , Li n ea r Desi gn Semi n a r , Analog Devices, 1994.
6. Walt Kest er , Edit or , P r a ct i ca l An a log Desi gn Tech n i qu es,
Analog Devices,1994.
7. Walt Kest er , Edit or , Hi gh Sp eed Desi gn Tech n i qu es, Analog Devices,
1996.
8. Thomas M. Fr edr ickson, I n t u i t i ve Op er a t i on a l Amp li fi er s,
McGr aw-Hill, 1988.
9. Op t oelect r on i cs Da t a Book , EG&G Vact ec, St . Louis, MO, 1990.
10. Silicon Det ect or Cor por at ion, Camar illo, CA, Par t Number SD-020-12-001
Dat a Sheet .
11. P h ot od i od e 1991 Ca t a log, Hamamat su Phot onics, Br idgewat er , NJ
12. An Introduction to the Imaging CCD Array, Technical Not e 82W-4022,
Tekt r onix, Inc., Beaver t on, OR., 1987.
13. Lewis Smit h and Dan Sheingold, Noise and Operational Amplifier
Circuits, An a log Di a logu e 25t h An n i ver sa r y I ssu e, pp. 19-31,
Analog Devices, 1991.
14. J ames L. Melsa and Donald G. Schult z, Li n ea r Con t r ol Syst ems,
pp. 196-220, McGr aw-Hill, 1969.
5.40
15. J er ald G. Gr aeme, P h ot od i od e Amp li fi er s: Op Amp Solu t i on s,
McGr aw-Hill, 1995.
16. Er ik Bar nes, High Integration S implifies S ignal Processing for CCDs,
Elect r on i c Desi gn , Febr uar y 23, 1998, pp. 81-88.
17. Er ic Bar nes, Integrated for CCD S ignal Processing, An a log Di a logu e
32-1, Analog Devices, 1998.
18. Pr ecision Resist or Co., Inc., 10601 75t h St . N., Lar go, FLA,
33777-1427, 727-541-5771, ht t p://www.pr ecisionr esist or .com.
P OSI TI ON AND MOTI ON SENSORS
6.1
SECTI ON 6
Wa l t Kest er
Moder n linear and digit al int egr at ed cir cuit t echnology is used t hr oughout t he field
of posit ion and mot ion sensing. Fully int egr at ed solut ions which combine linear and
digit al funct ions have r esult ed in cost effect ive solut ions t o pr oblems which in t he
past have been solved using expensive elect r o-mechanical t echniques. These syst ems
ar e used in many applicat ions including r obot ics, comput er -aided manufact ur ing,
fact or y aut omat ion, avionics, and aut omot ive.
This sect ion is an over view of linear and r ot ar y posit ion sensor s and t heir associat ed
condit ioning cir cuit s. An int er est ing applicat ion of mixed-signal IC int egr at ion is
illust r at ed in t he field of AC mot or cont r ol. A discussion of micr omachined
acceler omet er s ends t he sect ion.
POSITION AND MOTION SENSORS
n Linear Position: Linear Variable Differential Transformers (LVDT)
n Hall Effect Sensors
u Proximity Detectors
u Linear Output (Magnetic Field Strength)
n Rotational Position:
u Rotary Variable Differential Transformers (RVDT)
u Optical Rotational Encoders
u Synchros and Resolvers
u Inductosyns (Linear and Rotational Position)
u Motor Control Applications
n Acceleration and Tilt: Accelerometers
Figure 6.1
LI NEAR VARI ABLE DI FFERENTI AL TRANSFORMERS
(LVDTS)
The linear var iable differ ent ial t r ansfor mer (LVDT) is an accur at e and r eliable
met hod for measur ing linear dist ance. LVDTs find uses in moder n machine-t ool,
r obot ics, avionics, and comput er ized manufact ur ing. By t he end of Wor ld War II, t he
LVDT had gained accept ance as a sensor element in t he pr ocess cont r ol indust r y
lar gely as a r esult of it s use in air cr aft , t or pedo, and weapons syst ems. The
publicat ion of The Linear Variable Differential Transformer by Her man Schaevit z in
6.2
1946 (Pr oceedings of t he SASE, Volume IV, No. 2) made t he user communit y at
lar ge awar e of t he applicat ions and feat ur es of t he LVDT.
The LVDT (see Figur e 6.2) is a posit ion-t o-elect r ical sensor whose out put is
pr opor t ional t o t he posit ion of a movable magnet ic cor e. The cor e moves linear ly
inside a t r ansfor mer consist ing of a cent er pr imar y coil and t wo out er secondar y coils
wound on a cylindr ical for m. The pr imar y winding is excit ed wit h an AC volt age
sour ce (t ypically sever al kHz), inducing secondar y volt ages which var y wit h t he
posit ion of t he magnet ic cor e wit hin t he assembly. The cor e is usually t hr eaded in
or der t o facilit at e at t achment t o a nonfer r omagnet ic r od which in t ur n in at t ached t o
t he object whose movement or displacement is being measur ed.
LINEAR VARIABLE DIFFERENTIAL TRANSFORMER (LVDT)
~
AC
SOURCE
V
OUT
= V
A
V
B
+
_
V
OUT
POSITION
+
_
V
OUT
POSITION
+
_
V
A
V
B
1.75"
THREADED
CORE
SCHAEVITZ
E100
Figure 6.2
The secondar y windings ar e wound out of phase wit h each ot her , and when t he cor e
is cent er ed t he volt ages in t he t wo secondar y windings oppose each ot her , and t he
net out put volt age is zer o. When t he cor e is moved off cent er , t he volt age in t he
secondar y t owar d which t he cor e is moved incr eases, while t he opposit e volt age
decr eases. The r esult is a differ ent ial volt age out put which var ies linear ly wit h t he
cor e's posit ion. Linear it y is excellent over t he design r ange of movement , t ypically
0.5% or bet t er . The LVDT offer s good accur acy, linear it y, sensit ivit y, infinit e
r esolut ion, as well as fr ict ionless oper at ion and r uggedness.
A wide var iet y of measur ement r anges ar e available in differ ent LVDTs, t ypically
fr om 100m t o 25cm. Typical excit at ion volt ages r ange fr om 1V t o 24V RMS, wit h
fr equencies fr om 50Hz t o 20kHz. Key specificat ions for t he Schaevit z E100 LVDT
ar e given in Figur e 6.3.
6.3
SCHAEVITZ E100 LVDT SPECIFICATIONS
n Nominal Linear Range: 0.1 inches ( 2.54mm)
n Input Voltage: 3V RMS
n Operating Frequency: 50Hz to 10kHz (2.5kHz nominal)
n Linearity: 0.5% Fullscale
n Sensitivity: 2.4mV Output / 0.001in / Volt Excitation
n Primary Impedance: 660
n Secondary Impedance: 960
Figure 6.3
Not e t hat a t r ue null does not occur when t he cor e is in cent er posit ion because of
mismat ches bet ween t he t wo secondar y windings and leakage induct ance. Also,
simply measur ing t he out put volt age V
OUT
will not t ell on which side of t he null
posit ion t he cor e r esides.
A signal condit ioning cir cuit which r emoves t hese difficult ies is shown in Figur e 6.4
wher e t he absolut e values of t he t wo out put volt ages ar e subt r act ed. Using t his
t echnique, bot h posit ive and negat ive var iat ions about t he cent er posit ion can be
measur ed. While a diode/capacit or -t ype r ect ifier could be used as t he absolut e value
cir cuit , t he pr ecision r ect ifier shown in Figur e 6.5 is mor e accur at e and linear . The
input is applied t o a V/I conver t er which in t ur n dr ives an analog mult iplier . The
sign of t he differ ent ial input is det ect ed by t he compar at or whose out put swit ches
t he sign of t he V/I out put via t he analog mult iplier . The final out put is a pr ecision
r eplica of t he absolut e value of t he input . These cir cuit s ar e well under st ood by IC
designer s and ar e easy t o implement on moder n bipolar pr ocesses.
The indust r y-st andar d AD598 LVDT signal condit ioner shown in Figur e 6.6
(simplified for m) per for ms all r equir ed LVDT signal pr ocessing. The on-chip
excit at ion fr equency oscillat or can be set fr om 20Hz t o 20kHz wit h a single ext er nal
capacit or . Two absolut e value cir cuit s followed by t wo filt er s ar e used t o det ect t he
amplit ude of t he A and B channel input s. Analog cir cuit s ar e t hen used t o gener at e
t he r at iomet r ic funct ion [AB]/[A+B]. Not e t hat t his funct ion is independent of t he
amplit ude of t he pr imar y winding excit at ion volt age, assuming t he sum of t he LVDT
out put volt age amplit udes r emains const ant over t he oper at ing r ange. This is
usually t he case for most LVDTs, but t he user should always check wit h t he
manufact ur er if it is not specified on t he LVDT dat a sheet . Not e also t hat t his
appr oach r equir es t he use of a 5-wir e LVDT.
6.4
IMPROVED LVDT OUTPUT SIGNAL PROCESSING
~
AC
SOURCE
+
ABSOLUTE
VALUE
ABSOLUTE
VALUE
FILTER
FILTER
+
_
V
OUT
_
POSITION +
_
V
OUT +
_
LVDT
Figure 6.4
PRECISION ABSOLUTE VALUE CIRCUIT
(FULL-WAVE RECTIFIER)
V / I
+
+
_
_
1
COMPARATOR
gm STAGE
MULTIPLIER
INPUT
OUTPUT
Figure 6.5
6.5
AD598 LVDT SIGNAL CONDITIONER (SIMPLIFIED)
AMP
~
+
_
A B
A + B
ABS
VALUE
FILTER
ABS
VALUE
FILTER
FILTER AMP

V
A
V
B
V
OUT
AD598
EXCITATION
5-WIRE LVDT
OSCILLATOR
Figure 6.6
A single ext er nal r esist or set s t he AD598 excit at ion volt age fr om appr oximat ely 1V
RMS t o 24V RMS. Dr ive capabilit y is 30mA RMS. The AD598 can dr ive an LVDT at
t he end of 300 feet of cable, since t he cir cuit is not affect ed by phase shift s or
absolut e signal magnit udes. The posit ion out put r ange of V
OUT
is 11V for a 6mA
load and it can dr ive up t o 1000 feet of cable. The V
A
and V
B
input s can be as low as
100mV RMS.
The AD698 LVDT signal condit ioner (see Figur e 6.7) has similar specificat ions as
t he AD598 but pr ocesses t he signals slight ly differ ent ly. Not e t hat t he AD698
oper at es fr om a 4-wir e LVDT and uses synchr onous demodulat ion. The A and B
signal pr ocessor s each consist of an absolut e value funct ion and a filt er . The A
out put is t hen divided by t he B out put t o pr oduce a final out put which is r at iomet r ic
and independent of t he excit at ion volt age amplit ude. Not e t hat t he sum of t he LVDT
secondar y volt ages does not have t o r emain const ant in t he AD698.
The AD698 can also be used wit h a half-br idge (similar t o an aut o-t r ansfor mer )
LVDT as shown in Figur e 6.8. In t his ar r angement , t he ent ir e secondar y volt age is
applied t o t he B pr ocessor , while t he cent er -t ap volt age is applied t o t he A pr ocessor .
The half-br idge LVDT does not pr oduce a null volt age, and t he A/B r at io r epr esent s
t he r ange-of-t r avel of t he cor e.
6.6
A
B
AD698 LVDT SIGNAL CONDITIONER (SIMPLIFIED)
AMP
~
+
_
FILTER AMP
V
B
V
OUT
AD698
EXCITATION
4-WIRE LVDT
OSCILLATOR
A
B

V
A
REFERENCE
A, B = ABSOLUTE VALUE + FILTER
Figure 6.7
HALF-BRIDGE LVDT CONFIGURATION
A
B
AMP
~
+
_
FILTER AMP
V
OUT
AD698
EXCITATION
HALF BRIDGE LVDT
OSCILLATOR
A
B

REFERENCE
A, B = ABSOLUTE VALUE + FILTER

Figure 6.8
6.7
It should be not ed t hat t he LVDT concept can be implement ed in r ot ar y for m, in
which case t he device is called a rotary variable differential transformer (RVDT). The
shaft is equivalent t o t he cor e in an LVDT, and t he t r ansfor mer windings ar e wound
on t he st at ionar y par t of t he assembly. However , t he RVDT is linear over a
r elat ively nar r ow r ange of r ot at ion and is not capable of measur ing a full 360
r ot at ion. Alt hough capable of cont inuous r ot at ion, t ypical RVDTs ar e linear over a
r ange of about 40 about t he null posit ion (0). Typical sensit ivit y is 2 t o 3mV per
volt per degr ee of r ot at ion, wit h input volt ages in t he r ange of 3V RMS at
fr equencies bet ween 400Hz and 20kHz. The 0 posit ion is mar ked on t he shaft and
t he body.
HALL EFFECT MAGNETI C SENSORS
If a cur r ent flows in a conduct or (or semiconduct or ) and t her e is a magnet ic field
pr esent which is per pendicular t o t he cur r ent flow, t hen t he combinat ion of cur r ent
and magnet ic field will gener at e a volt age per pendicular t o bot h (see Figur e 6.9).
This phenomenon is called t he Hall Effect, was discover ed by E. H. Hall in 1879. The
volt age, V
H
, is known as t he Hall Voltage. V
H
is a funct ion of t he cur r ent densit y,
t he magnet ic field, and t he char ge densit y and car r ier mobilit y of t he conduct or .
HALL EFFECT SENSORS
I I
T
B
V
H
CONDUCTOR
OR
SEMICONDUCTOR
I = CURRENT
B = MAGNETIC FIELD
T = THICKNESS
V
H
= HALL VOLTAGE
Figure 6.9
The Hall effect may be used t o measur e magnet ic fields (and hence in cont act -fr ee
cur r ent measur ement ), but it s commonest applicat ion is in mot ion sensor s wher e a
fixed Hall sensor and a small magnet at t ached t o a moving par t can r eplace a cam
and cont act s wit h a gr eat impr ovement in r eliabilit y. (Cams wear and cont act s ar c
or become fouled, but magnet s and Hall sensor s ar e cont act fr ee and do neit her .)
Since V
H
is pr opor t ional t o magnet ic field and not t o r at e of change of magnet ic field
6.8
like an induct ive sensor , t he Hall Effect pr ovides a mor e r eliable low speed sensor
t han an induct ive pickup.
Alt hough sever al mat er ials can be used for Hall effect sensor s, silicon has t he
advant age t hat signal condit ioning cir cuit s can be int egr at ed on t he same chip as
t he sensor . CMOS pr ocesses ar e common for t his applicat ion. A simple r ot at ional
speed det ect or can be made wit h a Hall sensor , a gain st age, and a compar at or as
shown in Figur e 6.10. The cir cuit is designed t o det ect r ot at ion speed as in
aut omot ive applicat ions. It r esponds t o small changes in field, and t he compar at or
has built -in hyst er esis t o pr event oscillat ion. Sever al companies manufact ur e such
Hall swit ches, and t heir usage is widespr ead.
HALL EFFECT SENSOR USED AS A ROTATION SENSOR
HALL
CELL
B
I
+
_
V
H
V
THRESHOLD
COMPARATOR
WITH
HYSTERESIS
GAIN
MAGNETS
ROTATION
V
OUT
Figure 6.10
Ther e ar e many ot her applicat ions, par t icular ly in aut omot ive t hr ot t le, pedal,
suspension, and valve posit ion sensing, wher e a linear r epr esent at ion of t he
magnet ic field is desir ed. The AD22151 is a linear magnet ic field sensor whose
out put volt age is pr opor t ional t o a magnet ic field applied per pendicular ly t o t he
package t op sur face (see Figur e 6.11). The AD22151 combines int egr at ed bulk Hall
cell t echnology and condit ioning cir cuit r y t o minimize t emper at ur e r elat ed dr ift s
associat ed wit h silicon Hall cell char act er ist ics.
The ar chit ect ur e maximizes t he advant ages of a monolit hic implement at ion while
allowing sufficient ver sat ilit y t o meet var ied applicat ion r equir ement s wit h a
minimum number of ext er nal component s. Pr incipal feat ur es include dynamic offset
dr ift cancellat ion using a chopper -t ype op amp and a built -in t emper at ur e sensor .
Designed for single +5V supply oper at ion, low offset and gain dr ift allows oper at ion
over a 40C t o +150C r ange. Temper at ur e compensat ion (set ext er nally wit h a
r esist or R1) can accommodat e a number of magnet ic mat er ials commonly ut ilized in
posit ion sensor s. Out put volt age r ange and gain can be easily set wit h ext er nal
r esist or s. Typical gain r ange is usually set fr om 2mV/Gauss t o 6mV/Gauss. Out put
volt age can be adjust ed fr om fully bipolar (r ever sible) field oper at ion t o fully
6.9
unipolar field sensing. The volt age out put achieves near r ail-t o-r ail dynamic r ange
(+0.5V t o +4.5V), capable of supplying 1mA int o lar ge capacit ive loads. The out put
signal is r at iomet r ic t o t he posit ive supply r ail in all configur at ions.
AD22151 LINEAR OUTPUT MAGNETIC FIELD SENSOR
_
+
CHOPPER
AMP
V
CC
/ 2
R1
R2
R3
OUTPUT
AMP
V
CC
= +5V
V
CC
/ 2
TEMP
REF
+
_
V
OUT
= 1 +
R3
R2
0.4mV Gauss NONLINEARITY = 0.1% FS
AD22151
V
OUT
Figure 6.11
OP TI CAL ENCODERS
Among t he most popular posit ion measur ing sensor s, opt ical encoder s find use in
r elat ively low r eliabilit y and low r esolut ion applicat ions. An incremental opt ical
encoder (left -hand diagr am in Figur e 6.12) is a disc divided int o sect or s t hat ar e
alt er nat ely t r anspar ent and opaque. A light sour ce is posit ioned on one side of t he
disc, and a light sensor on t he ot her side. As t he disc r ot at es, t he out put fr om t he
det ect or swit ches alt er nat ely on and off, depending on whet her t he sect or appear ing
bet ween t he light sour ce and t he det ect or is t r anspar ent or opaque. Thus, t he
encoder pr oduces a st r eam of squar e wave pulses which, when count ed, indicat e t he
angular posit ion of t he shaft . Available encoder r esolut ions (t he number of opaque
and t r anspar ent sect or s per disc) r ange fr om 100 t o 65,000, wit h absolut e accur acies
appr oaching 30 ar c-seconds (1/43,200 per r ot at ion). Most incr ement al encoder s
feat ur e a second light sour ce and sensor at an angle t o t he main sour ce and sensor ,
t o indicat e t he dir ect ion of r ot at ion. Many encoder s also have a t hir d light sour ce
and det ect or t o sense a once-per -r evolut ion mar ker . Wit hout some for m of r evolut ion
mar ker , absolut e angles ar e difficult t o det er mine. A pot ent ially ser ious
disadvant age is t hat incr ement al encoder s r equir e ext er nal count er s t o det er mine
absolut e angles wit hin a given r ot at ion. If t he power is moment ar ily shut off, or if
t he encoder misses a pulse due t o noise or a dir t y disc, t he r esult ing angular
infor mat ion will be in er r or .
6.10
INCREMENTAL AND ABSOLUTE OPTICAL ENCODERS
LIGHT
SOURCES
SENSORS
CONDITIONING
ELECTRONICS
SHAFT
DISC
LIGHT
SOURCES
SENSORS
CONDITIONING
ELECTRONICS
DISC
5 BITS
SHAFT
INCREMENTAL
ABSOLUTE
5 BITS

Figure 6.12
The absolute opt ical encoder (r ight -hand diagr am in Figur e 6.12) over comes t hese
disadvant ages but is mor e expensive. An absolut e opt ical encoder 's disc is divided up
int o N sect or s (N = 5 for example shown), and each sect or is fur t her divided r adially
along it s lengt h int o opaque and t r anspar ent sect ions, for ming a unique N-bit digit al
wor d wit h a maximum count of 2
N
1. The digit al wor d for med r adially by each
sect or incr ement s in value fr om one sect or t o t he next , usually employing Gr ay code.
Binar y coding could be used, but can pr oduce lar ge er r or s if a single bit is incor r ect ly
int er pr et ed by t he sensor s. Gr ay code over comes t his defect : t he maximum er r or
pr oduced by an er r or in any single bit of t he Gr ay code is only
1 LSB aft er t he Gr ay code is conver t ed int o binar y code. A set of N light sensor s
r esponds t o t he N-bit digit al wor d which cor r esponds t o t he disc's absolut e angular
posit ion. Indust r ial opt ical encoder s achieve up t o 16-bit r esolut ion, wit h absolut e
accur acies t hat appr oach t he r esolut ion (20 ar c seconds). Bot h absolut e and
incr ement al opt ical encoder s, however , may suffer damage in har sh indust r ial
envir onment s.
RESOLVERS AND SYNCHROS
Machine-t ool and r obot ics manufact ur er s have incr easingly t ur ned t o r esolver s and
synchr os t o pr ovide accur at e angular and r ot at ional infor mat ion. These devices excel
in demanding fact or y applicat ions r equir ing small size, long-t er m r eliabilit y,
absolut e posit ion measur ement , high accur acy, and low-noise oper at ion.
A diagr am of a t ypical synchr o and r esolver is shown in Figur e 6.13. Bot h sycnchr os
and r esolver s employ single-winding r ot or s t hat r evolve inside fixed st at or s. In t he
6.11
case of a simple synchr o, t he st at or has t hr ee windings or ient ed 120 apar t and
elect r ically connect ed in a Y-connect ion. Resolver s differ fr om synchr os in t hat t heir
st at or s have only t wo windings or ient ed at 90.
SYNCHROS AND RESOLVERS
R1
R2
S1
S2
S3
R1
R2
S1
S2
S3
S4
S1 TO S3 = V sin t sin
S3 TO S2 = V sin t sin ( + 120)
S2 TO S1 = V sin t sin ( + 240)
S1 TO S3 = V sin t sin
S4 TO S2 = V sin t sin ( + 90)
= V sin t cos
ROTOR
ROTOR
STATOR
STATOR
ROTOR
STATOR
SYNCHRO
RESOLVER
V sin t
V sin t

Figure 6.13
Because synchr os have t hr ee st at or coils in a 120 or ient at ion, t hey ar e mor e
difficult t han r esolver s t o manufact ur e and ar e t her efor e mor e cost ly. Today,
synchr os find decr easing use, except in cer t ain milit ar y and avionic r et r ofit
applicat ions.
Moder n r esolver s, in cont r ast , ar e available in a br ushless for m t hat employ a
t r ansfor mer t o couple t he r ot or signals fr om t he st at or t o t he r ot or . The pr imar y
winding of t his t r ansfor mer r esides on t he st at or , and t he secondar y on t he r ot or .
Ot her r esolver s use mor e t r adit ional br ushes or slip r ings t o couple t he signal int o
t he r ot or winding. Br ushless r esolver s ar e mor e r ugged t han synchr os because t her e
ar e no br ushes t o br eak or dislodge, and t he life of a br ushless r esolver is limit ed
only by it s bear ings. Most r esolver s ar e specified t o wor k over 2V t o 40V RMS and at
fr equencies fr om 400Hz t o 10kHz. Angular accur acies r ange fr om 5 ar c-minut es t o
0.5 ar c-minut es. (Ther e ar e 60 ar c-minut es in one degr ee, and 60 ar c-seconds in one
ar c-minut e. Hence, one ar c-minut e is equal t o 0.0167 degr ees).
In oper at ion, synchr os and r esolver s r esemble r ot at ing t r ansfor mer s. The r ot or
winding is excit ed by an AC r efer ence volt age, at fr equencies up t o a few kHz. The
magnit ude of t he volt age induced in any st at or winding is pr opor t ional t o t he sine of
t he angle, , bet ween t he r ot or coil axis and t he st at or coil axis. In t he case of a
synchr o, t he volt age induced acr oss any pair of st at or t er minals will be t he vect or
sum of t he volt ages acr oss t he t wo connect ed coils.
6.12
For example, if t he r ot or of a synchr o is excit ed wit h a r efer ence volt age, Vsint ,
acr oss it s t er minals R1 and R2, t hen t he st at or 's t er minal will see volt ages in t he
for m:
S1 t o S3 = V sint sin
S3 t o S2 = V sint sin ( + 120)
S2 t o S1 = V sint sin ( + 240),
wher e is t he shaft angle.
In t he case of a r esolver , wit h a r ot or AC r efer ence volt age of Vsint , t he st at or 's
t er minal volt ages will be:
S1 t o S3 = V sint sin
S4 t o S2 = V sint sin( + 90) = V sint cos.
It should be not ed t hat t he 3-wir e synchr o out put can be easily conver t ed int o t he
r esolver -equivalent for mat using a Scot t -T t r ansfor mer . Ther efor e, t he following
signal pr ocessing example descr ibes only t he r esolver configur at ion.
A t ypical r esolver -t o-digit al conver t er (RDC) is shown funct ionally in Figur e 6.14.
The t wo out put s of t he r esolver ar e applied t o cosine and sine mult iplier s. These
mult iplier s incor por at e sine and cosine lookup t ables and funct ion as mult iplying
digit al-t o-analog conver t er s. Begin by assuming t hat t he cur r ent st at e of t he
up/down count er is a digit al number r epr esent ing a t r ial angle, . The conver t er
seeks t o adjust t he digit al angle, , cont inuously t o become equal t o, and t o t r ack ,
t he analog angle being measur ed. The r esolver 's st at or out put volt ages ar e wr it t en
as:
V
1
= V sint sin
V
2
= V sint cos
wher e is t he angle of t he r esolver 's r ot or . The digit al angle is applied t o t he
cosine mult iplier , and it s cosine is mult iplied by V
1
t o pr oduce t he t er m:
V sint sin cos.
The digit al angle is also applied t o t he sine mult iplier and mult iplied by V
2
t o
pr oduct t he t er m:
V sint cos sin.
These t wo signals ar e subt r act ed fr om each ot her by t he er r or amplifier t o yield an
AC er r or signal of t he for m:
V sint [sin cos cos sin].
Using a simple t r igonomet r ic ident it y, t his r educes t o:
V sint [sin ( )].
6.13
The det ect or synchr onously demodulat es t his AC er r or signal, using t he r esolver 's
r ot or volt age as a r efer ence. This r esult s in a DC er r or signal pr opor t ional t o
sin().
The DC er r or signal feeds an int egr at or , t he out put of which dr ives a volt age-
cont r olled-oscillat or (VCO). The VCO, in t ur n, causes t he up/down count er t o count
in t he pr oper dir ect ion t o cause:
sin ( ) 0.
When t his is achieved,
0,
and t her efor e
=
t o wit hin one count . Hence, t he count er 's digit al out put , , r epr esent s t he angle .
The lat ches enable t his dat a t o be t r ansfer r ed ext er nally wit hout int er r upt ing t he
loop's t r acking.
RESOLVER-TO-DIGITAL CONVERTER (RTD)
COSINE
MULTIPLIER
SINE
MULTIPLIER
DETECTOR
INTEGRATOR
UP / DOWN
COUNTER
VCO
V sin t sin
V sin t cos
V sin t sin cos
V sin t cos sin
_
+
V sin t [sin ( )]
ERROR
V sin t ROTOR REFERENCE
STATOR
INPUTS
LATCHES
K sin ( )

= DIGITAL ANGLE

VELOCITY
WHEN ERROR = 0,
= 1 LSB

Figure 6.14
6.14
This cir cuit is equivalent t o a so-called t ype-2 ser vo loop, because it has, in effect ,
t wo int egr at or s. One is t he count er , which accumulat es pulses; t he ot her is t he
int egr at or at t he out put of t he det ect or . In a t ype-2 ser vo loop wit h a const ant
r ot at ional velocit y input , t he out put digit al wor d cont inuously follows, or t r acks t he
input , wit hout needing ext er nally der ived conver t commands, and wit h no st eady
st at e phase lag bet ween t he digit al out put wor d and act ual shaft angle. An er r or
signal appear s only dur ing per iods of acceler at ion or deceler at ion.
As an added bonus, t he t r acking RDC pr ovides an analog DC out put volt age dir ect ly
pr opor t ional t o t he shaft 's r ot at ional velocit y. This is a useful feat ur e if velocit y is t o
be measur ed or used as a st abilizat ion t er m in a ser vo syst em, and it makes
t achomet er s unnecessar y.
Since t he oper at ion of an RDC depends only on t he r at io bet ween input signal
amplit udes, at t enuat ion in t he lines connect ing t hem t o r esolver s doesn't
subst ant ially affect per for mance. For similar r easons, t hese conver t er s ar e not
gr eat ly suscept ible t o wavefor m dist or t ion. In fact , t hey can oper at e wit h as much as
10% har monic dist or t ion on t he input signals; some applicat ions act ually use squar e-
wave r efer ences wit h lit t le addit ional er r or .
Tr acking ADCs ar e t her efor e ideally suit ed t o RDCs. While ot her ADC ar chit ect ur es,
such as successive appr oximat ion, could be used, t he t r acking conver t er is t he most
accur at e and efficient for t his applicat ion.
Because t he t r acking conver t er doubly int egr at es it s er r or signal, t he device offer s a
high degr ee of noise immunit y (12 dB-per -oct ave r olloff). The net ar ea under any
given noise spike pr oduces an er r or . However , t ypical induct ively coupled noise
spikes have equal posit ive and negat ive going wavefor ms. When int egr at ed, t his
r esult s in a zer o net er r or signal. The r esult ing noise immunit y, combined wit h t he
conver t er 's insensit ivit y t o volt age dr ops, let s t he user locat e t he conver t er at a
consider able dist ance fr om t he r esolver . Noise r eject ion is fur t her enhanced by t he
det ect or 's r eject ion of any signal not at t he r efer ence fr equency, such as wideband
noise.
The AD2S90 is one of a number of int egr at ed RDCs offer ed by Analog Devices. Key
specificat ions ar e shown in Figur e 6.15. The gener al ar chit ect ur e is similar t o t hat of
Figur e 6.14. The input signal level should be 2V RMS 10% in t he fr equency r ange
fr om 3kHz t o 20kHz.
6.15
PERFORMANCE CHARACTERISTICS FOR
AD2S90 RESOLVER-TO-DIGITAL CONVERTER
n 12-Bit Resolution (1 LSB = 0.08= 5.3 arc min)
n Inputs: 2V RMS 10%, 3kHz to 20kHz
n Angular Accuracy: 10.6 arc min 1 LSB
n Maximum Tracking Rate: 375 revolutions per second
n Maximum VCO Clock Rate: 1.536MHz
n Settling Time:
u 1Step: 7ms
u 179Step: 20ms
n Differential Inputs
n Serial Output Interface
n 5V Supplies, 50mW Power Dissipation
n 20 Pin PLCC
Figure 6.15
I NDUCTOSYNS
Synchr os and r esolver s inher ent ly measur e r ot ar y posit ion, but t hey can make
linear posit ion measur ement s when used wit h lead scr ews. An alt er nat ive, t he
Induct osyn (r egist er ed t r ademar k of Far r and Cont r ols, Inc.) measur es linear
posit ion dir ect ly. In addit ion, Induct osyns ar e accur at e and r ugged, well-suit ed t o
sever e indust r ial envir onment s, and do not r equir e ohmic cont act .
The linear Induct osyn consist s of t wo magnet ically coupled par t s; it r esembles a
mult ipole r esolver in it s oper at ion (see Figur e 6.16). One par t , t he scale, is fixed (e.g.
wit h epoxy) t o one axis, such as a machine t ool bed. The ot her par t , t he slider ,
moves along t he scale in conjunct ion wit h t he device t o be posit ioned (for example,
t he machine t ool car r ier ).
The scale is const r uct ed of a base mat er ial such as st eel, st ainless st eel, aluminum,
or a t ape of spr ing st eel, cover ed by an insulat ing layer . Bonded t o t his is a pr int ed-
cir cuit t r ace, in t he for m of a cont inuous r ect angular wavefor m pat t er n. The pat t er n
t ypically has a cyclic pit ch of 0.1 inch, 0.2 inch, or 2 millimet er s. The slider , about 4
inches long, has t wo separ at e but ident ical pr int ed cir cuit t r aces bonded t o t he
sur face t hat faces t he scale. These t wo t r aces have a wavefor m pat t er n wit h exact ly
t he same cyclic pit ch as t he wavefor m on t he scale, but one t r ace is shift ed one-
quar t er of a cycle r elat ive t o t he ot her . The slider and t he scale r emain separ at ed by
a small air gap of about 0.007 inch.
6.16
LINEAR INDUCTOSYN
SCALE
V sin t
V sin t sin
2 X
S
V sin t cos
2 X
S
SCALE
TRACES
SINE COSINE
SLIDER
TRACES
TWO WINDINGS SHIFTED
BY 1/4 PERIOD (90)
EXPANDED
S
SLIDER
X
Figure 6.16
Induct osyn oper at ion r esembles t hat of a r esolver . When t he scale is ener gized wit h
a sine wave, t his volt age couples t o t he t wo slider windings, inducing volt ages
pr opor t ional t o t he sine and cosine of t he slider 's spacing wit hin t he cyclic pit ch of
t he scale. If S is t he dist ance bet ween pit ches, and X is t he slider displacement
wit hin a pit ch, and t he scale is ener gized wit h a volt age V sint , t hen t he slider
windings will see t er minal volt ages of:
V (sine out put ) = V sint sin[2X/S]
V (cosine out put ) = V sint cos[2X/S].
As t he slider moves t he dist ance of t he scale pit ch, t he volt ages pr oduced by t he t wo
slider windings ar e similar t o t hose pr oduced by a r esolver r ot at ing t hr ough 360.
The absolut e or ient at ion of t he Induct osyn is det er mined by count ing successive
pit ches in eit her dir ect ion fr om an est ablished st ar t ing point . Because t he
Induct osyn consist s of a lar ge number of cycles, some for m of coar se cont r ol is
necessar y in or der t o avoid ambiguit y. The usual met hod of pr oviding t his is t o use a
r esolver or synchr o oper at ed t hr ough a r ack and pinion or a lead scr ew.
6.17
In cont r ast t o a r esolver 's highly efficient t r ansfor mat ion of 1:1 or 2:1, t ypical
Induct osyns oper at e wit h t r ansfor mat ion r at ios of 100:1. This r esult s in a pair of
sinusoidal out put signals in t he millivolt r ange which gener ally r equir e
amplificat ion.
Since t he slider out put signals ar e der ived fr om an aver age of sever al spat ial cycles,
small er r or s in conduct or spacing have minimal effect s. This is an impor t ant r eason
for t he Induct osyn's ver y high accur acy. In combinat ion wit h 12-bit RDCs, linear
Induct osyns r eadily achieve 25 micr oinch r esolut ions.
Rot ar y induct osyns can be cr eat ed by pr int ing t he scale on a cir cular r ot or and t he
slider 's t r ack pat t er n on a cir cular st at or . Such r ot ar y devices can achieve ver y high
r esolut ions. For inst ance, a t ypical r ot ar y Induct osyn may have 360 cyclic pit ches
per r ot at ion, and might use a 12-bit RDC. The conver t er effect ively divides each
pit ch int o 4096 sect or s. Mult iplying by 360 pit ches, t he r ot ar y Induct osyn divides
t he cir cle int o a t ot al of 1,474,560 sect or s. This cor r esponds t o an angular r esolut ion
of less t han 0.9 ar c seconds. As in t he case of t he linear Induct osyn, a means must
be pr ovided for count ing t he individual pit ches as t he shaft r ot at es. This may be
done wit h an addit ional r esolver act ing as t he coar se measur ement .
VECTOR AC I NDUCTI ON MOTOR CONTROL
Long known for it s simplicit y of const r uct ion, low-cost , high efficiency and long-t er m
dependabilit y, t he AC induct ion mot or has been limit ed by t he inabilit y t o cont r ol it s
dynamic per for mance in all but t he cr udest fashion. This has sever ely r est r ict ed t he
applicat ion of AC induct ion mot or s wher e dynamic cont r ol of speed, t or que and
r esponse t o changing load is r equir ed. However , r ecent advances in digit al signal
pr ocessing (DSP) and mixed-signal int egr at ed cir cuit t echnology ar e pr oviding t he
AC induct ion mot or wit h per for mance never befor e t hought possible. Manufact ur er s
anxious t o har ness t he power and economy of Vect or Cont r ol can r educe R&D cost s
and t ime t o mar ket for applicat ions r anging fr om indust r ial dr ives t o elect r ic
aut omobiles and locomot ives wit h a st andar d chipset /development syst em.
It is unlikely t hat Nikola Tesla (1856-1943), t he invent or of t he induct ion mot or ,
could have envisaged t hat t his wor khor se of indust r y could be r ejuvenat ed int o a
new class of mot or t hat is compet it ive in most indust r ial applicat ions.
Befor e discussing t he advant ages of Vect or Cont r ol it is necessar y t o have a basic
under st anding of t he fundament al oper at ion of t he differ ent t ypes of elect r ic mot or s
in common use.
Unt il r ecent ly, mot or applicat ions r equir ing ser vo-cont r ol t asks such as t uned
r esponse t o dynamic loads, const ant t or que and speed cont r ol over a wide r ange
wer e almost exclusively t he domain of DC br ush and DC per manent magnet
synchr onous mot or s. The fundament al r eason for t his pr efer ence was t he
availabilit y of well under st ood and pr oven cont r ol schemes. Alt hough easily
6.18
cont r olled, DC br ush mot or s suffer fr om sever al disadvant ages; br ushes wear and
must be r eplaced at r egular int er vals, commut at or s wear and can be per manent ly
damaged by inadequat e br ush maint enance, br ush/commut at or assemblies ar e a
sour ce of par t iculat e cont aminant s, and t he ar cing of mechanical commut at ion can
be a ser ious fir e hazar d is some envir onment s.
The availabilit y of power inver t er s capable of cont r olling high-hor sepower mot or s
allowed pr act ical implement at ion of alt er nat e mot or ar chit ect ur es such as t he DC
per manent magnet synchr onous mot or (PMSM) in ser vo cont r ol applicat ions.
Alt hough eliminat ing many of t he mechanical pr oblems associat ed wit h DC br ush
mot or s, t hese mot or s r equir ed mor e complex cont r ol schemes and suffer ed fr om
sever al dr awbacks of t heir own. Aside fr om being cost ly, DC PMSMs in lar ger , high-
hor sepower configur at ions suffer fr om high r ot or moment -of-iner t ia as well as
limit ed use in high speed applicat ions due t o mechanical const r aint s of r ot or
const r uct ion and t he need t o implement field weakening t o exceed baseplat e speed.
In t he 1960's, advances in cont r ol t heor y, in par t icular t he development of indirect
field-oriented control, pr ovided t he t heor et ical basis for dynamic cont r ol of AC
induct ion mot or s. Because of t he int ensive mat hemat ical comput at ions r equir ed by
indir ect field-or ient ed cont r ol, now commonly r efer r ed t o as vector control, pr act ical
implement at ion was not possible for many year s. Available har dwar e could not
per for m t he high-speed pr ecision sensing of r ot or posit ion and near r eal-t ime
comput at ion of dynamic flux vect or s. The cur r ent availabilit y of pr ecision opt ical
encoder s, isolat ed gat e bipolar t r ansist or s (IGBTs), high-speed r esolver -t o-digit al
conver t er s and high-speed digit al signal pr ocessor s (DSPs) has pushed vect or cont r ol
t o t he for efr ont of mot or development due t o t he advant ages inher ent in t he AC
induct ion mot or .
A simplified block diagr am of an AC induct ion mot or cont r ol syst em is shown in
Figur e 6.17. In t his example, a single-chip IC (ADMC300, ADMC330, or ADMC331)
per for ms t he cont r ol funct ions. The input s t o t he cont r oller chip ar e t he mot or
cur r ent s (nor mally t hr ee-phase) and t he mot or r ot or posit ion and velocit y. Hall-
effect sensor s ar e oft en used t o monit or t he cur r ent s, and a r esolver and an RDC
monit or t he r ot or posit ion and velocit y. The DSP is used t o per for m t he r eal t ime
vect or -t ype calculat ions necessar y t o gener at e t he cont r ol out put s t o t he inver t er
pr ocessor s. The t r ansfor mat ions r equir ed for vect or cont r ol ar e also accomplished
wit h t he DSP.
The ADMC300 compr ises a high per for mance, 5 channel 16-bit ADC syst em, a 12-
bit 3-phase PWM gener at ion unit , and a flexible encoder int er face for posit ion sensor
feedback. The ADMC330 includes a 7 channel 12-bit ADC syst em and a 12-bit 3-
phase PWM gener at or . The ADMC331 includes a 7 channel 12-bit ADC syst em, and
a pr ogr ammable 16-bit 3-phase PWM gener at or . It also has addit ional power fact or
cor r ect ion cont r ol capabilit ies. All devices have on-chip DSPs (appr oximat ely
20MHz) based on Analog Device's Modified Har var d Ar chit echur e 16-bit DSP cor e.
Thir d-par t y DSP soft war e and r efer ence designs ar e available t o facilit at e mot or
cont r ol syst em development using t hese chips.
6.19
AC INDUCTION MOTOR CONTROL APPLICATION
VECTOR
TRANSFORM
PROCESSOR
PWM
POWER
STAGE
(INVERTER)
AC
MOTOR
RESOLVER
RESOLVER TO
DIGITAL
CONVERTER
ADCs DSP
HOST
COMPUTER
POSITION, VELOCITY
MOTOR CURRENTS
ADMC300, ADMC330, or ADMC331
Figure 6.17
ACCELEROMETERS
Acceler omet er s ar e widely used t o measur e t ilt , iner t ial for ces, shock, and vibr at ion.
They find wide usage in aut omot ive, medical, indust r ial cont r ol, and ot her
applicat ions. Moder n micr omachining t echniques allow t hese acceler omet er s t o be
manufact ur ed on CMOS pr ocesses at low cost wit h high r eliabilit y. Analog Devices
iMEMS (Int egr at ed Micr o Elect r o Mechanical Syst ems) acceler omet er s r epr esent a
br eakt hr ough in t his t echnology. A significant advant age of t his t ype of
acceler omet er over piezoelect r ic-t ype char ge-out put acceler omet er s is t hat DC
acceler at ion can be measur ed (e.g. t hey can be used in t ilt measur ement s wher e t he
acceler at ion is a const ant 1g).
The basic unit cell sensor building block for t hese acceler omet er s is shown in Figur e
6.19. The sur face micr omachined sensor element is made by deposit ing polysilicon
on a sacr ificial oxide layer t hat is t hen et ched away leaving t he suspended sensor
element . The act ual sensor has t ens of unit cells for sensing acceler at ion, but t he
diagr am shows only one cell for clar it y. The elect r ical basis of t he sensor is t he
differ ent ial capacit or (CS1 and CS2) which is for med by a cent er plat e which is par t
of t he moving beam and t wo fixed out er plat es. The t wo capacit or s ar e equal at r est
(no applied acceler at ion). When acceler at ion is applied, t he mass of t he beam causes
it t o move closer t o one of t he fixed plat es while moving fur t her fr om t he ot her . This
change in differ ent ial capacit ance for ms t he elect r ical basis for t he condit ioning
elect r onics shown in Figur e 6.20.
6.20
ACCELEROMETER APPLICATIONS
n Tilt or Inclination
u Car Alarms
u Patient Monitors
n Inertial Forces
u Laptop Computer Disc Drive Protection
u Airbag Crash Sensors
u Car Navigation systems
u Elevator Controls
n Shock or Vibration
u Machine Monitoring
u Control of Shaker Tables
n ADI Accelerometer Fullscale g-Range: 2g to 100g
n ADI Accelerometer Frequency Range: DC to 1kHz
Figure 6.18
ADXL-FAMILY MICROMACHINED ACCELEROMETERS
(TOP VIEW OF IC)
FIXED
OUTER
PLATES
CS1 CS1
< CS2 = CS2
DENOTES ANCHOR
BEAM
TETHER
CS1 CS2
CENTER
PLATE
AT REST
APPLIED ACCELERATION
Figure 6.19
6.21
ADXL-FAMILY ACCELEROMETERS
INTERNAL SIGNAL CONDITIONING
OSCILLATOR
A1
SYNCHRONOUS
DEMODULATOR
BEAM
PLATE
PLATE
CS1
CS2
SYNC
0
180
A2
V
OUT
CS2 > CS1
A
P
P
L
I
E
D

A
C
C
E
L
E
R
A
T
I
O
N
Figure 6.20
The sensor 's fixed capacit or plat es ar e dr iven differ ent ially by a 1MHz squar e wave:
t he t wo squar e wave amplit udes ar e equal but ar e 180 out of phase. When at r est ,
t he values of t he t wo capacit or s ar e t he same, and t her efor e t he volt age out put at
t heir elect r ical cent er (i.e., at t he cent er plat e at t ached t o t he movable beam) is zer o.
When t he beam begins t o move, a mismat ch in t he capacit ance pr oduces an out put
signal at t he cent er plat e. The out put amplit ude will incr ease wit h t he acceler at ion
exper ienced by t he sensor . The cent er plat e is buffer ed by A1 and applied t o a
synchr onous demodulat or . The dir ect ion of beam mot ion affect s t he phase of t he
signal, and synchr onous demodulat ion is t her efor e used t o ext r act t he amplit ude
infor mat ion. The synchr onous demodulat or out put is amplified by A2 which supplies
t he acceler at ion out put volt age, V
OUT
.
An int er est ing applicat ion of low-g acceler omet er s is measur ing t ilt . Figur e 6.21
shows t he r esponse of an acceler omet er t o t ilt . The acceler omet er out put on t he
diagr am has been nor malized t o 1g fullscale. The acceler omet er out put is
pr opor t ional t o t he sine of t he t ilt angle wit h r espect t o t he hor izon. Not e t hat
maximum sensit ivit y occur s when t he acceler omet er axis is per pendicular t o t he
acceler at ion. This scheme allows t ilt angles fr om 90 t o +90 (180 of r ot at ion) t o be
measur ed. However , in or der t o measur e a full 360 r ot at ion, a dual-axis
acceler omet er must be used.
6.22
USING AN ACCELEROMETER TO MEASURE TILT
X
0
+90

1g
Acceleration
X
90
1g
0
+1g
+90
Acceleration = 1g sin
0g
90
Figure 6.21
Figur e 6.22 shows a simplified block diagr am of t he ADXL202 dual axis 2g
acceler omet er . The out put is a pulse whose dut y cycle cont ains t he acceler at ion
infor mat ion. This t ype of out put is ext r emely useful because of it s high noise
immunit y, and t he dat a is t r ansmit t ed over a single wir e. St andar d low cost
micr ocont r oller s have t imer s which can be easily used t o measur e t he T1 and T2
int er vals. The acceler at ion in g is t hen calculat ed using t he for mula:
A(g) = 8 [T1/T2 0.5] .
Not e t hat a dut y cycle of 50% (T1 = T2) yields a 0g out put . T2 does not have t o be
measur ed for ever y measur ement cycle. It need only be updat ed t o account for
changes due t o t emper at ur e. Since t he T2 t ime per iod is shar ed by bot h X and Y
channels, it is necessar y t o only measur e it on one channel. The T2 per iod can be set
fr om 0.5ms t o 10ms wit h an ext er nal r esist or .
Analog volt ages r epr esent ing acceler at ion can be obt ained by buffer ing t he signal
fr om t he X
FILT
and Y
FILT
out put s or by passing t he dut y cycle signal t hr ough an
RC filt er t o r econst r uct it s DC value.
A single acceler omet er cannot wor k in all applicat ions. Specifically, t her e is a need
for bot h low-g and high-g acceler omet er s. Low-g devices ar e useful in such
applicat ions as t ilt measur ement s, but higher -g acceler omet er s ar e needed in
applicat ions such as air bag cr ash sensor s. Figur e 6.23 summar izes Analog Devices
family of ADXL acceler omet er s t o dat e. Not e t hat dual-axis ver sions as well as dut y-
cycle out put ver sions ar e also available for some of t he devices.
6.23
ADXL202 2g DUAL AXIS ACCELEROMETER
OSCILLATOR
DEMOD
DEMOD
DUTY
CYCLE
MODULATOR
X
Y
SENSOR
SENSOR
32k
32k
+3.0V TO +5.25V
V
DD
V
DD
C
X
C
Y
X
FILT
Y
FILT
SELF TEST
R
SET
T2
XOUT
YOUT
C
T1
T2
A(g) = 8 (T1 /T2 0.5)
0g = 50% DUTY CYCLE
T2 = R
SET
/125M
ADXL202
Figure 6.22
ADXL FAMILY OF ACCELEROMETERS
ADXL202
ADXL05
ADXL105
ADXL210
ADXL150
ADXL250
ADXL190
g RANGE
2g
5g
5g
10g
50g
50g
100g
NOISE
DENSITY
0.5mg/ Hz
0.5mg/ Hz
0.175mg/ Hz
0.5mg/ Hz
1mg/ Hz
1mg/ Hz
4mg/ Hz
SINGLE/
DUAL AXIS
Dual
Single
Single
Dual
Single
Dual
Single
VOLTAGE/
DUTY CYCLE
OUTPUT
Duty Cycle
Voltage
Voltage
Duty Cycle
Voltage
Voltage
Voltage
Figure 6.23
6.24
REFERENCES
1. Her man Schaevit z, The Linear Variable Differential Transformer,
P r oceed i n gs of t h e SASE, Volume IV, No. 2, 1946.
2. Dr . Er nest D.D. Schmidt , Linear Displacement - Linear Variable
Differential Transformers - LVDTs, Schaevit z Sensor s,
ht t p://www.schaevit z.com.
3. E-Ser ies LVDT Dat a Sheet , Schaevit z Sensor s, ht t p://www.schaevit z.com.
Schaevit z Sensor s is now a division of Lucas Cont r ol Syst ems, 1000 Lucas
Way, Hampt on, VA 23666.
5. Har r y L. Tr iet ley, Tr a n sd u cer s i n Mech a n i ca l a n d Elect r on i c
Desi gn , Mar cel Dekker , Inc., 1986.
6. AD598 and AD698 Dat a Sheet , Analog Devices, Inc., ht t p://www.analog.com.
7. Bill Tr avis, Hall-Effect S ensor ICs S port Magnetic Personalities,
EDN, Apr il 9, 1998, pp. 81-91.
8. AD22151 Dat a Sheet , Analog Devices, Inc., ht t p://www.analog.com.
9. Dan Sheingold, An a log-Di gi t a l Con ver si on Ha n d book , Th i r d Ed i t i on ,
Pr ent ice-Hall, 1986.
10. F. P. Flet t , Vector Control Using a S ingle Vector Rotation S emiconductor for
Induction and Permanent Magnet Motors, P CI M Con fer en ce, I n t elli gen t
Mot i on , Sep t ember 1992 P r oceed i n gs, Available fr om Analog Devices.
11. F. P. Flet t , S ilicon Control Algorithms for Brushless Permanent Magnet
S ynchronous Machines, P CI M Con fer en ce, I n t elli gen t Mot i on , J u n e
1991 P r oceed i n gs, Available fr om Analog Devices.
12. P.J .M. Coussens, et al, Three Phase Measurements with Vector Rotation
Blocks in Mains and Motion Control, P CI M Con fer en ce, I n t elli gen t
Mot i on , Ap r i l 1992 P r oceed i n gs, Available fr om Analog Devices.
13. Dennis Fu, Digital to S ynchro and Resolver Conversion with the AC Vector
Processor AD2S 100, Available fr om Analog Devices.
14. Dennis Fu, Circuit Applications of the AD2S 90 Resolver-to-Digital Converter,
AN-230, Analog Devices.
15. Aengus Mur r ay and P. Ket t le, Towards a S ingle Chip DS P Based Motor
6.25
Control S olution, P r oceed i n gs P CI M - I n t elli gen t Mot i on , May 1996,
Nur nber g Ger many, pp. 315-326. Also available at ht t p://www.analog.com.
16. D. J . Lucey, P. J . Roche, M. B. Har r ingt on, and J . R. Scannell,
Comparison of Various S pace Vector Modulation S trategies,
P r oceed i n gs I r i sh DSP a n d Con t r ol Colloqu i u m, J uly 1994, Dublin,
Ir eland, pp. 169-175.
17. Niall Lyne, ADCs Lend Flexibility to Vector Motor Control Applications,
Elect r on i c Desi gn , May 1, 1998, pp. 93-100.
18. Fr ank Goodenough, Airbags Boom when IC Accelerometer S ees 50g,
Elect r on i c Desi gn , August 8, 1991.
TEMP ERATURE SENSORS
7.1
SECTI ON 7
Wa l t Kest er , J a m es Br ya n t , Wa l t J u n g
I NTRODUCTI ON
Measur ement of t emper at ur e is cr it ical in moder n elect r onic devices, especially
expensive lapt op comput er s and ot her por t able devices wit h densely packed cir cuit s
which dissipat e consider able power in t he for m of heat . Knowledge of syst em
t emper at ur e can also be used t o cont r ol bat t er y char ging as well as pr event damage
t o expensive micr opr ocessor s.
Compact high power por t able equipment oft en has fan cooling t o maint ain junct ion
t emper at ur es at pr oper levels. In or der t o conser ve bat t er y life, t he fan should only
oper at e when necessar y. Accur at e cont r ol of t he fan r equir es a knowledge of cr it ical
t emper at ur es fr om t he appr opr iat e t emper at ur e sensor .
n Monitoring
u Portable Equipment
u CPU Temperature
u Battery Temperature
u Ambient Temperature
n Compensation
u Oscillator Drift in Cellular Phones
u Thermocouple Cold-Junction Compensation
n Control
u Battery Charging
u Process Control
APPLICATIONS OF TEMPERATURE SENSORS
Figure 7.1
Accur at e t emper at ur e measur ement s ar e r equir ed in many ot her measur ement
syst ems such as pr ocess cont r ol and inst r ument at ion applicat ions. In most cases,
because of low-level nonlinear out put s, t he sensor out put must be pr oper ly
condit ioned and amplified befor e fur t her pr ocessing can occur .
Except for IC sensor s, all t emper at ur e sensor s have nonlinear t r ansfer funct ions. In
t he past , complex analog condit ioning cir cuit s wer e designed t o cor r ect for t he sensor
nonlinear it y. These cir cuit s oft en r equir ed manual calibr at ion and pr ecision
r esist or s t o achieve t he desir ed accur acy. Today, however , sensor out put s may be
7.2
digit ized dir ect ly by high r esolut ion ADCs. Linear izat ion and calibr at ion is t hen
per for med digit ally, t her eby r educing cost and complexit y.
Resist ance Temper at ur e Devices (RTDs) ar e accur at e, but r equir e excit at ion cur r ent
and ar e gener ally used in br idge cir cuit s. Ther mist or s have t he most sensit ivit y but
ar e t he most non-linear . However , t hey ar e popular in por t able applicat ions such as
measur ement of bat t er y t emper at ur e and ot her cr it ical t emper at ur es in a syst em.
Moder n semiconduct or t emper at ur e sensor s offer high accur acy and high linear it y
over an oper at ing r ange of about 55C t o +150C. Int er nal amplifier s can scale t he
out put t o convenient values, such as 10mV/C. They ar e also useful in cold-junct ion-
compensat ion cir cuit s for wide t emper at ur e r ange t her mocouples. Semiconduct or
t emper at ur e sensor s can be int egr at ed int o mult i-funct ion ICs which per for m a
number of ot her har dwar e monit or ing funct ions.
Figur e 7.2 list s t he most popular t ypes of t emper at ur e t r ansducer s and t heir
char act er ist ics.
TYPES OF TEMPERATURE SENSORS
THERMOCOUPLE RTD THERMISTOR SEMICONDUCTOR
Widest Range:
184C to +2300C
Range:
200C to +850C
Range:
0C to +100C
Range:
55C to +150C
High Accuracy and
Repeatability
Fair Linearity Poor Linearity Linearity: 1C
Accuracy: 1C
Needs Cold Junction
Compensation
Requires
Excitation
Requires
Excitation
Requires Excitation
Low-Voltage Output Low Cost High Sensitivity 10mV/K, 20mV/K,
or 1A/K Typical
Output
Figure 7.2
THERMOCOUP LE P RI NCI P LES AND COLD-J UNCTI ON
COMP ENSATI ON
Ther mocouples ar e small, r ugged, r elat ively inexpensive, and oper at e over t he
widest r ange of all t emper at ur e sensor s. They ar e especially useful for making
measur ement s at ext r emely high t emper at ur es (up t o +2300C) in host ile
envir onment s. They pr oduce only millivolt s of out put , however , and r equir e
pr ecision amplificat ion for fur t her pr ocessing. They also r equir e cold-junct ion-
compensat ion (CJ C) t echniques which will be discussed shor t ly. They ar e mor e
linear t han many ot her sensor s, and t heir non-linear it y has been well char act er ized.
Some common t her mocouples ar e shown in Figur e 7.3. The most common met als
used ar e Ir on, Plat inum, Rhodium, Rhenium, Tungst en, Copper , Alumel (composed
7.3
of Nickel and Aluminum), Chr omel (composed of Nickel and Chr omium) and
Const ant an (composed of Copper and Nickel).
COMMON THERMOCOUPLES
JUNCTION MATERIALS
TYPICAL
USEFUL
RANGE (C)
NOMINAL
SENSITIVITY
(V/C)
ANSI
DESIGNATION
Platinum (6%)/ Rhodium-
Platinum (30%)/Rhodium
38 to 1800 7.7 B
Tungsten (5%)/Rhenium -
Tungsten (26%)/Rhenium
0 to 2300 16 C
Chromel - Constantan 0 to 982 76 E
Iron - Constantan 0 to 760 55 J
Chromel - Alumel 184 to 1260 39 K
Platinum (13%)/Rhodium-
Platinum
0 to 1593 11.7 R
Platinum (10%)/Rhodium-
Platinum
0 to 1538 10.4 S
Copper-Constantan 184 to 400 45 T
Figure 7.3
Figur e 7.4 shows t he volt age-t emper at ur e cur ves of t hr ee commonly used
t her mocouples, r efer r ed t o a 0C fixed-t emper at ur e r efer ence junct ion. Of t he
t her mocouples shown, Type J t her mocouples ar e t he most sensit ive, pr oducing t he
lar gest out put volt age for a given t emper at ur e change. On t he ot her hand, Type S
t her mocouples ar e t he least sensit ive. These char act er ist ics ar e ver y impor t ant t o
consider when designing signal condit ioning cir cuit r y in t hat t he t her mocouples'
r elat ively low out put signals r equir e low-noise, low-dr ift , high-gain amplifier s.
To under st and t her mocouple behavior , it is necessar y t o consider t he non-linear it ies
in t heir r esponse t o t emper at ur e differ ences. Figur e 7.4 shows t he r elat ionships
bet ween sensing junct ion t emper at ur e and volt age out put for a number of
t her mocouple t ypes (in all cases, t he r efer ence cold junct ion is maint ained at 0C). It
is evident t hat t he r esponses ar e not quit e linear , but t he nat ur e of t he non-linear it y
is not so obvious.
Figur e 7.5 shows how t he Seebeck coefficient (t he change of out put volt age wit h
change of sensor junct ion t emper at ur e - i.e., t he fir st der ivat ive of out put wit h
r espect t o t emper at ur e) var ies wit h sensor junct ion t emper at ur e (we ar e st ill
consider ing t he case wher e t he r efer ence junct ion is maint ained at 0C).
When select ing a t her mocouple for making measur ement s over a par t icular r ange of
t emper at ur e, we should choose a t her mocouple whose Seebeck coefficient var ies as
lit t le as possible over t hat r ange.
7.4
THERMOCOUPLE OUTPUT VOLTAGES FOR
TYPE J, K, AND S THERMOCOUPLES
-250 0 250 500 750 1000 1250 1500 1750
-10
0
10
20
30
40
50
60
T
H
E
R
M
O
C
O
U
P
L
E

O
U
T
P
U
T

V
O
L
T
A
G
E

(
m
V
)
TEMPERATURE (C)
TYPE J
TYPE K
TYPE S
Figure 7.4
THERMOCOUPLE SEEBECK COEFFICIENT
VERSUS TEMPERATURE
-250 0 250 500 750 1000 1250 1500 1750
0
10
20
30
40
50
60
70
S
E
E
B
E
C
K

C
O
E
F
F
I
C
I
E
N
T

-

V
/

C
TEMPERATURE (C)
TYPE J
TYPE K
TYPE S
Figure 7.5
7.5
For example, a Type J t her mocouple has a Seebeck coefficient which var ies by less
t han 1V/C bet ween 200 and 500C, which makes it ideal for measur ement s in t his
r ange.
Pr esent ing t hese dat a on t her mocouples ser ves t wo pur poses: Fir st , Figur e 7.4
illust r at es t he r ange and sensit ivit y of t he t hr ee t her mocouple t ypes so t hat t he
syst em designer can, at a glance, det er mine t hat a Type S t her mocouple has t he
widest useful t emper at ur e r ange, but a Type J t her mocouple is mor e sensit ive.
Second, t he Seebeck coefficient s pr ovide a quick guide t o a t her mocouple's linear it y.
Using Figur e 7.5, t he syst em designer can choose a Type K t her mocouple for it s
linear Seebeck coefficient over t he r ange of 400C t o 800C or a Type S over t he
r ange of 900C t o 1700C. The behavior of a t her mocouple's Seebeck coefficient is
impor t ant in applicat ions wher e var iat ions of t emper at ur e r at her t han absolut e
magnit ude ar e impor t ant . These dat a also indicat e what per for mance is r equir ed of
t he associat ed signal condit ioning cir cuit r y.
To use t her mocouples successfully we must under st and t heir basic pr inciples.
Consider t he diagr ams in Figur e 7.6.
THERMOCOUPLE BASICS
T1
Metal A
Metal B
Thermoelectric
EMF
R Metal A Metal A
R = Total Circuit Resistance
I = (V1 V2) / R
V1 T1 V2 T2
V1 V2
Metal B
Metal A Metal A
V1
V1
T1
T1
T2
T2
V2
V2
V
Metal A Metal A
Copper Copper
Metal B Metal B
T3 T4
V = V1 V2, If T3 = T4
A. THERMOELECTRIC VOLTAGE
B. THERMOCOUPLE
C. THERMOCOUPLE MEASUREMENT
D. THERMOCOUPLE MEASUREMENT
I
V1
Figure 7.6
If we join t wo dissimilar met als at any t emper at ur e above absolut e zer o, t her e will
be a pot ent ial differ ence bet ween t hem (t heir "t her moelect r ic e.m.f." or "cont act
pot ent ial") which is a funct ion of t he t emper at ur e of t he junct ion (Figur e 7.6A). If we
join t he t wo wir es at t wo places, t wo junct ions ar e for med (Figur e 7.6B). If t he t wo
junct ions ar e at differ ent t emper at ur es, t her e will be a net e.m.f. in t he cir cuit , and a
cur r ent will flow det er mined by t he e.m.f. and t he t ot al r esist ance in t he cir cuit
(Figur e 7.6B). If we br eak one of t he wir es, t he volt age acr oss t he br eak will be
7.6
equal t o t he net t her moelect r ic e.m.f. of t he cir cuit , and if we measur e t his volt age,
we can use it t o calculat e t he t emper at ur e differ ence bet ween t he t wo junct ions
(Figur e 7.6C). We must always remember that a thermocouple measures the
temperature difference between two junctions, not the absolute temperature at one
junction. We can only measur e t he t emper at ur e at t he measur ing junct ion if we
know t he t emper at ur e of t he ot her junct ion (oft en called t he "r efer ence" junct ion or
t he "cold" junct ion).
But it is not so easy t o measur e t he volt age gener at ed by a t her mocouple. Suppose
t hat we at t ach a volt met er t o t he cir cuit in Figur e 7.6C (Figur e 7.6D). The wir es
at t ached t o t he volt met er will for m fur t her t her mojunct ions wher e t hey ar e
at t ached. If bot h t hese addit ional junct ions ar e at t he same t emper at ur e (it does not
mat t er what t emper at ur e), t hen t he "Law of Int er mediat e Met als" st at es t hat t hey
will make no net cont r ibut ion t o t he t ot al e.m.f. of t he syst em. If t hey ar e at
differ ent t emper at ur es, t hey will int r oduce er r or s. Since every pair of dissimilar
metals in contact generates a thermoelectric e.m.f. (including copper /solder ,
kovar /copper [kovar is t he alloy used for IC leadfr ames] and aluminum/kovar [at t he
bond inside t he IC]), it is obvious t hat in pr act ical cir cuit s t he pr oblem is even mor e
complex, and it is necessar y t o t ake ext r eme car e t o ensur e t hat all t he junct ion
pair s in t he cir cuit r y ar ound a t her mocouple, except t he measur ement and r efer ence
junct ions t hemselves, ar e at t he same t emper at ur e.
Ther mocouples gener at e a volt age, albeit a ver y small one, and do not r equir e
excit at ion. As shown in Figur e 7.6D, however , t wo junct ions (T1, t he measur ement
junct ion and T2, t he r efer ence junct ion) ar e involved. If T2 = T1, t hen V2 = V1, and
t he out put volt age V = 0. Ther mocouple out put volt ages ar e oft en defined wit h a
r efer ence junct ion t emper at ur e of 0C (hence t he t er m cold or ice point junct ion), so
t he t her mocouple pr ovides an out put volt age of 0V at 0C. To maint ain syst em
accur acy, t he r efer ence junct ion must t her efor e be at a well-defined t emper at ur e
(but not necessar ily 0C). A concept ually simple appr oach t o t his need is shown in
Figur e 7.7. Alt hough an ice/wat er bat h is r elat ively easy t o define, it is quit e
inconvenient t o maint ain.
Today an ice-point r efer ence, and it s inconvenient ice/wat er bat h, is gener ally
r eplaced by elect r onics. A t emper at ur e sensor of anot her sor t (oft en a semiconduct or
sensor , somet imes a t her mist or ) measur es t he t emper at ur e of t he cold junct ion and
is used t o inject a volt age int o t he t her mocouple cir cuit which compensat es for t he
differ ence bet ween t he act ual cold junct ion t emper at ur e and it s ideal value (usually
0C) as shown in Figur e 7.8. Ideally, t he compensat ion volt age should be an exact
mat ch for t he differ ence volt age r equir ed, which is why t he diagr am gives t he
volt age as f(T2) (a function of T2) r at her t han KT2, wher e K is a simple const ant . In
pr act ice, since t he cold junct ion is r ar ely mor e t han a few t ens of degr ees fr om 0C,
and gener ally var ies by lit t le mor e t han 10C, a linear appr oximat ion (V=KT2) t o
t he mor e complex r ealit y is sufficient ly accur at e and is what is oft en used. (The
expr ession for t he out put volt age of a t her mocouple wit h it s measur ing junct ion at
TC and it s r efer ence at 0C is a polynomial of t he for m V = K
1
T + K
2
T
2
+ K
3
T
3
+
..., but t he values of t he coefficient s K
2
, K
3
, et c. ar e ver y small for most common
t ypes of t her mocouple. Refer ences 8 and 9 give t he values of t hese coefficient s for a
wide r ange of t her mocouples.)
7.7
CLASSICAL COLD-JUNCTION COMPENSATION USING AN
ICE-POINT (0C) REFERENCE JUNCTION
METAL A METAL A
METAL B
ICE
BATH
0C
V(0C)
T1 V1
V1 V(0C)
T2
Figure 7.7
USING A TEMPERATURE SENSOR
FOR COLD-JUNCTION COMPENSATION
TEMPERATURE
COMPENSATION
CIRCUIT
TEMP
SENSOR
T2 V(T2) T1 V(T1)
V(OUT)
V(COMP)
SAME
TEMP
METAL A
METAL B
METAL A
COPPER COPPER
ISOTHERMAL BLOCK
V(COMP) = f(T2)
V(OUT) = V(T1) V(T2) + V(COMP)
IF V(COMP) = V(T2) V(0C), THEN
V(OUT) = V(T1) V(0C)
Figure 7.8
7.8
When elect r onic cold-junct ion compensat ion is used, it is common pr act ice t o
eliminat e t he addit ional t her mocouple wir e and t er minat e t he t her mocouple leads in
t he isot her mal block in t he ar r angement shown in Figur e 7.9. The Met al A-Copper
and t he Met al B-Copper junct ions, if at t he same t emper at ur e, ar e equivalent t o t he
Met al A-Met al B t her mocouple junct ion in Figur e 7.8.
TERMINATING THERMOCOUPLE LEADS
DIRECTLY TO AN ISOTHERMAL BLOCK
TEMPERATURE
COMPENSATION
CIRCUIT
TEMP
SENSOR
METAL A
METAL B
COPPER
COPPER
COPPER
V(OUT) = V1 V(0C)
T1 V1
T2
T2
ISOTHERMAL BLOCK
Figure 7.9
The cir cuit in Figur e 7.10 condit ions t he out put of a Type K t her mocouple, while
pr oviding cold-junct ion compensat ion, for t emper at ur es bet ween 0C and 250C. The
cir cuit oper at es fr om single +3.3V t o +12V supplies and has been designed t o
pr oduce an out put volt age t r ansfer char act er ist ic of 10mV/C.
A Type K t her mocouple exhibit s a Seebeck coefficient of appr oximat ely 41V/C;
t her efor e, at t he cold junct ion, t he TMP35 volt age out put sensor wit h a t emper at ur e
coefficient of 10mV/C is used wit h R1 and R2 t o int r oduce an opposing cold-junct ion
t emper at ur e coefficient of 41V/C. This pr event s t he isot her mal, cold-junct ion
connect ion bet ween t he cir cuit 's pr int ed cir cuit boar d t r aces and t he t her mocouple's
wir es fr om int r oducing an er r or in t he measur ed t emper at ur e. This compensat ion
wor ks ext r emely well for cir cuit ambient t emper at ur es in t he r ange of 20C t o 50C.
Over a 250C measur ement t emper at ur e r ange, t he t her mocouple pr oduces an
out put volt age change of 10.151mV. Since t he r equir ed cir cuit 's out put full-scale
volt age change is 2.5V, t he gain of t he cir cuit is set t o 246.3. Choosing R4 equal t o
4.99k set s R5 equal t o 1.22M. Since t he closest 1% value for R5 is 1.21M, a
50k pot ent iomet er is used wit h R5 for fine t r im of t he full-scale out put volt age.
Alt hough t he OP193 is a single-supply op amp, it s out put st age is not r ail-t o-r ail,
and will only go down t o about 0.1V above gr ound. For t his r eason, R3 is added t o
t he cir cuit t o supply an out put offset volt age of about 0.1V for a nominal supply
volt age of 5V. This offset (10C) must be subt r act ed when making measur ement s
7.9
r efer enced t o t he OP193 out put . R3 also pr ovides an open t her mocouple det ect ion,
for cing t he out put volt age t o gr eat er t han 3V should t he t her mocouple open.
Resist or R7 balances t he DC input impedance of t he OP193, and t he 0.1F film
capacit or r educes noise coupling int o it s non-inver t ing input .
R1*
24.9k
USING A TEMPERATURE SENSOR FOR
COLD-JUNCTION COMPENSATION (TMP35)
TMP35
OP193
ISOTHERMAL
BLOCK
COLD
JUNCTION
R6
100k
R4*
4.99k
R2*
102
P1
50k
R5*
1.21M
R3*
1.24M
TYPE K
THERMO
COUPLE
CHROMEL
ALUMEL
+
Cu
Cu
3.3V TO 5.5V
V
OUT
0.1 - 2.6V
* USE 1% RESISTORS
10mV/C
0 C < T < 250 C
0.1F
R7*
4.99k
0.1F
FILM
Figure 7.10
The AD594/AD595 is a complet e inst r ument at ion amplifier and t her mocouple cold
junct ion compensat or on a monolit hic chip (see Figur e 7.11). It combines an ice point
r efer ence wit h a pr ecalibr at ed amplifier t o pr ovide a high level (10mV/C) out put
dir ect ly fr om t he t her mocouple signal. Pin-st r apping opt ions allow it t o be used as a
linear amplifier -compensat or or as a swit ched out put set -point cont r oller using
eit her fixed or r emot e set -point cont r ol. It can be used t o amplify it s compensat ion
volt age dir ect ly, t her eby becoming a st and-alone Celsius t r ansducer wit h 10mV/C
out put . In such applicat ions it is ver y impor t ant t hat t he IC chip is at t he same
t emper at ur e as t he cold junct ion of t he t her mocouple, which is usually achieved by
keeping t he t wo in close pr oximit y and isolat ed fr om any heat sour ces.
The AD594/AD595 includes a t her mocouple failur e alar m t hat indicat es if one or
bot h t her mocouple leads open. The alar m out put has a flexible for mat which
includes TTL dr ive capabilit y. The device can be power ed fr om a single-ended supply
(which may be as low as +5V), but by including a negat ive supply, t emper at ur es
below 0C can be measur ed. To minimize self-heat ing, an unloaded AD594/AD595
will oper at e wit h a supply cur r ent of 160A, but is also capable of deliver ing 5mA
t o a load.
The AD594 is pr ecalibr at ed by laser wafer t r imming t o mat ch t he char act er ist ics of
t ype J (ir on/const ant an) t her mocouples, and t he AD595 is laser t r immed for t ype K
7.10
(chr omel/alumel). The t emper at ur e t r ansducer volt ages and gain cont r ol r esist or s
ar e available at t he package pins so t hat t he cir cuit can be r ecalibr at ed for ot her
t her mocouple t ypes by t he addit ion of r esist or s. These t er minals also allow mor e
pr ecise calibr at ion for bot h t her mocouple and t her momet er applicat ions. The
AD594/AD595 is available in t wo per for mance gr ades. The C and t he A ver sions
have calibr at ion accur acies of 1C and 3C, r espect ively. Bot h ar e designed t o be
used wit h cold junct ions bet ween 0 t o +50C. The cir cuit shown in Figur e 7.11 will
pr ovide a dir ect out put fr om a t ype J t her mocouple (AD594) or a t ype K
t her mocouple (AD595) capable of measur ing 0 t o +300C.
AD594/AD595 MONOLITHIC THERMOCOUPLE AMPLIFIERS
WITH COLD-JUNCTION COMPENSATION
ICE
POINT
COMP
+
OVERLOAD
DETECT
V
OUT
10mV/C
+5V
BROKEN
THERMOCOUPLE
ALARM
4.7k
G
+
TC

+TC
+
+A
THERMOCOUPLE
G
AD594/AD595
TYPE J: AD594
TYPE K: AD595
0.1F
Figure 7.11
The AD596/AD597 ar e monolit hic set -point cont r oller s which have been opt imized
for use at elevat ed t emper at ur es as ar e found in oven cont r ol applicat ions. The
device cold-junct ion compensat es and amplifies a t ype J /K t her mocouple t o der ive an
int er nal signal pr opor t ional t o t emper at ur e. They can be configur ed t o pr ovide a
volt age out put (10mV/C) dir ect ly fr om t ype J /K t her mocouple signals. The device is
packaged in a 10-pin met al can and is t r immed t o oper at e over an ambient r ange
fr om +25C t o +100C. The AD596 will amplify t her mocouple signals cover ing t he
ent ir e 200C t o +760C t emper at ur e r ange r ecommended for t ype J t her mocouples
while t he AD597 can accommodat e 200C t o +1250C t ype K input s. They have a
calibr at ion accur acy of 4C at an ambient t emper at ur e of 60C and an ambient
t emper at ur e st abilit y specificat ion of 0.05C/C fr om +25C t o +100C.
None of t he t her mocouple amplifier s pr eviously descr ibed compensat e for
t her mocouple non-linear it y, t hey only pr ovide condit ioning and volt age gain. High
7.11
r esolut ion ADCs such as t he AD77XX family can be used t o digit ize t he
t her mocouple out put dir ect ly, allowing a micr ocont r oller t o per for m t he t r ansfer
funct ion linear izat ion as shown in Figur e 7.12. The t wo mult iplexed input s t o t he
ADC ar e used t o digit ize t he t her mocouple volt age and t he cold-junct ion
t emper at ur e sensor out put s dir ect ly. The input PGA gain is pr ogr ammable fr om 1
t o 128, and t he ADC r esolut ion is bet ween 16 and 22 bit s (depending upon t he
par t icular ADC select ed). The micr ocont r oller per for ms bot h t he cold-junct ion
compensat ion and t he linear izat ion ar it hmet ic.
AD77XX ADC USED WITH
TMP35 TEMPERATURE SENSOR FOR CJC
MUX
TMP35

ADC
OUTPUT
REGISTER
CONTROL
REGISTER
SERIAL
INTERFACE
PGA
3V OR 5V
(DEPENDING ON ADC)
THERMO
COUPLE
AD77XX SERIES
(16-22 BITS)
TO MICROCONTROLLER
G=1 TO 128
0.1F
AIN1+
AIN1
AIN2
AIN2+
Figure 7.12
RESI STANCE TEMP ERATURE DETECTORS (RTDS)
The Resist ance Temper at ur e Det ect or , or t he RTD, is a sensor whose r esist ance
changes wit h t emper at ur e. Typically built of a plat inum (Pt ) wir e wr apped ar ound a
cer amic bobbin, t he RTD exhibit s behavior which is mor e accur at e and mor e linear
over wide t emper at ur e r anges t han a t her mocouple. Figur e 7.13 illust r at es t he
t emper at ur e coefficient of a 100 RTD and t he Seebeck coefficient of a Type S
t her mocouple. Over t he ent ir e r ange (appr oximat ely 200C t o +850C), t he RTD is
a mor e linear device. Hence, linear izing an RTD is less complex.
7.12
RESISTANCE TEMPERATURE DETECTORs (RTD)
n Platinum (Pt) the Most Common
n 100, , 1000 Standard Values
n Typical TC = 0.385% / C,
0.385 / / C for 100 Pt RTD
n Good Linearity - Better than Thermocouple,
Easily Compensated
0 400 800
0.275
0.300
0.325
0.350
0.375
0.400
5.50
6.50
7.50
8.50
9.50
10.5
11.5
TYPE S
THERMOCOUPLE
100 Pt RTD
RTD
RESISTANCE
TC, / C
TYPE S
THERMOCOUPLE
SEEBECK
COEFFICIENT,
V / C
TEMPERATURE - C
Figure 7.13
Unlike a t her mocouple, however , an RTD is a passive sensor and r equir es cur r ent
excit at ion t o pr oduce an out put volt age. The RTD's low t emper at ur e coefficient of
0.385%/C r equir es similar high-per for mance signal condit ioning cir cuit r y t o t hat
used by a t her mocouple; however , t he volt age dr op acr oss an RTD is much lar ger
t han a t her mocouple out put volt age. A syst em designer may opt for lar ge value
RTDs wit h higher out put , but lar ge-valued RTDs exhibit slow r esponse t imes.
Fur t her mor e, alt hough t he cost of RTDs is higher t han t hat of t her mocouples, t hey
use copper leads, and t her moelect r ic effect s fr om t er minat ing junct ions do not affect
t heir accur acy. And finally, because t heir r esist ance is a funct ion of t he absolut e
t emper at ur e, RTDs r equir e no cold-junct ion compensat ion.
Caut ion must be exer cised using cur r ent excit at ion because t he cur r ent t hr ough t he
RTD causes heat ing. This self-heat ing changes t he t emper at ur e of t he RTD and
appear s as a measur ement er r or . Hence, car eful at t ent ion must be paid t o t he
design of t he signal condit ioning cir cuit r y so t hat self-heat ing is kept below 0.5C.
Manufact ur er s specify self-heat ing er r or s for var ious RTD values and sizes in st ill
and in moving air . To r educe t he er r or due t o self-heat ing, t he minimum cur r ent
should be used for t he r equir ed syst em r esolut ion, and t he lar gest RTD value chosen
t hat r esult s in accept able r esponse t ime.
Anot her effect t hat can pr oduce measur ement er r or is volt age dr op in RTD lead
wir es. This is especially cr it ical wit h low-value 2-wir e RTDs because t he
t emper at ur e coefficient and t he absolut e value of t he RTD r esist ance ar e bot h small.
If t he RTD is locat ed a long dist ance fr om t he signal condit ioning cir cuit r y, t hen t he
lead r esist ance can be ohms or t ens of ohms, and a small amount of lead r esist ance
can cont r ibut e a significant er r or t o t he t emper at ur e measur ement . To illust r at e
7.13
t his point , let us assume t hat a 100 plat inum RTD wit h 30-gauge copper leads is
locat ed about 100 feet fr om a cont r oller 's display console. The r esist ance of 30-gauge
copper wir e is 0.105/ft , and t he t wo leads of t he RTD will cont r ibut e a t ot al 21 t o
t he net wor k which is shown in Figur e 7.14. This addit ional r esist ance will pr oduce a
55C er r or in t he measur ement ! The leads' t emper at ur e coefficient can cont r ibut e an
addit ional, and possibly significant , er r or t o t he measur ement . To eliminat e t he
effect of t he lead r esist ance, a 4-wir e t echnique is used.
A 100 Pt RTD WITH 100 FEET
OF 30-GAUGE LEAD WIRES
R = 10.5
R = 10.5
COPPER
COPPER
100
Pt RTD
RESISTANCE TC OF COPPER = 0.40%/C @ 20C
RESISTANCE TC OF Pt RTD = 0.385%/ C @ 20C
Figure 7.14
In Figur e 7.15, a 4-wir e, or Kelvin, connect ion is made t o t he RTD. A const ant
cur r ent is applied t hough t he FORCE leads of t he RTD, and t he volt age acr oss t he
RTD it self is measur ed r emot ely via t he SENSE leads. The measur ing device can be
a DVM or an inst r ument at ion amplifier , and high accur acy can be achieved pr ovided
t hat t he measur ing device exhibit s high input impedance and/or low input bias
cur r ent . Since t he SENSE leads do not car r y appr eciable cur r ent , t his t echnique is
insensit ive t o lead wir e lengt h. Sour ces of er r or s ar e t he st abilit y of t he const ant
cur r ent sour ce and t he input impedance and/or bias cur r ent s in t he amplifier or
DVM.
RTDs ar e gener ally configur ed in a four -r esist or br idge cir cuit . The br idge out put is
amplified by an inst r ument at ion amplifier for fur t her pr ocessing. However , high
r esolut ion measur ement ADCs such as t he AD77XX ser ies allow t he RTD out put t o
be digit ized dir ect ly. In t his manner , linear izat ion can be per for med digit ally,
t her eby easing t he analog cir cuit r equir ement s.
7.14
FOUR-WIRE OR KELVIN CONNECTION TO Pt RTD
FOR ACCURATE MEASUREMENTS
I
FORCE
LEAD
FORCE
LEAD
R
LEAD
R
LEAD
100
Pt RTD
SENSE
LEAD
SENSE
LEAD
TO HIGH - Z
IN-AMP OR ADC
Figure 7.15
Figur e 7.16 shows a 100 Pt RTD dr iven wit h a 400A excit at ion cur r ent sour ce.
The out put is digit ized by one of t he AD77XX ser ies ADCs. Not e t hat t he RTD
excit at ion cur r ent sour ce also gener at es t he 2.5V r efer ence volt age for t he ADC via
t he 6.25k r esist or . Var iat ions in t he excit at ion cur r ent do not affect t he cir cuit
accur acy, since bot h t he input volt age and t he r efer ence volt age var y r at iomet r ically
wit h t he excit at ion cur r ent . However , t he 6.25k r esist or must have a low
t emper at ur e coefficient t o avoid er r or s in t he measur ement . The high r esolut ion of
t he ADC and t he input PGA (gain of 1 t o 128) eliminat es t he need for addit ional
condit ioning cir cuit s.
The ADT70 is a complet e Pt RTD signal condit ioner which pr ovides an out put
volt age of 5mV/C when using a 1k RTD (see Figur e 7.17). The Pt RTD and t he
1k r efer ence r esist or ar e bot h excit ed wit h 1mA mat ched cur r ent sour ces. This
allows t emper at ur e measur ement s t o be made over a r ange of appr oximat ely 50C
t o +800C.
The ADT70 cont ains t he t wo mat ched cur r ent sour ces, a pr ecision r ail-t o-r ail out put
inst r ument at ion amplifier , a 2.5V r efer ence, and an uncommit t ed r ail-t o-r ail out put
op amp. The ADT71 is t he same as t he ADT70 except t he int er nal volt age r efer ence
is omit t ed. A shut down funct ion is included for bat t er y power ed equipment t hat
r educes t he quiescent cur r ent fr om 3mA t o 10A. The gain or full-scale r ange for t he
Pt RTD and ADT701 syst em is set by a pr ecision ext er nal r esist or connect ed t o t he
inst r ument at ion amplifier . The uncommit t ed op amp may be used for scaling t he
int er nal volt age r efer ence, pr oviding a "Pt RTD open" signal or "over t emper at ur e"
war ning, pr oviding a heat er swit ching signal, or ot her ext er nal condit ioning
det er mined by t he user . The ADT70 is specified for oper at ion fr om 40C t o +125C
and is available in 20-pin DIP and SOIC packages.
7.15
INTERFACING A Pt RTD TO A HIGH RESOLUTION ADC

ADC
OUTPUT
REGISTER
CONTROL
REGISTER
SERIAL
INTERFACE
PGA
3V OR 5V
(DEPENDING ON ADC)
AD77XX SERIES
(16-22 BITS)
TO MICROCONTROLLER
G=1 TO 128
400A
100
Pt RTD
+
AIN1+
AIN1
MUX
+VREF
VREF
R
REF
6.25k
Figure 7.16
CONDITIONING THE PLATINUM RTD USING THE ADT70
2.5V
REFERENCE
SHUT
DOWN
1k Pt
RTD
1k REF
RES
INST
AMP
R
G
= 50k
MATCHED
1mA SOURCES
+5V
-1V TO -5V
OUT = 5mV/ C
ADT70
GND
REF
Note: Some Pins Omitted
for Clarity
+
0.1F
Figure 7.17
7.16
THERMI STORS
Similar in funct ion t o t he RTD, t her mist or s ar e low-cost t emper at ur e-sensit ive
r esist or s and ar e const r uct ed of solid semiconduct or mat er ials which exhibit a
posit ive or negat ive t emper at ur e coefficient . Alt hough posit ive t emper at ur e
coefficient devices ar e available, t he most commonly used t her mist or s ar e t hose wit h
a negat ive t emper at ur e coefficient . Figur e 7.18 shows t he r esist ance-t emper at ur e
char act er ist ic of a commonly used NTC (Negat ive Temper at ur e Coefficient )
t her mist or . The t her mist or is highly non-linear and, of t he t hr ee t emper at ur e
sensor s discussed, is t he most sensit ive.
RESISTANCE CHARACTERISTICS OF A
10k NTC THERMISTOR
0
10
20
30
40
0 20 40 60 80 100
THERMISTOR
RESISTANCE
k
TEMPERATURE - C
Nominal Value @ 25 C
ALPHA THERMISTOR, INCORPORATED
RESISTANCE/TEMPERATURE CURVE 'A'
10 k THERMISTOR, #13A1002-C3
Figure 7.18
The t her mist or 's high sensit ivit y (t ypically, 44,000ppm/C at 25C, as shown in
Figur e 7.19), allows it t o det ect minut e var iat ions in t emper at ur e which could not be
obser ved wit h an RTD or t her mocouple. This high sensit ivit y is a dist inct advant age
over t he RTD in t hat 4-wir e Kelvin connect ions t o t he t her mist or ar e not needed t o
compensat e for lead wir e er r or s. To illust r at e t his point , suppose a 10k NTC
t her mist or , wit h a t ypical 25C t emper at ur e coefficient of 44,000ppm/C, wer e
subst it ut ed for t he 100 Pt RTD in t he example given ear lier , t hen a t ot al lead wir e
r esist ance of 21 would gener at e less t han 0.05C er r or in t he measur ement . This is
r oughly a fact or of 500 impr ovement in er r or over an RTD.
7.17
TEMPERATURE COEFFICIENT OF
10k NTC THERMISTOR
-20000
-30000
-40000
-50000
-60000
0 20 40 60 80 100
THERMISTOR
TEMPERATURE
COEFFICIENT
ppm/ C
TEMPERATURE - C
ALPHA THERMISTOR, INCORPORATED
RESISTANCE/TEMPERATURE CURVE 'A'
10 k THERMISTOR, #13A1002-C3
Figure 7.19
However , t he t her mist or 's high sensit ivit y t o t emper at ur e does not come wit hout a
pr ice. As was shown in Figur e 7.18, t he t emper at ur e coefficient of t her mist or s does
not decr ease linear ly wit h incr easing t emper at ur e as it does wit h RTDs; t her efor e,
linear izat ion is r equir ed for all but t he nar r owest of t emper at ur e r anges. Ther mist or
applicat ions ar e limit ed t o a few hundr ed degr ees at best because t hey ar e mor e
suscept ible t o damage at high t emper at ur es. Compar ed t o t her mocouples and RTDs,
t her mist or s ar e fr agile in const r uct ion and r equir e car eful mount ing pr ocedur es t o
pr event cr ushing or bond separ at ion. Alt hough a t her mist or 's r esponse t ime is shor t
due t o it s small size, it s small t her mal mass makes it ver y sensit ive t o self-heat ing
er r or s.
Ther mist or s ar e ver y inexpensive, highly sensit ive t emper at ur e sensor s. However ,
we have shown t hat a t her mist or 's t emper at ur e coefficient var ies fr om 44,000
ppm/C at 25C t o 29,000ppm/C at 100C. Not only is t his non-linear it y t he
lar gest sour ce of er r or in a t emper at ur e measur ement , it also limit s useful
applicat ions t o ver y nar r ow t emper at ur e r anges if linear izat ion t echniques ar e not
used.
It is possible t o use a t her mist or over a wide t emper at ur e r ange only if t he syst em
designer can t oler at e a lower sensit ivit y t o achieve impr oved linear it y. One appr oach
t o linear izing a t her mist or is simply shunt ing it wit h a fixed r esist or . Par alleling t he
t her mist or wit h a fixed r esist or incr eases t he linear it y significant ly. As shown in
Figur e 7.20, t he par allel combinat ion exhibit s a mor e linear var iat ion wit h
t emper at ur e compar ed t o t he t her mist or it self. Also, t he sensit ivit y of t he
combinat ion st ill is high compar ed t o a t her mocouple or RTD. The pr imar y
7.18
disadvant age t o t his t echnique is t hat linear izat ion can only be achieved wit hin a
nar r ow r ange.
LINEARIZATION OF NTC THERMISTOR
USING A 5.17k SHUNT RESISTOR
0
10
20
30
40
0 20 40 60 80 100
RESISTANCE
k
TEMPERATURE - C
THERMISTOR
PARALLEL COMBINATION
Figure 7.20
The value of t he fixed r esist or can be calculat ed fr om t he following equat ion:
R =
RT RT RT RT RT
RT RT RT
2 1 3 2 1 3
1 3 2 2
+
+
( )
,
wher e RT1 is t he t her mist or r esist ance at T1, t he lowest t emper at ur e in t he
measur ement r ange, RT3 is t he t her mist or r esist ance at T3, t he highest
t emper at ur e in t he r ange, and RT2 is t he t her mist or r esist ance at T2, t he midpoint ,
T2 = (T1 +T3)/2.
For a t ypical 10k NTC t her mist or , RT1 = 32,650 at 0C, RT2 = 6,532 at 35C,
and RT3 = 1,752 at 70C. This r esult s in a value of 5.17k for R. The accur acy
needed in t he signal condit ioning cir cuit r y depends on t he linear it y of t he net wor k.
For t he example given above, t he net wor k shows a non-linear it y of 2.3C/ + 2.0 C.
The out put of t he net wor k can be applied t o an ADC t o per for m fur t her linear izat ion
as shown in Figur e 7.21. Not e t hat t he out put of t he t her mist or net wor k has a slope
of appr oximat ely 10mV/C, which implies a 12-bit ADC has mor e t han sufficient
r esolut ion.
7.19
LINEARIZED THERMISTOR AMPLIFIER
10k NTC
THERMISTOR
5.17k
LINEARIZATION
RESISTOR
226A
LINEARITY 2C, 0C TO +70C
V
OUT
0.994V @ T = 0C
V
OUT
0.294V @ T =70C
V
OUT
/ T 10mV/C
AMPLIFIER
OR ADC
Figure 7.21
SEMI CONDUCTOR TEMP ERATURE SENSORS
Moder n semiconduct or t emper at ur e sensor s offer high accur acy and high linear it y
over an oper at ing r ange of about 55C t o +150C. Int er nal amplifier s can scale t he
out put t o convenient values, such as 10mV/C. They ar e also useful in cold-junct ion-
compensat ion cir cuit s for wide t emper at ur e r ange t her mocouples.
All semiconduct or t emper at ur e sensor s make use of t he r elat ionship bet ween a
bipolar junct ion t r ansist or 's (BJ T) base-emit t er volt age t o it s collect or cur r ent :
V
BE
kT
q
I
c
I
s
|
.
`
,
ln
wher e k is Bolt zmann's const ant , T is t he absolut e t emper at ur e, q is t he char ge of
an elect r on, and I
s
is a cur r ent r elat ed t o t he geomet r y and t he t emper at ur e of t he
t r ansist or s. (The equat ion assumes a volt age of at least a few hundr ed mV on t he
collect or , and ignor es Ear ly effect s.)
If we t ake N t r ansist or s ident ical t o t he fir st (see Figur e 7.22) and allow t he t ot al
cur r ent I
c
t o be shar ed equally among t hem, we find t hat t he new base-emit t er
volt age is given by t he equat ion
V
N
kT
q
I
c
N I
s
|
.
`
,
ln
7.20
BASIC RELATIONSHIPS FOR SEMICONDUCTOR
TEMPERATURE SENSORS
I
C
I
C
V
BE
V
N
V
BE
V
BE
V
N
kT
q
N = = = = ln( )
V
BE
kT
q
I
C
I
S
= =

ln V
N
kT
q
I
C
N I
S
= =

ln
INDEPENDENT OF I
C
, I
S
ONE TRANSISTOR
N TRANSISTORS
Figure 7.22
Neit her of t hese cir cuit s is of much use by it self because of t he st r ongly t emper at ur e
dependent cur r ent I
s
, but if we have equal cur r ent s in one BJ T and N similar BJ Ts
t hen t he expr ession for t he difference bet ween t he t wo base-emit t er volt ages is
pr opor t ional t o absolut e t emper at ur e and does not cont ain I
s
.
V
BE
V
BE
V
N
kT
q
I
c
I
s
kT
q
I
c
N I
s

|
.
`
,

|
.
`
,
ln ln
V
BE
V
BE
V
N
kT
q
I
c
I
s
I
c
N I
s

|
.
`
,

|
.
`
,
]
]
]
]
ln ln
V
BE
V
BE
V
N
kT
q
I
c
I
s
I
c
N I
s
kT
q
N
|
.
`
,
|
.
`
,
]
]
]
]
]
]
ln ln( )
The cir cuit shown in Figur e 7.23 implement s t he above equat ion and is known as
t he "Br okaw Cell" (see Refer ence 10). The volt age V
BE
= V
BE
V
N
appear s acr oss
r esist or R2. The emit t er cur r ent in Q2 is t her efor e V
BE
/R2. The op amp's ser vo
loop and t he r esist or s, R, for ce t he same cur r ent t o flow t hr ough Q1. The Q1 and Q2
cur r ent s ar e equal and ar e summed and flow int o r esist or R1. The cor r esponding
volt age developed acr oss R1 is pr opor t ional t o absolut e t emper at ur e (PTAT) and
given by:
7.21
( )
V
PTAT
V
BE
V
N
R
R
R
kT
q
N

2R1
2
2
1
2
ln( ) .
CLASSIC BANDGAP TEMPERATURE SENSOR
"BROKAW CELL" R R
+
I
2
I
1
Q2
NA
Q1
A
R2
R1
V
N
V
BE
(Q1)
V
BANDGAP
= 1.205V
+V
IN
V
PTAT
= 2
R1
R2
kT
q
ln(N)
V
BE
V
BE
V
N
kT
q
N = = = = ln( )
Figure 7.23
The bandgap cell r efer ence volt age, V
BANDGAP
, appear s at t he base of Q1 and is
t he sum of V
BE
(Q1) and V
PTAT
. V
BE(Q1)
is complement ar y t o absolut e
t emper at ur e (CTAT), and summing it wit h V
PTAT
causes t he bandgap volt age t o be
const ant wit h r espect t o t emper at ur e (assuming pr oper choice of R1/R2 r at io and N
t o make t he bandgap volt age equal t o1.205V). This cir cuit is t he basic band-gap
t emper at ur e sensor , and is widely used in semiconduct or t emper at ur e sensor s.
Cu r r en t a n d Volt a ge Ou t p u t Temp er a t u r e Sen sor s
The concept s used in t he bandgap t emper at ur e sensor discussion above can be used
as t he basis for a var iet y of IC t emper at ur e sensor s t o gener at e eit her cur r ent or
volt age out put s. The AD592 and TMP17 (see Figur e 7.24) ar e cur r ent out put
sensor s which have scale fact or s of 1A/K. The sensor s do not r equir e ext er nal
calibr at ion and ar e available in sever al accur acy gr ades. The AD592 is available in
t hr ee accur acy gr ades. The highest gr ade ver sion (AD592CN) has a maximum er r or
@25C of 0.5C and 1.0C er r or fr om 25C t o +105C. Linear it y er r or is 0.35C.
The TMP17 is available in t wo accur acy gr ades. The highest gr ade ver sion
(TMP17F) has a maximum er r or @25C of 2.5C and 3.5C er r or fr om 40C t o
+105C. Typical linear it y er r or is 0.5C. The AD592 is available in a TO-92 package
and t he TMP17 in an SO-8 package.
7.22
CURRENT OUTPUT SENSORS: AD592, TMP17
n 1A/K Scale Factor
n Nominal Output Current @ +25C: 298.2A
n Operation from 4V to 30V
n 0.5C Max Error @ 25C, 1.0C Error Over Temp,
0.1C Typical Nonlinearity (AD592CN)
n 2.5C Max Error @ 25C, 3.5C Error Over Temp,
0.5C Typical Nonlinearity (TMP17F)
n AD592 Specified from 25C to +105C
n TMP17 Specified from 40C to +105C
V+
V
AD592: TO-92 PACKAGE
TMP17: SO-8 PACKAGE
Figure 7.24
RATIOMETRIC VOLTAGE OUTPUT SENSORS
R(T)
I(V
S
)
AD22103
V
S
= +3.3V
REFERENCE
INPUT
ADC
+
GND
V
OUT
V
OUT
V
S
V
V
mV
C
T
A
= = + +

3 3
0 25
28
.
.
0.1F
Figure 7.25
7.23
In some cases, it is desir able for t he out put of a t emper at ur e sensor t o be r at iomet r ic
wit h it s supply volt age. The AD22103 (see Figur e 7.25) has an out put t hat is
r at iomet r ic wit h it s supply volt age (nominally 3.3V) accor ding t o t he equat ion:
V
OUT
V
S
V
V
mV
C
T
A
+

|
.
`
,
3 3
0 25
28
.
. .
The cir cuit shown in Figur e 7.25 uses t he AD22103 power supply as t he r efer ence t o
t he ADC, t her eby eliminat ing t he need for a pr ecision volt age r efer ence. The
AD22103 is specified over a r ange of 0C t o +100C and has an accur acy bet t er t han
2.5C and a linear it y bet t er t han 0.5C.
The TMP35/TMP36/TMP37 ar e low volt age (2.7V t o 5.5V) SOT-23 (5-pin), SO-8, or
TO-92 packaged volt age out put t emper at ur e sensor s wit h a 10mV/C (TMP35/36) or
20mV/C (TMP37) scale fact or (see Figur e 7.26). Supply cur r ent is below 50A,
pr oviding ver y low self-heat ing (less t han 0.1C in st ill air ). A shut down feat ur e is
pr ovided which r educes t he cur r ent t o 0.5A.
The TMP35 pr ovides a 250mV out put at +25C and r eads t emper at ur e fr om +10C
t o +125C. The TMP36 is specified fr om 40C t o +125C. and pr ovides a 750mV
out put at 25C. Bot h t he TMP35 and TMP36 have an out put scale fact or of
+10mV/C. The TMP37 is int ended for applicat ions over t he r ange +5C t o +100C,
and pr ovides an out put scale fact or of 20mV/C. The TMP37 pr ovides a 500mV
out put at +25C.
ABSOLUTE VOLTAGE OUTPUT SENSORS
WITH SHUTDOWN
n V
OUT
:
u TMP35, 250mV @ 25C, 10mV/C (+10C to +125C)
u TMP36, 750mV @ 25C, 10mV/C (40C to +125C)
u TMP37, 500mV @ 25C, 20mV/C ( +5C to +100C)
n 2C Error Over Temp (Typical), 0.5C Non-Linearity (Typical)
n Specified 40C to +125C
n 50A Quiescent Current, 0.5A in Shutdown Mode
TMP35
TMP36
TMP37
+V
S
= 2.7V TO 5.5V
V
OUT
SHUTDOWN
SOT-23-5
ALSO
SO-8
OR TO-92
0.1F
Figure 7.26
7.24
The ADT45/ADT50 ar e volt age out put t emper at ur e sensor s packaged in a SOT-23-3
package designed for an oper at ing volt age of 2.7V t o 12V (see Figur e 7.27). The
devices ar e specified over t he r ange of 40C t o +125C. The out put scale fact or for
bot h devices is 10mV/C. Typical accur acies ar e t1C at +25C and t2C over t he
40C t o +125C r ange. The ADT45 pr ovides a 250mV out put at +25C and is
specified for t emper at ur e fr om 0C t o +100C. The ADT50 pr ovides a 750mV out put
at +25C and is specified for t emper at ur e fr om 40C t o +125C.
ADT45/ADT50 ABSOLUTE VOLTAGE OUTPUT SENSORS
n V
OUT
:
u ADT45, 250mV @ 25C, 10mV/C Scale Factor
u ADT50, 750mV @ 25C, 10mV/C Scale Factor
n 2C Error Over Temp (Typical), 0.5C Non-Linearity (Typical)
n 60A Quiescent Current
ADT45
ADT50
+V
S
= 2.7V TO 12V
V
OUT
0.1F
SOT-23
Figure 7.27
If t he ADT45/ADT50 sensor s ar e t her mally at t ached and pr ot ect ed, t hey can be
used in any t emper at ur e measur ement applicat ion wher e t he maximum
t emper at ur e r ange of t he medium is bet ween 40C t o +125C. Pr oper ly cement ed
or glued t o t he sur face of t he medium, t hese sensor s will be wit hin 0.01C of t he
sur face t emper at ur e. Caut ion should be exer cised, as any wir ing t o t he device can
act as heat pipes, int r oducing er r or s if t he sur r ounding air -sur face int er face is not
isot her mal. Avoiding t his condit ion is easily achieved by dabbing t he leads of t he
sensor and t he hookup wir es wit h a bead of t her mally conduct ive epoxy. This will
ensur e t hat t he ADT45/ADT50 die t emper at ur e is not affect ed by t he sur r ounding
air t emper at ur e.
7.25
In t he SOT-23-3 package, t he t her mal r esist ance junct ion-t o-case,
J C
, is 180C/W.
The t her mal r esist ance case-t o-ambient ,
CA
, is t he differ ence bet ween
J A
and
J C
, and is det er mined by t he char act er ist ics of t he t her mal connect ion. Wit h no air
flow and t he device solder ed on a PC boar d,
J A
is 300C/W. The t emper at ur e
sensor 's power dissipat ion, P
D
, is t he pr oduct of t he t ot al volt age acr oss t he device
and it s t ot al supply cur r ent (including any cur r ent deliver ed t o t he load). The r ise in
die t emper at ur e above t he medium's ambient t emper at ur e is given by:
T
J
= P
D
(
J C
+
CA
) + T
A
.
Thus, t he die t emper at ur e r ise of an unloaded ADT45/ADT50 (SOT-23-3 package)
solder ed on a boar d in st ill air at 25C and dr iven fr om a +5V supply (quiescent
cur r ent = 60A, P
D
= 300W) is less t han 0.09C. In or der t o pr event fur t her
t emper at ur e r ise, it is impor t ant t o minimize t he load cur r ent , always keeping it less
t han 100A.
The t r ansient r esponse of t he ADT45/ADT50 sensor s t o a st ep change in
t emper at ur e is det er mined by t he t her mal r esist ances and t he t her mal mass of t he
die and t he case. The t her mal mass of t he case var ies wit h t he measur ement
medium since it includes anyt hing t hat is in dir ect cont act wit h t he package. In all
pr act ical cases, t he t her mal mass of t he case is t he limit ing fact or in t he t her mal
r esponse t ime of t he sensor and can be r epr esent ed by a single-pole RC t ime
const ant . Ther mal mass is oft en consider ed t he t her mal equivalent of elect r ical
capacit ance.
The t her mal t ime const ant of a t emper at ur e sensor is defined t o be t he t ime
r equir ed for t he sensor t o r each 63.2% of t he final value for a st ep change in t he
t emper at ur e. Figur e 7.28 shows t he t her mal t ime const ant of t he ADT45/ADT50
ser ies of sensor s wit h t he SOT-23-3 package solder ed t o 0.338" x 0.307" copper PC
boar d as a funct ion of air flow velocit y. Not e t he r apid dr op fr om 32 seconds t o 12
seconds as t he air velocit y incr eases fr om 0 (st ill air ) t o 100 LFPM. As a point of
r efer ence, t he t her mal t ime const ant of t he ADT45/ADT50 ser ies in a st ir r ed oil bat h
is less t han 1 second, which ver ifies t hat t he major par t of t he t her mal t ime const ant
is det er mined by t he case.
The power supply pin of t hese sensor s should be bypassed t o gr ound wit h a 0.1F
cer amic capacit or having ver y shor t leads (pr efer ably sur face mount ) and locat ed as
close t o t he power supply pin as possible. Since t hese t emper at ur e sensor s oper at e
on ver y lit t le supply cur r ent and could be exposed t o ver y host ile elect r ical
envir onment s, it is impor t ant t o minimize t he effect s of EMI/RFI on t hese devices.
The effect of RFI on t hese t emper at ur e sensor s is manifest ed as abnor mal DC shift s
in t he out put volt age due t o r ect ificat ion of t he high fr equency noise by t he int er nal
IC junct ions. In t hose cases wher e t he devices ar e oper at ed in t he pr esence of high
fr equency r adiat ed or conduct ed noise, a lar ge value t ant alum elect r olyt ic capacit or
(>2.2F) placed acr oss t he 0.1F cer amic may offer addit ional noise immunit y.
7.26
THERMAL RESPONSE IN FORCED AIR FOR SOT-23-3
0 100 200 300 400
500
600 700
0
5
10
15
20
25
30
35
AIR VELOCITY - LFPM
TIME
CONSTANT-
SECONDS
SOT-23-3 SOLDERED TO 0.338" x 0.307" Cu PCB
V+ = 2.7V TO 5V
NO LOAD
Figure 7.28
Di gi t a l Ou t p u t Temp er a t u r e Sen sor s
Temper at ur e sensor s which have digit al out put s have a number of advant ages over
t hose wit h analog out put s, especially in r emot e applicat ions. Opt o-isolat or s can also
be used t o pr ovide galvanic isolat ion bet ween t he r emot e sensor and t he
measur ement syst em. A volt age-t o-fr equency conver t er dr iven by a volt age out put
t emper at ur e sensor accomplishes t his funct ion, however , mor e sophist icat ed ICs ar e
now available which ar e mor e efficient and offer sever al per for mance advant ages.
The TMP03/TMP04 digit al out put sensor family includes a volt age r efer ence,
V
PTAT
gener at or , sigma-delt a ADC, and a clock sour ce (see Figur e 7.29). The
sensor out put is digit ized by a fir st -or der sigma-delt a modulat or , also known as t he
"char ge balance" t ype analog-t o-digit al conver t er . This conver t er ut ilizes t ime-
domain over sampling and a high accur acy compar at or t o deliver 12 bit s of effect ive
accur acy in an ext r emely compact cir cuit .
The out put of t he sigma-delt a modulat or is encoded using a pr opr iet ar y t echnique
which r esult s in a ser ial digit al out put signal wit h a mar k-space r at io for mat (see
Figur e 7.30) t hat is easily decoded by any micr opr ocessor int o eit her degr ees
cent igr ade or degr ees Fahr enheit , and r eadily t r ansmit t ed over a single wir e. Most
impor t ant ly, t his encoding met hod avoids major er r or sour ces common t o ot her
modulat ion t echniques, as it is clock-independent . The nominal out put fr equency is
35Hz at + 25C, and t he device oper at es wit h a fixed high-level pulse widt h (T1) of
10ms.
7.27
DIGITAL OUTPUT SENSORS: TMP03/04
REFERENCE
VOLTAGE
TEMP
SENSOR
VPTAT
SIGMA-DELTA
ADC
CLOCK
(1MHz)
OUTPUT
(TMP04)
OUTPUT
(TMP03)
TMP03/TMP04
+V
S
= 4.5 TO 7V
GND
Figure 7.29
TMP03/TMP04 OUTPUT FORMAT
n T1 Nominal Pulse Width = 10ms
n 1.5C Error Over Temp, 0.5C Non-Linearity (Typical)
n Nominal T1/T2 @ 0C = 60%
n Nominal Frequency @ +25C = 35Hz
n 6.5mW Power Consumption @ 5V
n TO-92, SO-8, or TSSOP Packages
T1 T2
TEMPERATURE C
T
T
( ) = =

235
400 1
2
TEMPERATURE F
T
T
( ) = =

455
720 1
2
Figure 7.30
7.28
The TMP03/TMP04 out put is a st r eam of digit al pulses, and t he t emper at ur e
infor mat ion is cont ained in t he mar k-space r at io per t he equat ions:
Temper at ur e C
T
T
( )
|
.
`
,
235
400 1
2
Temper at ur e F
T
T
( )
|
.
`
,
455
720 1
2
.
Popular micr ocont r oller s, such as t he 80C51 and 68HC11, have on-chip t imer s
which can easily decode t he mar k-space r at io of t he TMP03/TMP04. A t ypical
int er face t o t he 80C51 is shown in Figur e 7.31. Two t imer s, labeled Timer 0 and
Timer 1 ar e 16 bit s in lengt h. The 80C51's syst em clock, divided by t welve, pr ovides
t he sour ce for t he t imer s. The syst em clock is nor mally der ived fr om a cr yst al
oscillat or , so t iming measur ement s ar e quit e accur at e. Since t he sensor 's out put is
r at iomet r ic, t he act ual clock fr equency is not impor t ant . This feat ur e is impor t ant
because t he micr ocont r oller 's clock fr equency is oft en defined by some ext er nal
t iming const r aint , such as t he ser ial baud r at e.
INTERFACING TMP04 TO A MICROCONTROLLER
CPU
TIMER
CONTROL
OSCILLATOR 12
TIMER 0
TIMER 1
80C51 MICROCONTROLLER
TMP04
OUT
V+
GND
+5V
NOTE: ADDITIONAL
PINS OMITTED
FOR CLARITY
XTAL
P1.0
0.1F
Figure 7.31
Soft war e for t he sensor int er face is st r aight for war d. The micr ocont r oller simply
monit or s I/O por t P1.0, and st ar t s Timer 0 on t he r ising edge of t he sensor out put .
The micr ocont r oller cont inues t o monit or P1.0, st opping Timer 0 and st ar t ing Timer
1 when t he sensor out put goes low. When t he out put r et ur ns high, t he sensor 's T1
and T2 t imes ar e cont ained in r egist er s Timer 0 and Timer 1, r espect ively. Fur t her
soft war e r out ines can t hen apply t he conver sion fact or shown in t he equat ions above
and calculat e t he t emper at ur e.
7.29
The TMP03/TMP04 ar e ideal for monit or ing t he t her mal envir onment wit hin
elect r onic equipment . For example, t he sur face mount ed package will accur at ely
r eflect t he t her mal condit ions which affect near by int egr at ed cir cuit s. The TO-92
package, on t he ot her hand, can be mount ed above t he sur face of t he boar d t o
measur e t he t emper at ur e of t he air flowing over t he boar d.
The TMP03 and TMP04 measur e and conver t t he t emper at ur e at t he sur face of
t heir own semiconduct or chip. When t hey ar e used t o measur e t he t emper at ur e of a
near by heat sour ce, t he t her mal impedance bet ween t he heat sour ce and t he sensor
must be consider ed. Oft en, a t her mocouple or ot her t emper at ur e sensor is used t o
measur e t he t emper at ur e of t he sour ce, while t he TMP03/TMP04 t emper at ur e is
monit or ed by measur ing T1 and T2. Once t he t her mal impedance is det er mined, t he
t emper at ur e of t he heat sour ce can be infer r ed fr om t he TMP03/TMP04 out put .
One example of using t he TMP04 t o monit or a high power dissipat ion
micr opr ocessor or ot her IC is shown in Figur e 7.32. The TMP04, in a sur face mount
package, is mount ed dir ect ly beneat h t he micr opr ocessor 's pin gr id ar r ay (PGA)
package. In a t ypical applicat ion, t he TMP04's out put would be connect ed t o an
ASIC wher e t he mar k-space r at io would be measur ed. The TMP04 pulse out put
pr ovides a significant advant age in t his applicat ion because it pr oduces a linear
t emper at ur e out put , while needing only one I/O pin and wit hout r equir ing an ADC.
MONITORING HIGH POWER MICROPROCESSOR
OR DSP WITH TMP04
FAST MICROPROCESSOR, DSP, ETC.,
IN PGA PACKAGE
PGA SOCKET
PC BOARD
TMP04 IN SURFACE
MOUNT PACKAGE
Figure 7.32
Th er most a t i c Swi t ch es a n d Set p oi n t Con t r oller s
Temper at ur e sensor s used in conjunct ion wit h compar at or s can act as t her most at ic
swit ches. ICs such as t he ADT05 accomplish t his funct ion at low cost and allow a
single ext er nal r esist or t o pr ogr am t he set point t o 2C accur acy over a r ange of
40C t o +150C (see Figur e 7.33). The device asser t s an open collect or out put when
t he ambient t emper at ur e exceeds t he user -pr ogr ammed set point t emper at ur e. The
ADT05 has appr oximat ely 4C of hyst er esis which pr event s r apid t her mal on/off
cycling. The ADT05 is designed t o oper at e on a single supply volt age fr om +2.7V t o
7.30
+7.0V facilit at ing oper at ion in bat t er y power ed applicat ions as well as indust r ial
cont r ol syst ems. Because of low power dissipat ion (200W @3.3V), self-heat ing
er r or s ar e minimized, and bat t er y life is maximized. An opt ional int er nal 200k
pull-up r esist or is included t o facilit at e dr iving light loads such as CMOS input s.
The set point r esist or is det er mined by t he equat ion:
R
SET
M C
T
SET
C C
k
+

39
281 6
90 3
( ) .
. .
The set point r esist or should be connect ed dir ect ly bet ween t he R
SET
pin (Pin 4) and
t he GND pin (Pin 5). If a gr ound plane is used, t he r esist or may be connect ed
dir ect ly t o t his plane at t he closest available point .
The set point r esist or can be of near ly any r esist or t ype, but it s init ial t oler ance and
t her mal dr ift will affect t he accur acy of t he pr ogr ammed swit ching t emper at ur e. For
most applicat ions, a 1% met al-film r esist or will pr ovide t he best t r adeoff bet ween
cost and accur acy. Once R
SET
has been calculat ed, it may be found t hat t he
calculat ed value does not agr ee wit h r eadily available st andar d r esist or s of t he
chosen t oler ance. In or der t o achieve a value as close as possible t o t he calculat ed
value, a compound r esist or can be const r uct ed by connect ing t wo r esist or s in ser ies
or par allel.
ADT05 THERMOSTATIC SWITCH
n 2C Setpoint Accuracy
n 4C Preset Hysteresis
n Specified Operating Range: 40C to + 150C
n Power Dissipation: 200W @ 3.3V
SET-
POINT
TEMP
SENSOR
200k
R
SET
+V
S
= 2.7V TO 7V
OUT
R
PULL-UP
ADT05
SOT-23-5
0.1F
Figure 7.33
7.31
The TMP01 is a dual set point t emper at ur e cont r oller which also gener at es a PTAT
out put volt age (see Figur e 7.34 and 7.35). It also gener at es a cont r ol signal fr om one
of t wo out put s when t he device is eit her above or below a specific t emper at ur e
r ange. Bot h t he high/low t emper at ur e t r ip point s and hyst er esis band ar e
det er mined by user -select ed ext er nal r esist or s.
TMP01 PROGRAMMABLE SETPOINT CONTROLLER
VPTAT
+
TEMPERATURE
SENSOR AND
VOLTAGE
REFERENCE
+
HYSTERESIS
GENERATOR
OVER
UNDER
V+
2.5V
VREF
SET
HIGH
SET
LOW
R1
R2
R3
GND
WINDOW
COMPARATOR
TMP01
Figure 7.34
The TMP01 consist s of a bandgap volt age r efer ence combined wit h a pair of mat ched
compar at or s. The r efer ence pr ovides bot h a const ant 2.5V out put and a PTAT
out put volt age which has a pr ecise t emper at ur e coefficient of 5mV/K and is 1.49V
(nominal) at +25C. The compar at or s compar e VPTAT wit h t he ext er nally set
t emper at ur e t r ip point s and gener at e an open-collect or out put signal when one of
t heir r espect ive t hr esholds has been exceeded.
Hyst er esis is also pr ogr ammed by t he ext er nal r esist or chain and is det er mined by
t he t ot al cur r ent dr awn out of t he 2.5V r efer ence. This cur r ent is mir r or ed and used
t o gener at e a hyst er esis offset volt age of t he appr opr iat e polar it y aft er a compar at or
has been t r ipped. The compar at or s ar e connect ed in par allel, which guar ant ees t hat
t her e is no hyst er esis over lap and eliminat es er r at ic t r ansit ions bet ween adjacent
t r ip zones.
7.32
The TMP01 ut ilizes laser t r immed t hin-film r esist or s t o maint ain a t ypical
t emper at ur e accur acy of t1C over t he r at ed t emper at ur e r ange. The open-collect or
out put s ar e capable of sinking 20mA, enabling t he TMP01 t o dr ive cont r ol r elays
dir ect ly. Oper at ing fr om a +5V supply, quiescent cur r ent is only 500A maximum.
TMP01 SETPOINT CONTROLLER KEY FEATURES
n V
C
: 4.5 to 13.2V
n Temperature Output: VPTAT, +5mV/K
n Nominal 1.49V Output @ 25C
n 1C Typical Accuracy Over Temperature
n Specified Operating Range: 55C to + 125C
n Resistor-Programmable Hysteresis
n Resistor-Programmable Setpoints
n Precision 2.5V 8mV Reference
n 400A Quiescent Current, 1A in Shutdown
n Packages: 8-Pin Dip, 8-Pin SOIC, 8-Pin TO-99
n Other Setpoint Controllers:
u Dual Setpoint Controllers: ADT22/ADT23
(3V Versions of TMP01 with Internal Hysteresis)
u Quad Setpoint Controller: ADT14
Figure 7.35
The ADT22/23-ser ies ar e similar t o t he TMP01 but have int er nal hyst er esis and ar e
designed t o oper at e on a 3V supply. A quad (ADT14) set point cont r oller is also
available.
ADCs Wi t h On -Ch i p Temp er a t u r e Sen sor s
The AD7816/7817/7818-ser ies digit al t emper at ur e sensor s have on-boar d
t emper at ur e sensor s whose out put s ar e digit ized by a 10-bit 9s conver sion t ime
swit ched capacit or SAR ADC. The ser ial int er face is compat ible wit h t he Int el 8051,
Mot or ola SPI and QSPI, and Nat ional Semiconduct or 's MICROWIRE
pr ot ocol. The device family offer s a var iet y of input opt ions for fur t her flexibilit y.
The AD7416/7417/7418 ar e similar but have st andar d ser ial int er faces. Funct ional
block diagr ams of t he AD7816, AD7817, and AD7818 ar e shown in Figur es 7.36, 37,
and 38, and key specificat ions in Figur e 7.39
7.33
AD7816 10-BIT DIGITAL TEMPERATURE SENSOR
WITH SERIAL INTERFACE
2.5V
REF
10-BIT
CHARGE
REDISTRIBUTION
SAR ADC
TEMP
SENSOR
OVER TEMP
REGISTER
A > B
CLOCK
+V
DD
= 2.7V TO 5.5V
OTI
SCLK
D
IN/OUT
AGND
RD/WR
CONVST
MUX
REF
IN
CONTROL
REGISTER
OUTPUT
REGISTER
AD7816
Figure 7.36
AD7817 10-BIT MUXED INPUT ADC WITH TEMP SENSOR
2.5V
REF
10-BIT
CHARGE
REDISTRIBUTION
SAR ADC
TEMP
SENSOR
OVER TEMP
REGISTER
CONTROL
REGISTER
A > B
CLOCK
+V
DD
= 2.7V TO 5.5V
OTI
SCLK
D
OUT
AGND
RD/WR
CONVST
MUX
REF
IN
DGND BUSY
V
IN1
V
IN2
V
IN3
V
IN4
CS
OUTPUT
REGISTER
D
IN
AD7817
Figure 7.37
7.34
AD7818 SINGLE INPUT 10-BIT ADC WITH TEMP SENSOR
2.5V
REF
10-BIT
CHARGE
REDISTRIBUTION
SAR ADC
TEMP
SENSOR
OVER TEMP
REGISTER
A > B
CLOCK
+V
DD
= 2.7V TO 5.5V
OTI
SCLK
AGND CONVST
MUX
CONTROL
REGISTER
OUTPUT
REGISTER
V
IN1
D
IN/OUT
RD/WR
AD7818
Figure 7.38
AD7816/7817/7818 - SERIES TEMP SENSOR
10-BIT ADCs WITH SERIAL INTERFACE
n 10-Bit ADC with 9s Conversion Time
n Flexible Serial Interface (Intel 8051, Motorola SPI and QSPI,
National MICROWIRE)
n On-Chip Temperature Sensor: 55C to +125C
n Temperature Accuracy: 2C from 40C to +85C
n On-Chip Voltage Reference: 2.5V 1%
n +2.7V to +5.5V Power Supply
n 4W Power Dissipation at 10Hz Sampling Rate
n Auto Power Down after Conversion
n Over-Temp Interrupt Output
n Four Single-Ended Analog Input Channels: AD7817
n One Single-Ended Analog Input Channel: AD7818
n AD7416/7417/7418: Similar, but have I
2
C Compatible Interface
Figure 7.39
7.35
MI CROP ROCESSOR TEMP ERATURE MONI TORI NG
Today's comput er s r equir e t hat har dwar e as well as soft war e oper at e pr oper ly, in
spit e of t he many t hings t hat can cause a syst em cr ash or lockup. The pur pose of
har dwar e monit or ing is t o monit or t he cr it ical it ems in a comput ing syst em and t ake
cor r ect ive act ion should pr oblems occur .
Micr opr ocessor supply volt age and t emper at ur e ar e t wo cr it ical par amet er s. If t he
supply volt age dr ops below a specified minimum level, fur t her oper at ions should be
halt ed unt il t he volt age r et ur ns t o accept able levels. In some cases, it is desir able t o
r eset t he micr opr ocessor under "br ownout " condit ions. It is also common pr act ice t o
r eset t he micr opr ocessor on power -up or power -down. Swit ching t o a bat t er y backup
may be r equir ed if t he supply volt age is low.
Under low volt age condit ions it is mandat or y t o inhibit t he micr opr ocessor fr om
wr it ing t o ext er nal CMOS memor y by inhibit ing t he Chip Enable signal t o t he
ext er nal memor y.
Many micr opr ocessor s can be pr ogr ammed t o per iodically out put a "wat chdog"
signal. Monit or ing t his signal gives an indicat ion t hat t he pr ocessor and it s soft war e
ar e funct ioning pr oper ly and t hat t he pr ocessor is not st uck in an endless loop.
The need for har dwar e monit or ing has r esult ed in a number of ICs, t r adit ionally
called "micr opr ocessor super visor y pr oduct s," which per for m some or all of t he above
funct ions. These devices r ange fr om simple manual r eset gener at or s (wit h
debouncing) t o complet e micr ocont r oller -based monit or ing sub-syst ems wit h on-chip
t emper at ur e sensor s and ADCs. Analog Devices' ADM-family of pr oduct s is
specifically t o per for m t he var ious micr opr ocessor super visor y funct ions r equir ed in
differ ent syst ems.
CPU t emper at ur e is cr it ically impor t ant in t he Pent ium II micr opr ocessor s. For t his
r eason, all new Pent ium II devices have an on-chip subst r at e PNP t r ansist or which
is designed t o monit or t he act ual chip t emper at ur e. The collect or of t he subst r at e
PNP is connect ed t o t he subst r at e, and t he base and emit t er ar e br ought out on t wo
separ at e pins of t he Pent ium II.
The ADM1021 Micr opr ocessor Temper at ur e Monit or is specifically designed t o
pr ocess t hese out put s and conver t t he volt age int o a digit al wor d r epr esent ing t he
chip t emper at ur e. The simplified analog signal pr ocessing por t ion of t he ADM1021
is shown in Figur e 7.40.
The t echnique used t o measur e t he t emper at ur e is ident ical t o t he "V
BE
" pr inciple
pr eviously discussed. Two differ ent cur r ent s (I and NI)ar e applied t o t he sensing
t r ansist or , and t he volt age measur ed for each. In t he ADM1021, t he nominal
cur r ent s ar e I = 6A, (N = 17), NI = 102A. The change in t he base-emit t er volt age,
V
BE
, is a PTAT volt age and given by t he equat ion:
V
BE
kT
q
N ln( ) .
7.36
Figur e 7.40 shows t he ext er nal sensor as a subst r at e t r ansist or , pr ovided for
t emper at ur e monit or ing in t he micr opr ocessor , but it could equally well be a discr et e
t r ansist or . If a discr et e t r ansist or is used, t he collect or should be connect ed t o t he
base and not gr ounded. To pr event gr ound noise int er fer ing wit h t he measur ement ,
t he mor e negat ive t er minal of t he sensor is not r efer enced t o gr ound, but is biased
above gr ound by an int er nal diode. If t he sensor is oper at ing in a noisy envir onment ,
C may be opt ionally added as a noise filt er . It s value is t ypically 2200pF, but should
be no mor e t han 3000pF.
ADM1021 MICROPROCESSOR TEMPERATURE MONITOR
INPUT SIGNAL CONDITIONING CIRCUITS
65kHz
LOWPASS
FILTER
OSCILLATOR
CHOPPER
AMPLIFIER
AND RECTIFIER
TO ADC
GAIN
=G
I N I
V
OUT
V
OUT
= G
kT
q
ln N
P
REMOTE
SENSING
TRANSISTOR
SPNP
I
BIAS
BIAS
DIODE
C
V
DD
= +3V TO +5.5V
kT
q
ln N V
BE
=
D+
D
Figure 7.40
To measur e V
BE
, t he sensing t r ansist or is swit ched bet ween oper at ing cur r ent s of
I and NI. The r esult ing wavefor m is passed t hr ough a 65kHz lowpass filt er t o
r emove noise, t hen t o a chopper -st abilized amplifier which per for ms t he funct ion of
amplificat ion and synchr onous r ect ificat ion. The r esult ing DC volt age is pr opor t ional
t o V
BE
and is digit ized by an 8-bit ADC. To fur t her r educe t he effect s of noise,
digit al filt er ing is per for med by aver aging t he r esult s of 16 measur ement cycles.
7.37
In addit ion, t he ADM1021 cont ains an on-chip t emper at ur e sensor , and it s signal
condit ioning and measur ement is per for med in t he same manner .
One LSB of t he ADC cor r esponds t o 1C, so t he ADC can t heor et ically measur e fr om
128C t o +127C, alt hough t he pr act ical lowest value is limit ed t o 65C due t o
device maximum r at ings. The r esult s of t he local and r emot e t emper at ur e
measur ement s ar e st or ed in t he local and r emot e t emper at ur e value r egist er s, and
ar e compar ed wit h limit s pr ogr ammed int o t he local and r emot e high and low limit
r egist er s as shown in Figur e 7.41. An ALERT out put signals when t he on-chip or
r emot e t emper at ur e is out of r ange. This out put can be used as an int er r upt , or as
an SMBus aler t .
The limit r egist er s can be pr ogr ammed, and t he device cont r olled and configur ed, via
t he ser ial Syst em Management Bus (SMBus). The cont ent s of any r egist er can also
be r ead back by t he SMBus. Cont r ol and configur at ion funct ions consist of:
swit ching t he device bet ween nor mal oper at ion and st andby mode, masking or
enabling t he ALERT out put , and select ing t he conver sion r at e which can be set
fr om 0.0625Hz t o 8Hz.
STATUS
REGISTER
ADM1021 SIMPLIFIED BLOCK DIAGRAM
ADDRESS POINTER
REGISTER
ONE-SHOT
REGISTER
CONVERSION RATE
REGISTER
LOCAL TEMPERATURE
LOW LIMIT REGISTER
LOCAL TEMPERATURE
HIGH LIMIT REGISTER
REMOTE TEMPERATURE
LOW LIMIT REGISTER
REMOTE TEMPERATURE
HIGH LIMIT REGISTER
CONFIGURATION
REGISTER
INTERRUPT
MASKING
SMBUS INTERFACE
LOCAL TEMPERATURE
LOW LIMIT COMPARATOR
LOCAL TEMPERATURE
HIGH LIMIT COMPARATOR
REMOTE TEMPERATURE
LOW LIMIT COMPARATOR
REMOTE TEMPERATURE
HIGH LIMIT COMPARATOR
LOCAL TEMPERATURE
VALUE REGISTER
REMOTE TEMPERATURE
VALUE REGISTER
SIGNAL CONDITIONING
AND ANALOG MUX
8-BIT
ADC
TEMP
SENSOR
D+
D
TEST V
DD
NC GND GND NC NC TEST SDATA SCLK ADD0 ADD1
STBY
ALERT
RUN/STANDBY
B
U
S
Y
EXTERNAL DIODE OPEN CIRCUIT
Figure 7.41
7.38
ADM1021 KEY SPECIFICATIONS
n On-Chip and Remote Temperature Sensing
n 1C Accuracy for On-Chip Sensor
n 3C Accuracy for Remote Sensor
n Programmable Over / Under Temperature Limits
n 2-Wire SMBus Serial Interface
n 70A Max Operating Current
n 3A Standby Current
n +3V to +5.5V Supplies
n 16-Pin QSOP Package
Figure 7.42
7.39
REF ERENCES
5. J im Williams, Thermocouple Measurement, Li n ea r Tech n ology
Ap p li ca t i on Not e 28, Linear Technology Cor por at ion.
6. Dan Sheingold, Non li n ea r Ci r cu i t s Ha n d b ook , Analog Devices, Inc.
7. J ames Wong, Temperature Measurements Gain from Advances in High-
precision Op Amps, Elect r on i c Desi gn , 15 May 1986.
8. OMEGA Temperature Measurement Handbook, Omega Inst r ument s, Inc.
9. Ha n d b ook of Ch emi st r y a n d P h ysi cs, Chemical Rubber Co.
10. Paul Br okaw, A S imple Three-Terminal IC Bandgap Voltage Reference,
I EEE J ou r n a l of Soli d St a t e Ci r cu i t s, Vol. SC-9, December , 1974.
ADCS FOR SI GNAL CONDI TI ONI NG
8.1
SECTI ON 8
ADCs FOR SI GNAL CONDI TI ONI NG
Wa l t Kest er , J a m es Br ya n t , J oe Bu xt on
The t r end in ADCs and DACs is t owar d higher speeds and higher r esolut ions at
r educed power levels. Moder n dat a conver t er s gener ally oper at e on 5V (dual
supply) or +5V (single supply). In fact , many new conver t er s oper at e on a single +3V
supply. This t r end has cr eat ed a number of design and applicat ions pr oblems which
wer e much less impor t ant in ear lier dat a conver t er s, wher e 15V supplies and 10V
input r anges wer e t he st andar d.
Lower supply volt ages imply smaller input volt age r anges, and hence mor e
suscept ibilit y t o noise fr om all pot ent ial sour ces: power supplies, r efer ences, digit al
signals, EMI/RFI, and pr obably most impor t ant , impr oper layout , gr ounding, and
decoupling t echniques. Single-supply ADCs oft en have an input r ange which is not
r efer enced t o gr ound. Finding compat ible single-supply dr ive amplifier s and dealing
wit h level shift ing of t he input signal in dir ect -coupled applicat ions also becomes a
challenge.
In spit e of t hese issues, component s ar e now available which allow ext r emely high
r esolut ions at low supply volt ages and low power . This sect ion discusses t he
applicat ions pr oblems associat ed wit h such component s and shows t echniques for
successfully designing t hem int o syst ems.
The most popular pr ecision signal condit ioning ADCs ar e based on t wo fundament al
ar chit ect ur es: successive approximation and sigma-delta. We have seen t hat t he
tracking ADC ar chit ect ur e is par t icular ly suit ed for r esolver -t o-digit al conver t er s,
but it is r ar ely used in ot her pr ecision signal condit ioning applicat ions. The flash
conver t er and t he subranging (or pipelined) conver t er ar chit ect ur es ar e widely used
wher e sampling fr equencies ext end int o t he megaher t z and hundr eds of megaher t z
r egion, but ar e over kill's in bot h speed and cost for low fr equency pr ecision signal
condit ioning applicat ions.
LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES
n Typical Supply Voltages: 5V, +5V, +5/+3V, +3V
n Lower Signal Swings Increase Sensitivity to
All Types of Noise (Device, Power Supply, Logic, etc.)
n Device Noise Increases at Low Currents
n Common Mode Input Voltage Restrictions
n Input Buffer Amplifier Selection Critical
n Auto-Calibration Modes Desirable at High Resolutions
Figure 8.1
8.2
ADCs FOR SIGNAL CONDITIONING
n Successive Approximation
u Resolutions to 16-bits
u Minimal Throughput Delay Time
u Used in Multiplexed Data Acquisition Systems
n Sigma-Delta
u Resolutions to 24-bits
u Excellent Differential Linearity
u Internal Digital Filter, Excellent AC Line Rejection
u Long Throughput Delay Time
u Difficult to Multiplex Inputs Due to Digital Filter Settling Time
n High Speed Architectures:
u Flash Converter
u Subranging or Pipelined
Figure 8.2
SUCCESSI VE AP P ROXI MATI ON ADCS
The successive appr oximat ion ADC has been t he mainst ay of signal condit ioning for
many year s. Recent design impr ovement s have ext ended t he sampling fr equency of
t hese ADCs int o t he megaher t z r egion. The use of int er nal swit ched capacit or
t echniques along wit h aut o calibr at ion t echniques ext end t he r esolut ion of t hese
ADCs t o 16-bit s on st andar d CMOS pr ocesses wit hout t he need for expensive t hin-
film laser t r imming.
The basic successive appr oximat ion ADC is shown in Figur e 8.3. It per for ms
conver sions on command. On t he asser t ion of t he CONVERT START command, t he
sample-and-hold (SHA) is placed in t he hold mode, and all t he bit s of t he successive
appr oximat ion r egist er (SAR) ar e r eset t o "0" except t he MSB which is set t o "1".
The SAR out put dr ives t he int er nal DAC. If t he DAC out put is gr eat er t han t he
analog input , t his bit in t he SAR is r eset , ot her wise it is left set . The next most
significant bit is t hen set t o "1". If t he DAC out put is gr eat er t han t he analog input ,
t his bit in t he SAR is r eset , ot her wise it is left set . The pr ocess is r epeat ed wit h each
bit in t ur n. When all t he bit s have been set , t est ed, and r eset or not as appr opr iat e,
t he cont ent s of t he SAR cor r espond t o t he value of t he analog input , and t he
conver sion is complet e.
The end of conver sion is gener ally indicat ed by an end-of-conver t (EOC), dat a-r eady
(DRDY), or a busy signal (act ually, not-BUSY indicat es end of conver sion). The
polar it ies and name of t his signal may be differ ent for differ ent SAR ADCs, but t he
fundament al concept is t he same. At t he beginning of t he conver sion int er val, t he
signal goes high (or low) and r emains in t hat st at e unt il t he conver sion is complet ed,
8.3
at which t ime it goes low (or high). The t r ailing edge is gener ally an indicat ion of
valid out put dat a.
SUCCESSIVE APPROXIMATION ADC
SHA
SUCCESSIVE
APPROXIMATION
REGISTER
(SAR)
DAC
TIMING
CONVERT
START
EOC,
DRDY,
OR BUSY
OUTPUT
ANALOG
INPUT
COMPARATOR
Figure 8.3
An N-bit conver sion t akes N st eps. It would seem on super ficial examinat ion t hat a
16-bit conver t er would have t wice t he conver sion t ime of an 8-bit one, but t his is not
t he case. In an 8-bit conver t er , t he DAC must set t le t o 8-bit accur acy befor e t he bit
decision is made, wher eas in a 16-bit conver t er , it must set t le t o 16-bit accur acy,
which t akes a lot longer . In pr act ice, 8-bit successive appr oximat ion ADCs can
conver t in a few hundr ed nanoseconds, while 16-bit ones will gener ally t ake sever al
micr oseconds.
Not ice t hat t he over all accur acy and linear it y of t he SAR ADC is det er mined
pr imar ily by t he int er nal DAC. Unt il r ecent ly, most pr ecision SAR ADCs used laser -
t r immed t hin-film DACs t o achieve t he desir ed accur acy and linear it y. The t hin-film
r esist or t r imming pr ocess adds cost , and t he t hin-film r esist or values may be
affect ed when subject ed t o t he mechanical st r esses of packaging.
For t hese r easons, swit ched capacit or (or char ge-r edist r ibut ion) DACs have become
popular in newer SAR ADCs. The advant age of t he swit ched capacit or DAC is t hat
t he accur acy and linear it y is pr imar ily det er mined by phot olit hogr aphy, which in
t ur n cont r ols t he capacit or plat e ar ea and t he capacit ance as well as mat ching. In
addit ion, small capacit or s can be placed in par allel wit h t he main capacit or s which
can be swit ched in and out under cont r ol of aut ocalibr at ion r out ines t o achieve high
accur acy and linear it y wit hout t he need for t hin-film laser t r imming. Temper at ur e
t r acking bet ween t he swit ched capacit or s can be bet t er t han 1ppm/C, t her eby
offer ing a high degr ee of t emper at ur e st abilit y.
8.4
A simple 3-bit capacit or DAC is shown in Figur e 8.4. The swit ches ar e shown in t he
track, or sample mode wher e t he analog input volt age, A
IN
, is const ant ly char ging
and dischar ging t he par allel combinat ion of all t he capacit or s. The hold mode is
init iat ed by opening S
IN
, leaving t he sampled analog input volt age on t he capacit or
ar r ay. Swit ch S
C
is t hen opened allowing t he volt age at node A t o move as t he bit
swit ches ar e manipulat ed. If S1, S2, S3, and S4 ar e all connect ed t o gr ound, a
volt age equal t o A
IN
appear s at node A. Connect ing S1 t o V
REF
adds a volt age
equal t o V
REF
/2 t o A
IN
. The compar at or t hen makes t he MSB bit decision, and
t he SAR eit her leaves S1 connect ed t o V
REF
or connect s it t o gr ound depending on
t he compar at or out put (which is high or low depending on whet her t he volt age at
node A is negat ive or posit ive, r espect ively). A similar pr ocess is followed for t he
r emaining t wo bit s. At t he end of t he conver sion int er val, S1, S2, S3, S4, and S
IN
ar e connect ed t o A
IN
, S
C
is connect ed t o gr ound, and t he conver t er is r eady for
anot her cycle.
3-BIT SWITCHED CAPACITOR DAC
_
+
C/ 4 C/ 2 C C/ 4
A
IN
V
REF
S
IN
S
C
S1 S2 S3 S4
BIT1
(MSB)
BIT2 BIT3
(LSB)
SWITCHES SHOWN IN TRACK (SAMPLE) MODE
A
C
TOTAL
= 2C
Figure 8.4
Not e t hat t he ext r a LSB capacit or (C/4 in t he case of t he 3-bit DAC) is r equir ed t o
make t he t ot al value of t he capacit or ar r ay equal t o 2C so t hat binar y division is
accomplished when t he individual bit capacit or s ar e manipulat ed.
The oper at ion of t he capacit or DAC (cap DAC) is similar t o an R/2R r esist ive DAC.
When a par t icular bit capacit or is swit ched t o V
REF
, t he volt age divider cr eat ed by
t he bit capacit or and t he t ot al ar r ay capacit ance (2C) adds a volt age t o node A equal
t o t he weight of t hat bit . When t he bit capacit or is swit ched t o gr ound, t he same
volt age is subt r act ed fr om node A.
8.5
Because of t heir popular it y, successive appr oximat ion ADCs ar e available in a wide
var iet y of r esolut ions, sampling r at es, input and out put opt ions, package st yles, and
cost s. It would be impossible t o at t empt t o list all t ypes, but Figur e 8.5 shows a
number of r ecent Analog Devices' SAR ADCs which ar e r epr esent at ive. Not e t hat
many devices ar e complet e dat a acquisit ion syst ems wit h input mult iplexer s which
allow a single ADC cor e t o pr ocess mult iple analog channels.
RESOLUTION / CONVERSION TIME COMPARISON
FOR REPRESENTATIVE SINGLE-SUPPLY SAR ADCs
AD7472
AD7891
AD7858/59
AD7887/88
AD7856/57
AD974
AD7670
RESOLUTION
12-BITS
12-BITS
12-BITS
12-BITS
14-BITS
16-BITS
16-BITS
SAMPLING
RATE
1.5MSPS
500kSPS
200kSPS
125kSPS
285kSPS
200kSPS
1MSPS
POWER
9mW
85mW
20mW
3.5mW
60mW
120mW
250mW
CHANNELS
1
8
8
8
8
4
1
Figure 8.5
While t her e ar e some var iat ions, t he fundament al t iming of most SAR ADCs is
similar and r elat ively st r aight for war d (see Figur e 8.6). The conver sion pr ocess is
init iat ed by asser t ing a CONVERT START signal. The CONVST signal is a
negat ive-going pulse whose posit ive-going edge act ually init iat es t he conver sion. The
int er nal sample-and-hold (SHA) amplifier is placed in t he hold mode on t his edge,
and t he var ious bit s ar e det er mined using t he SAR algor it hm. The negat ive-going
edge of t he CONVST pulse causes t he EOC or BUSY line t o go high. When t he
conver sion is complet e, t he BUSY line goes low, indicat ing t he complet ion of t he
conver sion pr ocess. In most cases t he t r ailing edge of t he BUSY line can be used as
an indicat ion t hat t he out put dat a is valid and can be used t o st r obe t he out put dat a
int o an ext er nal r egist er . However , because of t he many var iat ions in t er minology
and design, t he individual dat a sheet should always be consult ed when using wit h a
specific ADC.
It should also be not ed t hat some SAR ADCs r equir e an ext er nal high fr equency
clock in addit ion t o t he CONVERT START command. In most cases, t her e is no need
t o synchr onize t he t wo. The fr equency of t he ext er nal clock, if r equir ed, gener ally
falls in t he r ange of 1MHz t o 30MHz depending on t he conver sion t ime and
r esolut ion of t he ADC. Ot her SAR ADCs have an int er nal oscillat or which is used t o
per for m t he conver sions and only r equir e t he CONVERT START command. Because
8.6
of t heir ar chit ect ur e, SAR ADCs allow single-shot conver sion at any r epet it ion r at e
fr om DC t o t he conver t er 's maximum conver sion r at e.
TYPICAL SAR ADC TIMING
CONVST
CONVERSION
TIME
SAMPLE X SAMPLE X+1 SAMPLE X+2
DATA
X
DATA
X+1
OUTPUT
DATA
EOC,
BUSY
TRACK/
ACQUIRE
CONVERSION
TIME
TRACK/
ACQUIRE
Figure 8.6
In a SAR ADC, t he out put dat a for a par t icular cycle is valid at t he end of t he
conver sion int er val. In ot her ADC ar chit ect ur es, such as sigma-delt a or t he t wo-
st age subr anging ar chit ect ur e shown in Figur e 8.7, t his is not t he case. The
subr anging ADC shown in t he figur e is a t wo-st age pipelined or subr anging 12-bit
conver t er . The fir st conver sion is done by t he 6-bit ADC which dr ives a 6-bit DAC.
The out put of t he 6-bit DAC r epr esent s a 6-bit appr oximat ion t o t he analog input .
Not e t hat SHA2 delays t he analog signal while t he 6-bit ADC makes it s decision and
t he 6-bit DAC set t les. The DAC appr oximat ion is t hen subt r act ed fr om t he analog
signal fr om SHA2, amplified, and digit ized by a 7-bit ADC. The out put s of t he t wo
conver sions ar e combined, and t he ext r a bit used t o cor r ect er r or s made in t he fir st
conver sion. The t ypical t iming associat ed wit h t his t ype of conver t er is shown in
Figur e 8.8. Not e t hat t he out put dat a pr esent ed immediat ely aft er sample X
act ually cor r esponds t o sample X2, i.e., t her e is a t wo clock-cycle "pipeline" delay.
The pipelined ADC ar chit ect ur e is gener ally associat ed wit h high speed ADCs, and
in most cases t he pipeline delay, or latency, is not a major syst em pr oblem in most
applicat ions wher e t his t ype of conver t er is used.
Pipelined ADCs may have mor e t han t wo clock-cycles lat ency depending on t he
par t icular ar chit ect ur e. For inst ance, t he conver sion could be done in t hr ee, or four ,
or per haps even mor e pipelined st ages causing addit ional lat ency in t he out put dat a.
Ther efor e, if t he ADC is t o be used in an event -t r igger ed (or single-shot ) mode wher e
t her e must be a one-t o-one t ime cor r espondence bet ween each sample and t he
cor r esponding dat a, t hen t he pipeline delay can be t r oublesome, and t he SAR
ar chit ect ur e is advant ageous. Pipeline delay or lat ency can also be a pr oblem in high
speed ser vo-loop cont r ol syst ems or mult iplexed applicat ions. In addit ion, some
8.7
pipelined conver t er s have a minimum allowable conver sion r at e and must be kept
r unning t o pr event sat ur at ion of int er nal nodes.
12-BIT TWO-STAGE PIPELINED ADC ARCHITECTURE
SHA
1
SHA
2
TIMING
6-BIT
ADC
6-BIT
DAC
BUFFER
REGISTER
+
_
7-BIT
ADC
ERROR CORRECTION LOGIC
OUTPUT REGISTERS
6
6
7
12
12
ANALOG
INPUT
SAMPLING
CLOCK
OUTPUT DATA
Figure 8.7
TYPICAL PIPELINED ADC TIMING
SAMPLING
CLOCK
SAMPLE X SAMPLE X+1 SAMPLE X+2
DATA
X2
DATA
X1
DATA
X
OUTPUT
DATA
ABOVE SHOWS TWO CLOCK-CYCLES PIPELINE DELAY
Figure 8.8
8.8
Swit ched capacit or SAR ADCs gener ally have unbuffer ed input cir cuit s similar t o
t he cir cuit shown in Figur e 8.9 for t he AD7858/59 ADC. Dur ing t he acquisit ion t ime,
t he analog input must char ge t he 20pF equivalent input capacit ance t o t he cor r ect
value. If t he input is a DC signal, t hen t he sour ce r esist ance, R
S
, in ser ies wit h t he
125 int er nal swit ch r esist ance cr eat es a t ime const ant . In or der t o set t le t o 12-bit
accur acy, appr oximat ely 9 t ime const ant s must be allowed for set t ling, and t his
defines t he minimum allowable acquisit ion t ime. (Set t ling t o 14-bit s r equir es about
10 t ime const ant s, and 16-bit s r equir es about 11).
t
ACQ
> 9 (R
S
+ 125) 20pF.
For example, if R
S
= 50, t he acquisit ion t ime per t he above for mula must be at
least 310ns.
For AC applicat ions, a low impedance sour ce should be used t o pr event dist or t ion
due t o t he non-linear ADC input cir cuit . In a single supply applicat ion, a fast
set t ling r ail-t o-r ail op amp such as t he AD820 should be used. Fast set t ling allows
t he op amp t o set t le quickly fr om t he t r ansient cur r ent s induced on it s input by t he
int er nal ADC swit ches. In Figur e 8.9, t he AD820 dr ives a lowpass filt er consist ing of
t he 50 ser ies r esist or and t he 10nF capacit or (cut off fr equency appr oximat ely
320kHz). This filt er r emoves high fr equency component s which could r esult in
aliasing and incr eased noise.
Using a single supply op amp in t his applicat ion r equir es special consider at ion of
signal levels. The AD820 is connect ed in t he inver t ing mode and has a signal gain of
1. The noninver t ing input is biased at a common mode volt age of +1.3V wit h t he
10.7k/10k divider , r esult ing in an out put volt age of +2.6V for V
IN
= 0V, and
+0.1V for V
IN
= +2.5V. This offset is pr ovided because t he AD820 out put cannot go
all t he way t o gr ound, but is limit ed t o t he V
CESAT
of t he out put st age NPN
t r ansist or , which under t hese loading condit ions is about 50mV. The input r ange of
t he ADC is also offset by +100mV by applying t he +100mV offset fr om t he
412/10k divider t o t he AIN input .
The AD789X-family of single supply SAR ADCs (as well as t he AD974, AD976, and
AD977) includes a t hin film r esist ive at t enuat or and level shift er on t he analog
input t o allow a var iet y of input r ange opt ions, bot h bipolar and unipolar . A
simplified diagr am of t he input cir cuit of t he AD7890-10 12-bit , 8-channel ADC is
shown in Figur e 8.10. This ar r angement allows t he conver t er t o digit ize a 10V
input while oper at ing on a single +5V supply. The R1/R2/R3 t hin film net wor k
pr ovides t he at t enuat ion and level shift ing t o conver t t he 10V input t o a 0V t o
+2.5V signal which is digit ized by t he int er nal ADC. This t ype of input r equir es no
special dr ive cir cuit r y because R1 isolat es t he input fr om t he act ual conver t er
cir cuit r y. Never t heless, t he sour ce r esist ance, R
S
, should be kept r easonably low t o
pr event gain er r or s caused by t he R
S
/R1 divider .
8.9
DRIVING SWITCHED CAPACITOR INPUTS
OF AD7858/59 12-BIT, 200kSPS ADC
AD820
_
+
+
_
CAP
DAC
10k
10k
10.7k
10k
50
10nF
125
125
20pF
T
H
H T
V
REF
AIN+
AIN
DGND AGND
AV
DD
DV
DD
0.1F
0.1F
+2.5V
+1.30V
+3V TO +5V
V
IN
V
IN
: 0V TO +2.5V
AIN+ : +2.6V TO +0.1V
AD7858/59
CUTOFF
= 320kHz
0.1F
V
CM
=
NOTE: ONLY ONE INPUT SHOWN
T = TRACK
H = HOLD
10k
412
+100mV
0.1F
0.1F
Figure 8.9
DRIVING SINGLE-SUPPLY ADCs WITH SCALED INPUTS
+2.5V
REFERENCE
+
_
~
REFOUT/
REFIN
V
INX
AGND
R
S
2k
R2
7.5k
R3
10k
30k
+2.5V TO ADC REF CIRCUITS
TO MUX, SHA, ETC.
10V
0V TO +2.5V
AD7890-10
12-BITS, 8-CHANNEL
V
S
R1
R1, R2, R3 ARE
RATIO-TRIMMED
THIN FILM RESISTORS
+5V
Figure 8.10
8.10
SAR ADCS WI TH MULTI P LEXED I NP UTS
Mult iplexing is a fundament al par t of many dat a acquisit ion syst ems, and a
fundament al under st anding of mult iplexer s is r equir ed t o design a dat a acquisit ion
syst em. Swit ches for dat a acquisit ion syst ems, especially when int egr at ed int o t he
IC, gener ally ar e CMOS-t ypes shown in Figur e 8.11. Ut ilizing t he P-Channel and N-
Channel MOSFET swit ches in par allel minimizes t he change of on-r esist ance (R
ON
)
as a funct ion of signal volt age. On-r esist ance can var y fr om less t han 5 t o sever al
hundr ed ohms depending upon t he device. Var iat ion in on-r esist ance as a funct ion of
signal level (oft en called R
ON
-modulation) can cause dist or t ion if t he mult iplexer
must dr ive a load, and t her efor e R
ON
flatness is also an impor t ant specificat ion.
BASIC CMOS ANALOG SWITCH
P-CH
N-CH
P-CH
N-CH
V
IN
V
OUT
+V
S
V
S
V
S
+V
S
OFF
ON
+ SIGNAL VOLTAGE
R
ON
NMOS
PMOS
CMOS
Figure 8.11
Because of non-zer o R
ON
and R
ON
-modulat ion, mult iplexer out put s should be
isolat ed fr om t he load wit h a suit able buffer amplifier . A separ at e buffer is not
r equir ed if t he mult iplexer dr ives a high input impedance, such as a PGA, SHA or
ADC - but bewar e! Some SHAs and ADCs dr aw high fr equency pulse cur r ent at
t heir sampling r at e and cannot t oler at e being dr iven by an unbuffer ed mult iplexer .
The key mult iplexer specificat ions ar e switching time, on-resistance, on-resistance
flatness, and off-channel isolation, and crosstalk. Mult iplexer swit ching t ime r anges
fr om less t han 20ns t o over 1s, R
ON
fr om less t han 5 t o sever al hundr ed ohms,
and off-channel isolat ion fr om 50 t o 90dB.
8.11
A number of CMOS swit ches can be connect ed t o for m a mult iplexer as shown in
Figur e 8.12. The number of input channels t ypically r anges fr om 4 t o 16, and some
mult iplexer s have int er nal channel-addr ess decoding logic and r egist er s, while wit h
ot her s, t hese funct ions must be per for med ext er nally. Unused mult iplexer input s
must be gr ounded or sever e loss of syst em accur acy may r esult .
Swit ches and mult iplexer s may be opt imized for var ious applicat ions as shown in
Figur e 8.13.
SIMPLIFIED DIAGRAM OF A
TYPICAL ANALOG MULTIPLEXER
ADDRESS
REGISTER
ADDRESS
DECODER
R
ON
R
ON
CHANNEL
ADDRESS
CHANNEL 1
CHANNEL M
CLOCK
BUFFER,
SHA,
OR PGA
R
L
Figure 8.12
An M-channel mult iplexed dat a acquisit ion syst em is shown in Figur e 8.14. The
t ypical t iming associat ed wit h t he SAR ADC is also shown in t he diagr am. The
conver sion pr ocess is init iat ed on t he posit ive-going edge of t he CONVST pulse. If
maximum t hr oughput is desir ed, t he mult iplexer is changed t o t he next channel at
t he same t ime. This allows near ly t he ent ir e sampling per iod (1/f
s
) for t he
mult iplexer t o set t le. Remember t hat it is possible t o have a posit ive fullscale signal
on one channel and a negat ive fullscale signal on t he next , t her efor e t he mult iplexer
out put must set t le fr om a fullscale out put st ep change wit hin t he allocat ed t ime.
Also shown in Figur e 8.14 ar e input filt er s on each channel. These filt er s ser ve as
ant ialiasing filt er s t o r emove signals above one-half t he effect ive per -channel
sampling fr equency. If t he ADC is sampling at f
s
, and t he mult iplexer is sequencing
t hr ough all M channels, t hen t he per -channel sampling r at e is f
s
/M. The input
lowpass filt er s should have sufficient at t enuat ion f
s
/2M t o pr event dynamic r ange
limit at ions due t o aliasing.
8.12
WHAT'S NEW IN DISCRETE SWITCHES / MUXES?
n ADG508F, ADG509F, ADG527F: 15V Specified
u R
ON
< 300
u Switching Time < 250ns
u Fault Protection on Inputs and Outputs (40V to + 55V)
n ADG451, ADG452, ADG453: 15V, +12V, 5V Specified
u R
ON
< 5
u 2kV ESD Protection
n ADG7XX-Family: Single-Supply, +1.8V to +5.5V
u R
ON
< 5 , R
ON
Flatness < 2
Figure 8.13
MULTIPLEXED SAR ADC FILTERING AND TIMING
MUX
LPF
1
LPF
M
SHA ADC LPF
C
CHANGE
CHANNEL
CONVST, f
s
CONVST
CONVERT
EOC,
BUSY
TRACK/
ACQUIRE
MUX
OUTPUT
MUX SETTLING MUX SETTLING
CHANGE
CHANNEL
CHANGE
CHANNEL
CONVERT
TRACK/
ACQUIRE
CHANGE
CHANNEL
DATA
EOC,
BUSY
AIN
1
AIN
M
f
s
/ 2M
f
s
f
c
SEE TEXT
Figure 8.14
8.13
It is not necessar y, however , t hat each channel be sampled at t he same r at e, and t he
var ious input lowpass filt er s can be individually t ailor ed for t he act ual sampling
r at e and signal bandwidt h expect ed on each channel.
An opt ional lowpass filt er is oft en placed bet ween t he mult iplexer out put and t he
SHA input , designat ed LPF
C
in Figur e 8.14. Car e must be exer cised in select ing it s
cut off fr equency because it s t ime const ant dir ect ly affect s t he mult iplexer set t ling
t ime. If t he filt er is a single-pole, t he number of t ime const ant s, n, r equir ed t o set t le
t o a desir ed accur acy is given in Figur e 8.15.
SINGLE-POLE FILTER SETTLING
TIME TO REQUIRED ACCURACY
RESOLUTION
# OF BITS
6
8
10
12
14
16
18
20
22
LSB (%FS)
1.563
0.391
0.0977
0.0244
0.0061
0.00153
0.00038
0.000095
0.000024
# OF TIME
CONSTANTS, n
4.16
5.55
6.93
8.32
9.70
11.09
12.48
13.86
15.25
f
c
/f
s
0.67
0.89
1.11
1.32
1.55
1.77
2.00
2.22
2.44
f
s
= ADC Sampling Frequency
f
c
= Cutoff Frequency of LPF
C
Figure 8.15
If t he t ime const ant of LPF
C
is , and it s cut off fr equency f
c
, t hen
f
c
=
1
2
.
But t he sampling fr equency f
s
is r elat ed t o n by t he equat ion:
f
s
n
<
.
Combining t he t wo equat ions and solving for f
c
in t er ms of n and f
s
yields:
f
c
n f
s
>

2
.
8.14
As an example, assume t hat t he ADC is a 12-bit one sampling at 100kSPS. Fr om
t he t able, n = 8.32, and t her efor e f
c
> 132kSPS per t he above equat ion. While t his
filt er will help pr event wideband noise fr om ent er ing t he SHA, it does not pr ovide
t he same funct ion as t he ant ialiasing filt er s at t he input of each channel, whose
individual cut off fr equencies can be much lower .
For t his r eason, only a few int egr at ed dat a acquisit ion ICs wit h on-boar d
mult iplexer s give access t o t he mult iplexer out put and t he SHA input . If access is
offer ed and LPF
C
is used, t he set t ling t ime r equir ement must be obser ved in or der
t o achieve t he desir ed accur acy.
COMP LETE DATA ACQUI SI TI ON SYSTEMS ON A CHI P
VLSI mixed-signal pr ocessing allows t he int egr at ion of lar ge and complex dat a
acquisit ion cir cuit s on a single chip. Most signal condit ioning cir cuit s including
mult iplexer s, PGAs, and SHAs, can now be manufact ur ed on t he same chip as t he
ADC. This high level of int egr at ion per mit s dat a acquisit ion syst ems (DASs) t o be
specified and t est ed as a single complex funct ion.
Such funct ionalit y r elieves t he designer of most of t he bur den of t est ing and
calculat ing er r or budget s. The DC and AC char act er ist ics of a complet e dat a
acquisit ion syst em ar e specified as a complet e funct ion, which r emoves t he necessit y
of calculat ing per for mance fr om a collect ion of individual wor st case device
specificat ions. A complet e monolit hic syst em should achieve a higher per for mance at
much lower cost t han would be possible wit h a syst em built up fr om discr et e
funct ions. Fur t her mor e, syst em calibr at ion is easier , and in fact many monolit hic
DASs ar e self calibr at ing, offer ing bot h int er nal and syst em calibr at ion funct ions.
The AD7858 is an example of a highly int egr at ed IC DAS (see Figur e 8.16). The
device oper at es on a single supply volt age of +3V t o +5.5V and dissipat es only
15mW. The r esolut ion is 12-bit s, and t he maximum sampling fr equency is 200kSPS.
The input mult iplexer can be configur ed eit her as 8 single-ended input s or 4 pseudo-
differ ent ial input s. The AD7858 r equir es an ext er nal 4MHz clock and init iat es t he
conver sion on t he posit ive-going edge of t he CONVST pulse which does not need t o
be synchr onized t o t he high fr equency clock. Conver sion can also be init iat ed via
soft war e by set t ing a bit in t he pr oper cont r ol r egist er .
The AD7858 cont ains an on-chip 2.5V r efer ence (which can be over r idden wit h an
ext er nal one), and t he fullscale input volt age r ange is 0V t o V
REF
. The int er nal
DAC is a swit ched capacit or t ype, and t he ADC cont ains a self-calibr at ion and
syst em calibr at ion opt ion t o ensur e accur at e oper at ion over t ime and t emper at ur e.
The input /out put por t is a ser ial one and is SPI, QSPI, 8051, and P compat ible.
The AD7858L is a lower power (5.5mW) ver sion of t he AD7858 which oper at es at a
maximum sampling r at e of 100kSPS.
8.15
AD7858 12-BIT, 200kSPS 8-CHANNEL SINGLE-SUPPLY ADC
MUX T/H
2.5V REF
BUF
SWITCHED
CAPACITOR
DAC
CALIBRATION
MEMORY AND
CONTROLLER
SAR + ADC
CONTROL
SERIAL INTERFACE/CONTROL REGISTER
AIN1
REF
IN
/
REF
OUT
CREF1
CREF2
CAL
DV
DD
AV
DD
AGND
DGND
CLKIN
CONVST
BUSY
SLEEP
SYNC
DIN DOUT SCLK
AIN8
AD7858/
AD7858L
Figure 8.16
AD7858 / AD7858L DATA ACQUISITION ADCs
KEY SPECIFICATIONS
n 12-Bit, 8Channel, 200kSPS (AD7858), 100kSPS (AD7858L)
n System and Self-Calibration with Autocalibration on Power-Up
n Automatic Power Down After Conversion (25W)
n Low Power:
u AD7858: 15mW (V
DD
= +3V)
u AD7858L: 5.5mW (V
DD
= +3V)
n Flexible Serial Interface: 8051 / SPI / QSPI / P Compatible
n 24-Pin DIP, SOIC, SSOP Packages
n AD7859, AD7859L: Parallel Output Devices, Similar Specifications
Figure 8.17
8.16
SI GMA-DELTA ( ) MEASUREMENT ADCS
J a m es M. Br ya n t
Sigma-Delt a Analog-Digit al Conver t er s ( ADCs) have been known for near ly
t hir t y year s, but only r ecent ly has t he t echnology (high-densit y digit al VLSI) exist ed
t o manufact ur e t hem as inexpensive monolit hic int egr at ed cir cuit s. They ar e now
used in many applicat ions wher e a low-cost , low-bandwidt h, low-power ,
high-r esolut ion ADC is r equir ed.
Ther e have been innumer able descr ipt ions of t he ar chit ect ur e and t heor y of
ADCs, but most commence wit h a maze of int egr als and det er ior at e fr om t her e. In
t he Applicat ions Depar t ment at Analog Devices, we fr equent ly encount er engineer s
who do not under st and t he t heor y of oper at ion of ADCs and ar e convinced, fr om
st udy of a t ypical published ar t icle, t hat it is t oo complex t o compr ehend easily.
Ther e is not hing par t icular ly difficult t o under st and about ADCs, as long as you
avoid t he det ailed mat hemat ics, and t his sect ion has been wr it t en in an at t empt t o
clar ify t he subject . A ADC cont ains ver y simple analog elect r onics (a compar at or ,
a swit ch, and one or mor e int egr at or s and analog summing cir cuit s), and quit e
complex digit al comput at ional cir cuit r y. This cir cuit r y consist s of a digit al signal
pr ocessor (DSP) which act s as a filt er (gener ally, but not invar iably, a low pass
filt er ). It is not necessar y t o know pr ecisely how t he filt er wor ks t o appr eciat e what
it does. To under st and how a ADC wor ks familiar it y wit h t he concept s of
over-sampling, quantization noise shaping, digital filtering, and decimation is
r equir ed.
SIGMA-DELTA ADCs
n Low Cost, High Resolution (to 24-bits) Excellent DNL,
n Low Power, but Limited Bandwidth
n Key Concepts are Simple, but Math is Complex
u Oversampling
u Quantization Noise Shaping
u Digital Filtering
u Decimation
n Ideal for Sensor Signal Conditioning
u High Resolution
u Self, System, and Auto Calibration Modes
Figure 8.18
8.17
Let us consider t he t echnique of over -sampling wit h an analysis in t he fr equency
domain. Wher e a DC conver sion has a quantization error of up t o LSB, a sampled
dat a syst em has quantization noise. A per fect classical N-bit sampling ADC has an
RMS quant izat ion noise of q/12 unifor mly dist r ibut ed wit hin t he Nyquist band of
DC t o f
s
/2 (wher e q is t he value of an LSB and f
s
is t he sampling r at e) as shown in
Figur e 8.19A. Ther efor e, it s SNR wit h a full-scale sinewave input will be
(6.02N + 1.76) dB. If t he ADC is less t han per fect , and it s noise is gr eat er t han it s
t heor et ical minimum quant izat ion noise, t hen it s effective r esolut ion will be less
t han N-bit s. It s act ual resolut ion (oft en known as it s Effect ive Number of Bit s or
ENOB) will be defined by
ENOB
SNR dB
dB
=
1 76
6 02
.
.
.
If we choose a much higher sampling r at e, Kf
s
(see Figur e 8.19B), t he quant izat ion
noise is dist r ibut ed over a wider bandwidt h DC t o Kf
s
/2. If we t hen apply a digit al
low pass filt er (LPF) t o t he out put , we r emove much of t he quant izat ion noise, but
do not affect t he want ed signal - so t he ENOB is impr oved. We have accomplished a
high r esolut ion A/D conver sion wit h a low r esolut ion ADC. The fact or K is gener ally
r efer r ed t o as t he oversampling ratio.
OVERSAMPLING, DIGITAL FILTERING,
NOISE SHAPING, AND DECIMATION
f
s
2
f
s
Kf
s
2
Kf
s
Kf
s Kf
s
2
f
s
2
f
s
2
DIGITAL FILTER
REMOVED NOISE
REMOVED NOISE
QUANTIZATION
NOISE = q / 12
q = 1 LSB
ADC
ADC
DIGITAL
FILTER

MOD
DIGITAL
FILTER
f
s
Kf
s
Kf
s
DEC
f
s
Nyquist
Operation
Oversampling
+ Digital Filter
+ Decimation
Oversampling
+ Noise Shaping
+ Digital Filter
+ Decimation
A
B
C
DEC
f
s
Figure 8.19
8.18
Since t he bandwidt h is r educed by t he digit al out put filt er , t he out put dat a r at e may
be lower t han t he or iginal sampling r at e (Kf
s
) and st ill sat isfy t he Nyquist cr it er ion.
This may be achieved by passing ever y Mt h r esult t o t he out put and discar ding t he
r emainder . The pr ocess is known as "decimat ion" by a fact or of M. Despit e t he
or igins of t he t er m (decem is Lat in for t en), M can have any int eger value, pr ovided
t hat t he out put dat a r at e is mor e t han t wice t he signal bandwidt h. Decimat ion does
not cause any loss of infor mat ion (see Figur e 8.19B).
If we simply use over -sampling t o impr ove r esolut ion, we must over -sample by a
fact or of 2
2N
t o obt ain an N-bit incr ease in r esolut ion. The conver t er does not
need such a high over -sampling r at io because it not only limit s t he signal passband,
but also shapes t he quant izat ion noise so t hat most of it falls out side t his passband
as shown in Figur e 8.19C.
If we t ake a 1-bit ADC (gener ally known as a compar at or ), dr ive it wit h t he out put
of an int egr at or , and feed t he int egr at or wit h an input signal summed wit h t he
out put of a 1-bit DAC fed fr om t he ADC out put , we have a fir st -or der modulat or
as shown in Figur e 8.20. Add a digit al low pass filt er (LPF) and decimat or at t he
digit al out put , and we have a ADC: t he modulat or shapes t he quant izat ion
noise so t hat it lies above t he passband of t he digit al out put filt er , and t he ENOB is
t her efor e much lar ger t han would ot her wise be expect ed fr om t he over -sampling
r at io.
FIRST-ORDER SIGMA-DELTA ADC

+
_
+V
REF
V
REF
DIGITAL
FILTER
AND
DECIMATOR
+
_
CLOCK
Kf
s
V
IN
N-BITS
f
s
f
s
A
B
1-BIT DATA
STREAM
1-BIT
DAC
LATCHED
COMPARATOR
(1-BIT ADC)
1-BIT,
Kf
s
SIGMA-DELTA MODULATOR
INTEGRATOR
Figure 8.20
8.19
Int uit ively, a ADC oper at es as follows. Assume a DC input at V
IN
. The
int egr at or is const ant ly r amping up or down at node A. The out put of t he
compar at or is fed back t hr ough a 1-bit DAC t o t he summing input at node B. The
negat ive feedback loop fr om t he compar at or out put t hr ough t he 1-bit DAC back t o
t he summing point will for ce t he aver age DC volt age at node B t o be equal t o V
IN
.
This implies t hat t he aver age DAC out put volt age must equal t o t he input volt age
V
IN
. The aver age DAC out put volt age is cont r olled by t he ones-density in t he 1-bit
dat a st r eam fr om t he compar at or out put . As t he input signal incr eases t owar ds
+V
REF
, t he number of "ones" in t he ser ial bit st r eam incr eases, and t he number of
"zer os" decr eases. Similar ly, as t he signal goes negat ive t owar ds V
REF
, t he
number of "ones" in t he ser ial bit st r eam decr eases, and t he number of "zer os"
incr eases. Fr om a ver y simplist ic st andpoint , t his analysis shows t hat t he aver age
value of t he input volt age is cont ained in t he ser ial bit st r eam out of t he compar at or .
The digit al filt er and decimat or pr ocess t he ser ial bit st r eam and pr oduce t he final
out put dat a.
The concept of noise shaping is best explained in t he fr equency domain by
consider ing t he simple modulat or model in Figur e 8.21.
SIMPLIFIED FREQUENCY DOMAIN
LINEARIZED MODEL OF A SIGMA-DELTA MODULATOR
ANALOG FILTER
H(f) =
1
f
X
Y
+
_
X Y
1
f
( X Y )
Q =
QUANTIZATION
NOISE
Y =
1
f
( X Y )
+ Q
REARRANGING, SOLVING FOR Y:
Y =
X
f + 1
+
Q f
f + 1
SIGNAL TERM NOISE TERM
Y
Figure 8.21
8.20
The int egr at or in t he modulat or is r epr esent ed as an analog lowpass filt er wit h a
t r ansfer funct ion equal t o H(f) = 1/f. This t r ansfer funct ion has an amplit ude
r esponse which is inver sely pr opor t ional t o t he input fr equency. The 1-bit quant izer
gener at es quant izat ion noise, Q, which is inject ed int o t he out put summing block. If
we let t he input signal be X, and t he out put Y, t he signal coming out of t he input
summer must be X Y. This is mult iplied by t he filt er t r ansfer funct ion, 1/f, and t he
r esult goes t o one input t o t he out put summer . By inspect ion, we can t hen wr it e t he
expr ession for t he out put volt age Y as:
Y
f
X Y Q = +
1
( ) .
This expr ession can easily be r ear r anged and solved for Y in t er ms of X, f, and Q:
Y
X
f
Q f
f
=
+
+

+ 1 1
.
Not e t hat as t he fr equency f appr oaches zer o, t he out put volt age Y appr oaches X
wit h no noise component . At higher fr equencies, t he amplit ude of t he signal
component decr eases, and t he noise component incr eases. At high fr equency, t he
out put consist s pr imar ily of quant izat ion noise. In essence, t he analog filt er has a
lowpass effect on t he signal, and a highpass effect on t he quant izat ion noise. Thus
t he analog filt er per for ms t he noise shaping funct ion in t he modulat or model.
For a given input fr equency, higher or der analog filt er s offer mor e at t enuat ion. The
same is t r ue of modulat or s, pr ovided cer t ain pr ecaut ions ar e t aken.
By using mor e t han one int egr at ion and summing st age in t he modulat or , we can
achieve higher or der s of quant izat ion noise shaping and even bet t er ENOB for a
given over -sampling r at io as is shown in Figur e 8.22 for bot h a fir st and second-
or der modulat or . The block diagr am for t he second-or der modulat or is shown
in Figur e 8.23. Thir d, and higher , or der ADCs wer e once t hought t o be
pot ent ially unst able at some values of input - r ecent analyses using finite r at her
t han infinit e gains in t he compar at or have shown t hat t his is not necessar ily so, but
even if inst abilit y does st ar t t o occur , it is not impor t ant , since t he DSP in t he digit al
filt er and decimat or can be made t o r ecognize incipient inst abilit y and r eact t o
pr event it .
Figur e 8.24 shows t he r elat ionship bet ween t he or der of t he modulat or and t he
amount of over -sampling necessar y t o achieve a par t icular SNR. For inst ance, if t he
over sampling r at io is 64, an ideal second-or der syst em is capable of pr oviding an
SNR of about 80dB. This implies appr oximat ely 13 effect ive number of bit s (ENOB).
Alt hough t he filt er ing done by t he digit al filt er and decimat or can be done t o any
degr ee of pr ecision desir able, it would be point less t o car r y mor e t han 13 binar y bit s
t o t he out side wor ld. Addit ional bit s would car r y no useful signal infor mat ion, and
would be bur ied in t he quant izat ion noise unless post -filt er ing t echniques wer e
employed.
8.21
SIGMA-DELTA MODULATORS
SHAPE QUANTIZATION NOISE
f
s
2
Kf
s
2
2ND ORDER
1ST ORDER
DIGITAL
FILTER
Figure 8.22
SECOND-ORDER SIGMA-DELTA ADC

+
_
V
IN
INTEGRATOR
+
_
CLOCK
Kf
s
1-BIT
DAC
INTEGRATOR
DIGITAL FILTER
AND
DECIMATOR
N-BITS
f
s
+
_
1-BIT
DATA
STREAM
Figure 8.23
8.22
SNR VERSUS OVERSAMPLING RATIO FOR FIRST,
SECOND, AND THIRD-ORDER LOOPS
FIRST-ORDER LOOP
9dB / OCTAVE
SECOND-ORDER LOOP
15dB / OCTAVE
THIRD-ORDER LOOP*
21dB / OCTAVE
* > 2nd ORDER LOOPS DO NOT
OBEY LINEAR MODEL
4 8 16 32 64 128 256
0
20
40
60
80
100
120
SNR
(dB)
OVERSAMPLING RATIO, K
Figure 8.24
The ADCs t hat we have descr ibed so far cont ain int egr at or s, which ar e low pass
filt er s, whose passband ext ends fr om DC. Thus, t heir quant izat ion noise is pushed
up in fr equency. At pr esent , most commer cially available ADCs ar e of t his t ype
(alt hough some which ar e int ended for use in audio or t elecommunicat ions
applicat ions cont ain bandpass r at her t han lowpass digit al filt er s t o eliminat e any
syst em DC offset s). Sigma-delt a ADCs ar e available wit h r esolut ions up t o 24-bit s
for DC measur ement applicat ions (AD77XX-family), and wit h r esolut ions of 18-bit s
for high qualit y digit al audio applicat ions (AD1879).
But t her e is no par t icular r eason why t he filt er s of t he modulat or should be
LPFs, except t hat t r adit ionally ADCs have been t hought of as being baseband
devices, and t hat int egr at or s ar e somewhat easier t o const r uct t han bandpass
filt er s. If we r eplace t he int egr at or s in a ADC wit h bandpass filt er s (BPFs), t he
quant izat ion noise is moved up and down in fr equency t o leave a vir t ually noise-fr ee
r egion in t he pass-band (see Refer ence 1). If t he digit al filt er is t hen pr ogr ammed t o
have it s pass-band in t his r egion, we have a ADC wit h a bandpass, r at her t han a
lowpass char act er ist ic. Alt hough st udies of t his ar chit ect ur e ar e in t heir infancy,
such ADCs would seem t o be ideally suit ed for use in digit al r adio r eceiver s, medical
ult r asound, and a number of ot her applicat ions.
A ADC wor ks by over -sampling, wher e simple analog filt er s in t he modulat or
shape t he quant izat ion noise so t hat t he SNR in the bandwidth of interest is much
gr eat er t han would ot her wise be t he case, and by using high per for mance digit al
filt er s and decimat ion t o eliminat e noise out side t he r equir ed passband. Because t he
analog cir cuit r y is so simple and undemanding, it may be built wit h t he same digit al
8.23
VLSI pr ocess t hat is used t o fabr icat e t he DSP cir cuit r y of t he digit al filt er . Because
t he basic ADC is 1-bit (a compar at or ), t he t echnique is inher ent ly linear .
Alt hough t he det ailed analysis of ADCs involves quit e complex mat hemat ics,
t heir basic design can be under st ood wit hout t he necessit y of any mat hemat ics at
all. For fur t her discussion on ADCs, r efer t o Refer ences 2 and 3.
HI GH RESOLUTI ON, LOW-FREQUENCY SI GMA-DELTA
MEASUREMENT ADCS
The AD7710, AD7711, AD7712, AD7713, and AD7714, AD7730, and AD7731 ar e
member s of a family of sigma-delt a conver t er s designed for high accur acy, low
fr equency measur ement s. They have no missing codes t o 24-bit s, and t heir effect ive
r esolut ions ext end t o 22.5 bit s depending upon t he device, updat e r at e, pr ogr ammed
filt er bandwidt h, PGA gain, post -filt er ing, et c. They all use similar sigma-delt a
cor es, and t heir main differ ences ar e in t heir analog input s, which ar e opt imized for
differ ent t r ansducer s. Newer member s of t he family, such as t he AD7714,
AD7730/7730L, and t he AD7731/7731L ar e designed and specified for single supply
oper at ion.
Ther e ar e also similar 16-bit devices available (AD7705, AD7706, AD7715) which
also oper at e on single supplies.
The AD1555/AD1556 is a 24-bit t wo-chip modulat or /filt er specifically designed
for seismic dat a acquisit ion syst ems. This combinat ion yields a dynamic r ange of
120dB. The AD1555 cont ains a PGA and a 4t h-or der modulat or . The AD1555
out put s a ser ial 1-bit dat a st r eam t o t he AD1556 which cont ains t he digit al filt er
and decimat or .
Because of t he high r esolut ion of t hese conver t er s, t he effect s of noise must be fully
under st ood and how it affect s t he ADC per for mance. This discussion also applies t o
ADCs of lower r esolut ion, but is par t icular ly impor t ant when dealing wit h 16-bit or
gr eat er ADCs.
Figur e 8.25 shows t he out put code dist r ibut ion, or hist ogr am, for a t ypical high
r esolut ion ADC wit h a DC, or "gr ounded" input cent er ed on a code. If t her e wer e no
noise sour ces pr esent , t he ADC out put would always yield t he same code, r egar dless
of how many samples wer e t aken. Of cour se, if t he DC input happened t o be in a
t r ansit ion zone bet ween t wo adjacent codes, t hen t he dist r ibut ion would be spr ead
bet ween t hese t wo codes, but no fur t her . Var ious noise sour ces int er nal t o t he
conver t er , however , cause a dist r ibut ion of codes ar ound a pr imar y one as shown in
t he diagr am.
This noise in t he ADC is gener at ed by unwant ed signal coupling and by component s
such as r esist or s (J ohnson noise) and act ive devices like swit ches (kT/C noise). In
addit ion, t her e is r esidual quant izat ion noise which is not r emoved by t he digit al
filt er . The t ot al noise can be consider ed t o be an input noise sour ce which is summed
wit h t he input signal int o an ideal noiseless ADC. It is somet imes called input-
referred noise, or effective input noise. The dist r ibut ion of t he noise is pr imar ily
8.24
gaussian, and t her efor e an RMS noise value can be det er mined (i.e., t he st andar d
deviat ion of t he dist r ibut ion).
EFFECT OF INPUT-REFERRED NOISE
ON ADC "GROUNDED INPUT" HISTOGRAM
n n+1 n+2 n+3 n+4 n1 n2 n3 n4
NUMBER OF
OCCURANCES
RMS NOISE
P-P INPUT NOISE
6.6 RMS NOISE
OUTPUT CODE
Figure 8.25
In or der t o char act er ize t he input -r efer r ed noise, we int r oduce t he concept of
Effective Resolution, somet imes r efer r ed t o as effect ive number of bit s (ENOB). It
should be not ed, however , t hat ENOB is most oft en used t o descr ibe t he dynamic
per for mance of higher speed ADCs wit h AC input signals, and is not oft en used wit h
r espect t o pr ecision low fr equency ADCs.
Effect ive Resolut ion is defined by t he following equat ion:
Effect ive solut ion
Fullscale Range
RMS Noise
Bit s Re log =

2
.
Noise-Fr ee Code Resolut ion is defined by:
Noise Fr ee Code solut ion
Fullscale Range
Peak t o Peak Noise
Bit s Re log =

2
.
Peak-t o-peak noise is appr oximat ely 6.6 t imes t he RMS noise, so Noise-Fr ee Code
Resolut ion can be expr essed as:
Noise Fr ee Code solut ion
Fullscale Range
RMS Noise
Bit s
Effect ive solut ion Bit s
Re log
.
Re .
=
=
2
6 6
2 72
.
8.25
Noise Fr ee Code Resolut ion is t her efor e t he maximum number of ADC bit s t hat can
be used and st ill always get a single-code out put dist r ibut ion for a DC input placed
on a code cent er , i.e., t her e is no code flicker. This does not say t hat t he r est of t he
LSBs ar e unusable, it is only a way t o define t he noise amplit ude and r elat e it t o
ADC r esolut ion. It should also be not ed t hat addit ional ext er nal post -filt er ing and
aver aging of t he ADC out put dat a can fur t her r educe input r efer r ed noise and
incr ease t he effect ive r esolut ion.
DEFINITION OF "NOISE-FREE" CODE RESOLUTION
EFFECTIVE
RESOLUTION
= log
2
FULLSCALE RANGE
RMS NOISE
BITS
NOISE-FREE
CODE RESOLUTION
= log
2
FULLSCALE RANGE
P-P NOISE
BITS
P-P NOISE = 6.6 RMS NOISE
NOISE-FREE
CODE RESOLUTION
=
log
2
FULLSCALE RANGE
6.6 RMS NOISE
BITS
= EFFECTIVE RESOLUTION 2.72 BITS
Figure 8.26
The AD7730 is one of t he newest member s of t he AD77XX family and is shown in
Figur e 8.27. This ADC was specifically designed t o int er face dir ect ly t o br idge
out put s in weigh scale applicat ions. The device accept s low-level signals dir ect ly
fr om a br idge and out put s a ser ial digit al wor d. Ther e ar e t wo buffer ed differ ent ial
input s which ar e mult iplexed, buffer ed, and dr ive a PGA. The PGA can be
pr ogr ammed for four differ ent ial unipolar analog input r anges: 0V t o +10mV, 0V t o
+20mV, 0V t o +40mV, and 0V t o +80mV and four differ ent ial bipolar input r anges:
10mV, 20mV, 40mV, and 80mV. The maximum peak-t o-peak, or noise-fr ee
r esolut ion achievable is 1 in 230,000 count s, or appr oximat ely 18-bit s. It should be
not ed t hat t he noise-fr ee r esolut ion is a funct ion of input volt age r ange, filt er cut off,
and out put wor d r at e. Noise is gr eat er using t he smaller input r anges wher e t he
PGA gain must be incr eased. Higher out put wor d r at es and associat ed higher filt er
cut off fr equencies will also incr ease t he noise.
The analog input s ar e buffer ed on-chip allowing r elat ively high sour ce impedances.
Bot h analog channels ar e differ ent ial, wit h a common mode volt age r ange t hat
comes wit hin 1.2V of AGND and 0.95V of AVDD. The r efer ence input is also
differ ent ial, and t he common mode r ange is fr om AGND t o AVDD.
8.26
AD7730 SINGLE-SUPPLY BRIDGE ADC
MUX

PGA
SIGMA-
DELTA
MODULATOR
PROGRAMMABLE
DIGITAL
FILTER
REFERENCE DETECT
CALIBRATION
MICROCONTROLLER
6-BIT
DAC
+
+/
AC
EXCITATION
CLOCK
CLOCK
GENERATION
REGISTER BANK
SIGMA-DELTA ADC
SERIAL INTERFACE
AND CONTROL LOGIC
VBIAS
AIN1(+)
AIN1()
AIN2(+)/D1
AIN2()/D0
ACX
ACX
AVDD DVDD REFIN() REFIN(+)
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
AGND DGND POL RDY RESET
100nA
100nA
BUFFER
AD7730
+
_
Figure 8.27
n Resolution of 80,000 Counts Peak-to-Peak (16.5-Bits)
for 10mV Fullscale Range
n Chop Mode for Low Offset and Drift
n Offset Drift: 5nV/C (Chop Mode Enabled)
n Gain Drift: 2ppm/C
n Line Frequency Common Mode Rejection: > 150dB
n Two-Channel Programmable Gain Front End
n On-Chip DAC for Offset/TARE Removal
n FASTStep Mode
n AC Excitation Output Drive
n Internal and System Calibration Options
n Single +5V Supply
n Power Dissipation: 65mW, (125mW for 10mV FS Range)
n 24-Lead SOIC and 24-Lead TSSOP Packages
Figure 8.28
8.27
The 6-bit DAC is cont r olled by on-chip r egist er s and can r emove TARE (pan weight )
values of up t o 80mV fr om t he analog input signal r ange. The r esolut ion of t he
TARE funct ion is 1.25mV wit h a +2.5V r efer ence and 2.5mV wit h a +5V r efer ence.
The out put of t he PGA is applied t o t he modulat or and pr ogr ammable digit al
filt er . The ser ial int er face can be configur ed for t hr ee-wir e oper at ion and is
compat ible wit h micr ocont r oller s and digit al signal pr ocessor s. The AD7730 cont ains
self-calibr at ion and syst em-calibr at ion opt ions and has an offset dr ift of less t han
5nV/C and a gain dr ift of less t han 2ppm/C. This low offset dr ift is obt ained using a
chop mode which oper at es similar ly t o a chopper -st abilized amplifier .
The over sampling fr equency of t he AD7730 is 4.9152MHz, and t he out put dat a r at e
can be set fr om 50Hz t o 1200Hz. The clock sour ce can be pr ovided via an ext er nal
clock or by connect ing a cr yst al oscillat or acr oss t he MCLK IN and MCLK OUT pins.
The AD7730 can accept input signals fr om a DC-excit ed br idge. It can also handle
input signals fr om an AC-excit ed br idge by using t he AC excit at ion clock signals
(ACX and ACX). These ar e non-over lapping clock signals used t o synchr onize t he
ext er nal swit ches which dr ive t he br idge. The ACX clocks ar e demodulat ed on t he
AD7730 input .
The AD7730 cont ains t wo 100nA const ant cur r ent gener at or s, one sour ce cur r ent
fr om AVDD t o AIN(+) and one sink cur r ent fr om AIN() t o AGND. The cur r ent s ar e
swit ched t o t he select ed analog input pair under t he cont r ol of a bit in t he Mode
Regist er . These cur r ent s can be used in checking t hat a sensor is st ill oper at ional
befor e at t empt ing t o t ake measur ement s on t hat channel. If t he cur r ent s ar e t ur ned
on and a fullscale r eading is obt ained, t hen t he sensor has gone open cir cuit . If t he
measur ement is 0V, t he sensor has gone shor t cir cuit . In nor mal oper at ion, t he
bur nout cur r ent s ar e t ur ned off by set t ing t he pr oper bit in t he Mode Regist er t o 0.
The AD7730 cont ains an int er nal pr ogr ammable digit al filt er . The filt er consist s of
t wo sect ions: a fir st st age filt er , and a second st age filt er . The fir st st age is a sinc
3
lowpass filt er . The cut off fr equency and out put r at e of t his fir st st age filt er is
pr ogr ammable. The second st age filt er has t hr ee modes of oper at ion. In it s nor mal
mode, it is a 22-t ap FIR filt er t hat pr ocesses t he out put of t he fir st st age filt er . When
a st ep change is det ect ed on t he analog input , t he second st age filt er ent er s a second
mode (FASTSt ep) wher e it per for ms a var iable number of aver ages for some t ime
aft er t he st ep change, and t hen t he second st age filt er swit ches back t o t he FIR filt er
mode. The t hir d opt ion for t he second st age filt er (SKIP mode) is t hat it is
complet ely bypassed so t he only filt er ing pr ovided on t he AD7730 is t he fir st st age.
Bot h t he FASTSt ep mode and SKIP mode can be enabled or disabled via bit s in t he
cont r ol r egist er .
Figur e 8.29 shows t he full fr equency r esponse of t he AD7730 when t he second st age
filt er is set for nor mal FIR oper at ion. This r esponse is wit h t he chop mode enabled
and an out put wor d r at e of 200Hz and a clock fr equency of 4.9152MHz. The
r esponse is shown fr om DC t o 100Hz. The r eject ion at 50Hz 1Hz and 60Hz 1Hz
is bet t er t han 88dB.
8.28
Figur e 8.30 shows t he st ep r esponse of t he AD7730 wit h and wit hout t he FASTSt ep
mode enabled. The ver t ical axis shows t he code value and indicat es t he set t ling of
t he out put t o t he input st ep change. The hor izont al axis shows t he number of out put
wor ds r equir ed for t hat set t ling t o occur . The posit ive input st ep change occur s at
t he 5t h out put . In t he nor mal mode (FASTSt ep disabled), t he out put has not
r eached it s final value unt il t he 23r d out put wor d. In FASTSt ep mode wit h chopping
enabled, t he out put has set t led t o t he final value by t he 7t h out put wor d. Bet ween
t he 7t h and t he 23r d out put , t he FASTSt ep mode pr oduces a set t led r esult , but wit h
addit ional noise compar ed t o t he specified noise level for nor mal oper at ing
condit ions. It st ar t s at a noise level compar able t o t he SKIP mode, and as t he
aver aging incr eases ends up at t he specified noise level. The complet e set t ling t ime
r equir ed for t he par t t o r et ur n t o t he specified noise level is t he same for FASTSt ep
mode and nor mal mode.
AD7730 DIGITAL FILTER FREQUENCY RESPONSE
0
10
20
30
40
50
60
70
80
90
110
120
130
0 10 20 30 40 50 60 70 80 90 100
GAIN
(dB)
FREQUNCY (Hz)
SINC
3
+ 22-TAP FIR FILTER,
CHOP MODE ENABLED
Figure 8.29
The FASTSt ep mode gives a much ear lier indicat ion of wher e t he out put channel is
going and it s new value. This feat ur e is ver y useful in weigh scale applicat ions t o
give a much ear lier indicat ion of t he weight , or in an applicat ion scanning mult iple
channels wher e t he user does not have t o wait t he full set t ling t ime t o see if a
channel has changed.
8.29
Not e, however , t hat t he FASTSt ep mode is not par t icular ly suit able for mult iplexed
applicat ions because of t he excess noise associat ed wit h t he set t ling t ime. For
mult iplexed applicat ions, t he full 23-cycle out put wor d int er val should be allowed for
set t ling t o a new channel. This point s out t he fundament al issue of using ADCs
in mult iplexed applicat ions. Ther e is no r eason why t hey won't wor k, pr ovided t he
int er nal digit al filt er is allowed t o set t le fully aft er swit ching channels.
AD7730 DIGITAL FILTER SETTLING TIME
SHOWING FASTStep MODE
0 5 10 15 20 25
20,000,000
15,000,000
10,000,000
5,000,000
0
CODE
NUMBER OF OUTPUT SAMPLES
FASTStep ENABLED
FASTStep DISABLED
Figure 8.30
The calibr at ion modes of t he AD7730 ar e given in Figur e 8.31. A calibr at ion cycle
may be init iat ed at any t ime by wr it ing t o t he appr opr iat e bit s of t he Mode Regist er .
Calibr at ion r emoves offset and gain er r or s fr om t he device.
The AD7730 gives t he user access t o t he on-chip calibr at ion r egist er s allowing an
ext er nal micr opr ocessor t o r ead t he device's calibr at ion coefficient s and also t o wr it e
it s own calibr at ion coefficient s t o t he par t fr om pr est or ed values in ext er nal
E
2
PROM. This gives t he micr opr ocessor much gr eat er cont r ol over t he AD7730's
calibr at ion pr ocedur e. It also means t hat t he user can ver ify t hat t he device has
per for med it s calibr at ion cor r ect ly by compar ing t he coefficient s aft er calibr at ion
wit h pr est or ed values in E
2
PROM. Since t he calibr at ion coefficient s ar e der ived by
8.30
per for ming a conver sion on t he input volt age pr ovided, t he accur acy of t he
calibr at ion can only be as good as t he noise level t he par t pr ovides in t he nor mal
mode. To opt imize calibr at ion accur acy, it is r ecommended t o calibr at e t he par t at
it s lowest out put r at e wher e t he noise level is lowest . The coefficient s gener at ed at
any out put r at e will be valid for all select ed out put updat e r at es. This scheme of
calibr at ing at t he lowest out put dat a r at e does mean t hat t he dur at ion of t he
calibr at ion int er val is longer .
AD7730 SIGMA-DELTA ADC CALIBRATION OPTIONS
n Internal Zero-ScaleCalibration
u 22 Output Cycles (CHP = 0)
n Internal Full-Scale Calibration
n Calibration Programmed via the Mode Register
n Calibration Coefficients Stored in Calibration
Registers
n External Microprocessor Can Read or Write to
Calibration Coefficient Registers
Figure 8.31
The AD7730 r equir es an ext er nal volt age r efer ence, however , t he power supply may
be used as t he r efer ence in t he r at iomet r ic br idge applicat ion shown in Figur e 8.32.
In t his configur at ion, t he br idge out put volt age is dir ect ly pr opor t ional t o t he br idge
dr ive volt age which is also used t o est ablish t he r efer ence volt ages t o t he AD7730.
Var iat ions in t he supply volt age will not affect t he accur acy. The SENSE out put s of
t he br idge ar e used for t he AD7730 r efer ence volt ages in or der t o eliminat e er r or s
caused by volt age dr ops in t he lead r esist ances.
8.31
AD7730 BRIDGE APPLICATION (SIMPLIFIED SCHEMATIC)
+5V
AV
DD
AGND
+ A
IN
A
IN
+ V
REF
V
REF
R
LEAD
R
LEAD
6-LEAD
BRIDGE
AD7730
ADC
24 BITS
+SENSE
SENSE
V
O
+FORCE
FORCE
DV
DD
+5V/+3V
DGND
Figure 8.32
The AD7730 has a high impedance input buffer which isolat es t he analog input s
fr om swit ching t r ansient s gener at ed in t he PGA and t he sigma-delt a modulat or .
Ther efor e, no special pr ecaut ions ar e r equir ed in dr iving t he analog input s. Ot her
member s of t he AD77XX family, however , eit her do not have t he input buffer , or if
one is included on-chip, it can be swit ched eit her in or out under pr ogr am cont r ol.
Bypassing t he buffer offer s a slight impr ovement in noise per for mance. The
equivalent input cir cuit of t he AD77XX family wit hout an input buffer is shown in
Figur e 8.33. The input swit ch alt er nat es bet ween t he 10pF sampling capacit or and
gr ound. The 7k int er nal r esist ance, R
INT
, is t he on-r esist ance of t he input
mult iplexer . The swit ching fr equency is dependent on t he fr equency of t he input
clock and also t he PGA gain. If t he conver t er is wor king t o an accur acy of 20-bit s,
t he 10pF int er nal capacit or , C
INT
, must char ge t o 20-bit accur acy dur ing t he t ime
t he swit ch connect s t he capacit or t o t he input . This int er val is one-half t he per iod of
t he swit ching signal (it has a 50% dut y cycle). The input RC t ime const ant due t o
t he 7k r esist or and t he 10pF sampling capacit or is 70ns. If t he char ge is t o achieve
20-bit accur acy, t he capacit or must char ge for at least 14 t ime const ant s, or 980ns.
Any ext er nal r esist ance in ser ies wit h t he input will incr ease t his t ime const ant .
Ther e ar e t ables on t he dat a sheet s for t he var ious AD77XX ADCs which give t he
maximum allowable values of R
EXT
in or der maint ain a given level of accur acy.
These t ables should be consult ed if t he ext er nal sour ce r esist ance is mor e t han a few
k.
8.32
DRIVING UNBUFFERED AD77XX-SERIES ADC INPUTS
HIGH
IMPEDANCE
> 1G
SWITCHING FREQ
DEPENDS ON f
CLKIN
AND GAIN
C
INT

10pF
TYP
R
EXT
R
INT
7k
~
R
EXT
Increases C
INT
Charge Time and May Result in Gain Error
Charge Time Dependent on the Input Sampling Rate and Internal
PGA Gain Setting
Refer to Specific Data Sheet for Allowable Values of R
EXT
to
Maintain Desired Accuracy
Some AD77XX-Series ADCs Have Internal Buffering Which Isolates
Input from Switching Circuits
AD77XX-Series
(WITHOUT BUFFER)
V
SOURCE
Figure 8.33
Simult aneous sampling of mult iple channels is r elat ively common in dat a
acquisit ion syst ems. If sigma-delt a ADCs ar e used as shown in Figur e 8.34, t heir
out put s must be synchr onized. Alt hough t he input s ar e sampled at t he same inst ant
at a r at e Kf
s
, t he decimat ed out put wor d r at e, f
s
, is gener ally der ived int er nally in
each ADC by dividing t he input sampling fr equency by K. The out put dat a must
t her efor e be synchr onized by t he same clock at t he f
s
fr equency. The SYNC input of
t he AD77XX family can be used for t his pur pose.
Pr oduct s such as t he AD7716 include mult iple sigma-delt a ADCs in a single IC, and
pr ovide t he synchr onizat ion aut omat ically. The AD7716 is a quad sigma-delt a ADC
wit h up t o 22-bit r esolut ion and an input over sampling r at e of 570kSPS. A
funct ional diagr am of t he AD7716 is shown in Figur e 8.35, and key specificat ions in
Figur e 8.36. The cut off fr equency of t he digit al filt er s (which may be changed dur ing
oper at ion, but only at t he cost of a loss of valid dat a for a shor t t ime while t he filt er s
clear ) is pr ogr ammed by t he dat a wr it t en t o t he cont r ol r egist er . The out put wor d
r at e depends on t he cut off fr equency chosen. The AD7716 cont ains an aut o-zer oing
syst em t o minimize input offset dr ift .
8.33
SYNCHRONIZING MULTIPLE SIGMA-DELTA ADCs
IN SIMULTANEOUS SAMPLING APPLICATIONS
SIGMA-DELTA ADC
K
SIGMA-DELTA ADC
Kf
s
f
s
DATA
OUTPUT
DATA
OUTPUT
ANALOG
INPUTS
SYNC
SYNC
Figure 8.34
AD7716 MULTICHANNEL SIGMA-DELTA ADC
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
CONTROL
REGISTER
CLOCK
GENERATION
AVDD DVDD AVSS RESET A0 A1 A2 CLKIN CLKOUT
VREF AGND DGND DIN1 DOUT1 DOUT2
MODE
CASCIN
CASCOUT
RFS
SDATA
SCLK
DRDY
TFS
AIN1
AIN2
AIN3
AIN4
Figure 8.35
8.34
n Up to 22-Bit Resolution, 4 Input Channels
n Sigma-Delta Architecture, 570kSPS Oversampling Rate
n On-Chip Lowpass Filter, Programmable from 36.5Hz to 584Hz
n Serial Input / Output Interface
n 5V Power Supply Operation
n 50mW Power Dissipation
Figure 8.36
AP P LI CATI ONS OF SI GMA-DELTA ADCS I N P OWER
METERS
While elect r omechanical ener gy met er s have been popular for over 50 year s, a solid-
st at e ener gy met er deliver s far mor e accur acy and flexibilit y. J ust as impor t ant , a
well designed solid-st at e met er will have a longer useful life. The AD7750 Pr oduct -
t o-Fr equency Conver t er is t he fir st of a family of ICs designed t o implement t his
t ype of met er .
We must fir st consider t he fundament als of power measur ement (see Figur e 8.37).
Inst ant aneous AC volt age is given by t he expr ession v(t ) = Vcos(t ), and t he
cur r ent (assuming it is in phase wit h t he volt age) by i(t ) = Icos(t ). The
instantaneous power is t he pr oduct of v(t ) and i(t ):
p(t ) = VIcos
2
(t )
Using t he t r igonomet r ic ident it y, 2cos
2
(t ) = 1 + cos(2t ),
[ ]
p t
V I
t ( ) cos( ) =

+
2
1 2 = Inst ant aneous Power .
The instantaneous real power is simply t he aver age value of p(t ). It can be shown
t hat comput ing t he inst ant aneous r eal power in t his manner gives accur at e r esult s
even if t he cur r ent is not in phase wit h t he volt age (i.e., t he power fact or is not
unit y. By definit ion, t he power fact or is equal t o cos, wher e is t he phase angle
bet ween t he volt age and t he cur r ent ). It also gives t he cor r ect r eal power if t he
wavefor ms ar e non-sinusoidal.
8.35
BASICS OF POWER MEASUREMENTS
v(t) = V cos( t) (Instantaneous Voltage)
i(t) = I cos( t) (Instantaneous Current)
p(t) = V I cos
2
( t) (Instantaneous Power)
V I
2
= 1 + cos(2 t) p(t)
Average Value of p(t) = Instantaneous Real Power
Includes Effects of Power Factor and Waveform Distortion
Figure 8.37
The AD7750 implement s t hese calculat ions, and a block diagr am is shown in Figur e
8.38. Ther e ar e t wo input s t o t he device. The differ ent ial volt age bet ween V1+ and
V1 is a volt age cor r esponding t o t he inst ant aneous cur r ent . It is usually der ived
fr om a small t r ansfor mer placed in ser ies wit h t he line. The AD7750 is designed
wit h a swit ched capacit or ar chit ect ur e t hat allows a bipolar analog input wit h a
single +5V supply. The input volt age passes t hr ough a PGA which can be set for a
gain of 1 or 16. The gain of 16 opt ion allows for low values of shunt impedances in
t he cur r ent monit or ing cir cuit . The out put of t he PGA dr ives a 2nd or der 16-bit
sigma-delt a modulat or which samples t he signal at a 900kHz r at e. The ser ial bit
st r eam fr om t he modulat or is passed t hr ough a digit al highpass filt er t o r emove any
DC component . The highpass filt er has a phase lead of 2.58 at 50Hz. In or der t o
equalize t he phase differ ence bet ween t he t wo channels, a fixed delay of 143s is
t hen int r oduced in t he signal pat h. Because t he t ime delay is fixed, ext er nal phase
compensat ion will be r equir ed if t he line fr equency differ s fr om 50Hz. Ther e ar e
sever al ways t o accomplish t his, and t hey ar e descr ibed in det ail in t he AD7750 dat a
sheet .
The differ ent ial volt age applied bet ween V2+ and V2 r epr esent s t he volt age
wavefor m (scaled t o t he AD7750 input r ange). It is passed t hr ough a gain of 2
amplifier and a second sigma-delt a modulat or . The volt age and cur r ent out put s ar e
t hen mult iplied digit ally yielding t he instantaneous power. The instantaneous real
power is t hen obt ained by passing t he inst ant aneous power t hr ough a digit al
lowpass filt er . The low fr equency out put s F1 and F2 ar e gener at ed by accumulat ing
t his r eal power infor mat ion. The F1 and F2 out put s pr ovide t wo alt er nat ing low-
going pulses. This low fr equency inher ent ly means a long accumulat ion t ime
bet ween out put pulses. The out put fr equency is t her efor e pr opor t ional t o t he average
real power. This aver age r eal power infor mat ion can in t ur n be accumulat ed (e.g., an
elect r omechanical pulse count er or full st epping t wo phase st epper -mot or ) t o
gener at e r eal ener gy infor mat ion. The pulse widt h is set at 275ms. The fr equency of
t hese pulses is 0Hz t o about 14Hz.
8.36
AD7750 PRODUCT-TO-FREQUENCY CONVERTER
16
2ND ORDER
SIGMA-DELTA
MODULATOR
2
2ND ORDER
SIGMA-DELTA
MODULATOR
DIGITAL
HIGHPASS
FILTER
DELAY
DIGITAL
LOWPASS
FILTER
DIGITAL TO
FREQUENCY
CONVERTER
DIGITAL TO
FREQUENCY
CONVERTER
2.5V
BANDGAP
REFERENCE
G1 VDD ACDC
REVP
CLK
OUT
CLK
IN
F1
F2
FOUT
AGND REFOUT REFIN FS S1 S2 DGND
V1+
V1
V2+
V2
+
_
+
_
AD7750
Instantaneous
Real Power
Instantaneous Power
(CURRENT)
(VOLTAGE)
= v(t) i(t)
v(t)
i(t)
Figure 8.38
Because of it s high out put fr equency and hence shor t er int egr at ion t ime, t he FOUT
out put is pr opor t ional t o t he instantaneous r eal power . This is useful for syst em
calibr at ion pur poses which would t ake place under st eady load condit ions.
The er r or in t he r eal power measur ement is less t han 0.2% over a dynamic r ange of
500:1 and less t han 0.4% over a dynamic r ange of 1000:1.
A single-phase power met er applicat ion is shown in Figur e 8.39. The gr ound for t he
ent ir e cir cuit is r efer enced t o t he neut r al line. The +5V power for t he cir cuit is
der ived fr om an AC t o DC supply which is power ed fr om t he phase (hot ) line. This
can be simple half-wave diode r ect ifier followed by a filt er capacit or . The F1 and F2
out put s dr ive t he kW-Hr count er which displays t he ener gy usage.
The REVP out put (r ever se polar it y) dr ives an LED and goes high when negat ive
power is det ect ed (i.e., when t he volt age and cur r ent signals ar e 180 out of phase).
This condit ion would gener ally indicat e a pot ent ial mis-wir ing condit ion.
The AD7751 Ener gy Met er ing IC oper at es in a similar fashion t o t he AD7750 but
has inhanced per for mance feat ur es. It has on-chip fault det ect ion cir cuit s which
monit or t he cur r ent in bot h t he phase (hot ) and neut r al line. A fault is indicat ed
when t hese cur r ent s differ by mor e t han 12.5%, and billing is cont inued using t he
lar ger of t he t wo cur r ent s.
8.37
AD7750 SINGLE PHASE POWER METER APPLICATION
(SIMPLIFIED SCHEMATIC)
16
ADC 1
+ HPF
2 ADC2
+
_
+
_
LOWPASS
FILTER +
DIGITAL TO
FREQUNCY
CONVERTER
0 0 0 5 1 4 7
AC TO DC
SUPPLY
kW-Hr COUNTER
+5V
PHASE (HOT)
NEUTRAL
TO LOAD
CALIBRATION
LED
REVERSE
POLARITY
LED
AD7750
i(t)
v(t)
REVP
F1
F2
FOUT
Figure 8.39
8.38
REFERENCES
1. S. A. J ant zi, M. Snelgrove & P. F. Ferguson J r., A 4th-Order Bandpass
Sigma-Delta Modulator, I EEE J ou r n a l of Soli d St a t e Ci r cu i t s,
Vol. 38, No. 3, Mar ch 1993, pp.282-291.
2. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1993, Sect ion 14.
3. Mi xed Si gn a l Desi gn Semi n a r , Analog Devices, Inc., 1991, Sect ion 6.
4. AD77XX-Ser i es Da t a Sh eet s, Analog Devices, ht t p://www.analog.com.
5. Li n ea r Desi gn Semi n a r , Analog Devices, Inc., 1995, Sect ion 8.
6. J . Dat t or r o, A. Char pent ier , D. Andr eas, The Implementation of a One-
S tage Multirate 64:1 FIR Decimator for use in One-Bit S igma-Delta A/ D
Applications, AES 7t h I n t er n a t i on a l Con fer en ce, May 1989.
7. W.L. Lee and C.G. Sodini, A Topology for Higher-Order Interpolative
Coders, I SCAS P ROC. 1987.
8. P.F. Fer guson, J r ., A. Ganesan and R. W. Adams, One Bit Higher Order
S igma-Delta A/ D Converters, I SCAS P ROC. 1990, Vol. 2, pp. 890-893.
9. R. Koch, B. Heise, F. Eckbauer , E. Engelhar dt , J . Fisher , and F. Par zefall,
A 12-bit S igma-Delta Analog-to-Digital Converter with a 15MHz Clock
Rate, I EEE J ou r n a l of Soli d -St a t e Ci r cu i t s, Vol. SC-21, No. 6,
December 1986.
10. Wai Laing Lee, A Novel Higher Order Interpolative Modulator Topology
for High Resolution Oversampling A/ D Converters, MI T Ma st er s
Th esi s, J une 1987.
11. D. R. Welland, B. P. Del Signor e and E. J . Swanson, A S tereo 16-Bit
Delta-S igma A/ D Converter for Digital Audio, J . Au d i o En gi n eer i n g
Soci et y, Vol. 37, No. 6, J une 1989, pp. 476-485.
12. R. W. Adams, Design and Implementation of an Audio 18-Bit Analog-
to-Digital Converter Using Oversampling Techniques, J . Au d i o
En gi n eer i n g Soci et y, Vol. 34, Mar ch 1986, pp. 153-166.
13. B. Boser and Br uce Wooley, The Design of S igma-Delta Modulation
Analog-to-Digital Converters, I EEE J ou r n a l of Soli d -St a t e Ci r cu i t s,
Vol. 23, No. 6, December 1988, pp. 1298-1308.
14. Y. Mat suya, et . al., A 16-Bit Oversampling A/ D Conversion Technology
Using Triple-Integration Noise S haping, I EEE J ou r n a l of Soli d -St a t e
Ci r cu i t s, Vol. SC-22, No. 6, December 1987, pp. 921-929.
8.39
15. Y. Mat suya, et . al., A 17-Bit Oversampling D/ A Conversion Technology
Using Multistage Noise S haping, I EEE J ou r n a l of Soli d -St a t e Ci r cu i t s,
Vol. 24, No. 4, August 1989, pp. 969-975.
16. P. Fer guson, J r ., A. Ganesan, R. Adams, et . al., An 18-Bit 20-kHz Dual
S igma-Delta A/ D Converter, I SSCC Di gest of Tech n i ca l P a p er s,
Febr uar y 1991.
17. St even Har r is, The Effects of S ampling Clock J itter on Nyquist S ampling
Analog-to-Digital Converters and on Oversampling Delta S igma ADCs,
Au d i o En gi n eer i n g Soci et y Rep r i n t 2844 (F-4), Oct ober , 1989.
18. Max W. Hauser , Principles of Oversampling A/ D Conversion, J ou r n a l
Au d i o En gi n eer i n g Soci et y, Vol. 39, No. 1/2, J anuar y/Febr uar y 1991,
pp. 3-26.
19. Designing a Watt-Hour Energy Meter Based on the AD7750, AN-545,
Analog Devices, Inc., ht t p://www.analog.com.
20. Daniel H. Sheingold, An a log-Di gi t a l Con ver si on Ha n d book ,
Thir d Edit ion, Pr ent ice-Hall, 1986.
SMART SENSORS
9.1
SECTI ON 9
SMART SENSORS
Wa l t Kest er , Bi l l Ch est n u t , Gr a yson Ki n g
4-20MA CONTROL LOOP S
Indust r ial pr ocess cont r ol syst ems make ext ensive use of 4-20mA cont r ol loops.
Many sensor s and act uat or s ar e designed pr ecisely for t his mode of cont r ol. They ar e
popular because t hey ar e simple t o under st and, offer a met hod of st andar dizing t he
sensor /cont r ol int er face, and ar e r elat ively immune t o noise. Figur e 9.1 shows how a
r emot e act uat or is cont r olled via such a loop fr om a cent r ally locat ed cont r ol r oom.
Not ice t hat t he t r ansmit t er out put t o t he act uat or is cont r olled by a DAC, in t his
case, t he AD420. The ent ir e pr ocess is under t he cont r ol of a host comput er which
int er faces t o t he micr ocont r oller and t he AD420. This diagr am shows only one
act uat or , however an act ual indust r ial cont r ol syst em would have many act uat or s
and sensor s. Not ice t hat t he "zer o scale" out put of t he DAC is act ually 4mA, and
"fullscale" is 20mA. The choice of a non-zer o out put cur r ent for "zer o scale" allows
open cir cuit det ect ion at t he t r ansmit t er and allows t he loop t o act ually power t he
r emot e sensor if it s cur r ent r equir ement is less t han 4mA.
CONTROLLING A REMOTE ACTUATOR
USING A 4-20mA LOOP
4-20mA
DAC
C
HOST
COMPUTER
REGULATOR
LOOP
SUPPLY
R
SENSE
CONTROL ROOM
4-20mA
OUTPUT
ACTUATOR
AD420
12V TO 32V
LOOP
RETURN
Figure 9.1
Many of t he cont r ol r oom cir cuit s ar e dir ect ly power ed by t he loop power supply
which can r ange fr om appr oximat ely 12V t o 36V. In many cases, however , t his
volt age must be r egulat ed t o supply such devices as amplifier s, ADCs, and
micr ocont r oller s. The loop cur r ent is sensed by t he R
SENSE
r esist or which is
act ually a par t of t he AD420. The int er nal DAC in t he AD420 is a sigma-delt a t ype
SMART SENSORS
9.2
wit h 16-bit r esolut ion and monot onicit y. The ser ial digit al int er face allows easy
int er face t o t he micr ocont r oller .
Figur e 9.2 shows a 4-20mA out put "smar t " sensor which is complet ely power ed by
t he loop power supply. In or der for t his t o wor k, t he sum t ot al of all t he cir cuit s
under loop power can be no mor e t han 4mA. The hear t of t he cir cuit is t he AD421
loop-power ed 16-bit DAC. The int er nal 4-20mA DAC cur r ent as well as t he r est of
t he r et ur n cur r ent fr om t he AD421 and t he ot her cir cuit s under loop power flows
t hr ough t he R
SENSE
r esist or . The sensing cir cuit compensat es for t he addit ional
r et ur n cur r ent and ensur es t hat t he act ual loop r et ur n cur r ent cor r esponds t o t hat
r equir ed by t he digit al code applied t o t he DAC t hr ough t he micr ocont r oller . The
sensor out put is digit ized by t he AD7714/AD7715 sigma-delt a ADC. Not e t hat t he
t ot al cur r ent r equir ed by all t he cir cuit s under loop power is less t han t he r equir ed
4mA maximum. The AD421 cont ains a r egulat or cir cuit which cont r ols t he gat e of
t he ext er nal DMOS FET and r egulat es t he loop volt age t o eit her 3V, 3.3V, or 5V t o
power t he loop cir cuit s. In t his way t he maximum loop supply volt age is limit ed only
by t he br eakdown volt age of t he DMOS FET.
4-20mA LOOP POWERED SMART SENSOR
S
E
N
S
O
R
ADC C
4-20mA
DAC
R
SENSE
AD421
I
COMMON
< 4.00mA
ADC C
HOST
COMPUTER
REGULATOR
LOOP
SUPPLY
R
SENSE
3.3V / 5V
AD7714/AD7715
I
AD421
< 0.75mA
CONTROL ROOM
DMOS FET
DMOS FET: Supertex DN2535
Siliconix ND2020L or ND2410L
4-20mA
RETURN
LOOP
POWER
I
C+SENSOR
< 2.75mA
I
AD7714/AD7715
< 0.50mA
I
COMMON
Figure 9.2
The HART pr ot ocol uses a fr equency shift keying (FSK) t echnique based on t he Bell
202 Communicat ions St andar d which is one of sever al st andar ds used t o t r ansmit
digit al signals over t he t elephone lines. This t echnique is used t o super impose digit al
communicat ion on t o t he 4-20mA cur r ent loop connect ing t he cont r ol r oom t o t he
t r ansmit t er in t he field. Two differ ent fr equencies, 1200Hz and 2200Hz, ar e used t o
r epr esent binar y 1 and 0 r espect ively. These sinewave t ones ar e super imposed on
t he DC signal at a low level wit h t he aver age value of t he sinewave being zer o. This
allows simult aneous analog and digit al communicat ions. Addit ionally, no DC
component is added t o t he exist ing 4-20mA signal r egar dless of t he digit al dat a
SMART SENSORS
9.3
being sent over t he line. The phase of t he digit al FSK signal is cont inuous, so t her e
ar e no high fr equency component s inject ed ont o t he 4-20mA loop. Consequent ly,
exist ing analog inst r ument s cont inue t o wor k in syst ems t hat implement HART, as
t he lowpass filt er ing usually pr esent effect ively r emoves t he digit al signal. A single
pole 10Hz lowpass filt er effect ively r educes t he communicat ion signal t o a r ipple of
about 0.01% of t he fullscale signal. The HART pr ot ocol specifies t hat mast er
devices like a host cont r ol syst em t r ansmit a volt age signal, wher eas a slave or field
device t r ansmit s a cur r ent signal. The cur r ent signal is conver t ed int o a
cor r esponding volt age by t he loop load r esist or in t he cont r ol r oom.
Figur e 9.3 shows a block diagr am of a smar t and int elligent t r ansmit t er . An
int elligent t r ansmit t er is a t r ansmit t er in which t he funct ion of t he micr opr ocessor
ar e shar ed bet ween der iving t he pr imar y measur ement signal, st or ing infor mat ion
r egar ding t he t r ansmit t er it self, it s applicat ion dat a, and it s locat ion, and also
managing a communicat ion syst em which enables t wo-way communicat ion t o be
super imposed on t he same cir cuit t hat car r ies t he measur ement signal. A smar t
t r ansmit t er incor por at ing t he HART pr ot ocol is an example of a smar t int elligent
t r ansmit t er .
HART INTELLIGENT REMOTE TRANSMITTER
USING AD421 LOOP-POWERED 4-20mA DAC
S
E
N
S
O
R
ADC C
4-20mA
DAC
AD421
HART
MODEM
BELL 202
WAVEFORM
SHAPER
BANDPASS
FILTER
LOOP POWER
LOOP RETURN
C
C
HT20C12 / 20C15 (Symbios Logic)
HART DIGITAL SIGNAL: 1200Hz, 2200Hz FREQUENCY SHIFT KEYING (FSK)
Figure 9.3
The HART dat a t r ansmit t ed on t he loop shown in Figur e 9.3 is r eceived by t he
t r ansmit t er using a bandpass filt er and modem, and t he HART dat a is t r ansfer r ed
t o t he micr ocont r oller 's UART or asynchr onous ser ial por t t o t he modem. It is t hen
waveshaped befor e being coupled ont o t he AD421's out put t hr ough t he coupling
capacit or C
C
. The block cont aining t he Bell 202 Modem, waveshaper , and bandpass
filt er come in a complet e solut ion wit h t he 20C15 fr om Symbios Logic, Inc., or
HT2012 fr om SMAR Resear ch Cor por at ion.
SMART SENSORS
9.4
I NTERFACI NG SENSORS TO NETWORKS
Gr a yson Ki n g
The HART pr ot ocol is just one of many st andar ds for indust r ial net wor king. Most
indust r ial net wor ks r un independent ly of analog 4-20mA lines, but many ar e
int ended t o int er face (dir ect ly or indir ect ly) wit h smar t sensor s as shown in Figur e
9.4.
INDUSTRIAL NETWORKING
NODE FIELD NETWORK NODE
N
O
D
E
BRANCH
N
O
D
E
S
M
A
R
T

S
E
N
S
O
R
S
M
A
R
T

S
E
N
S
O
R
D
E
V
I
C
E

N
E
T
W
O
R
K
SMART SENSOR
SMART SENSOR
Figure 9.4
These indust r ial net wor ks can t ake many for ms. The field net wor k in Figur e 9.4
r epr esent s a wide bandwidt h dist r ibut ed net wor k such as Et her net or Lonwor k. A
field net wor k by t his definit ion is not gener ally int ended t o int er face dir ect ly wit h a
smar t sensor . A device net wor k, on t he ot her hand, is int ended specifically t o
int er face t o smar t sensor s. Most device net wor ks (such as ASI-bus, CAN-bus, and
HART) also pr ovide power t o smar t sensor s on t he same lines t hat car r y ser ial dat a.
Some of t odays mor e popular indust r ial net wor k st andar ds ar e list ed in Figur e 9.5.
Each offer s it s own advant ages and disadvant ages, and each has a unique har dwar e
implement at ion and ser ial pr ot ocol. This means t hat a smar t sensor designed for one
indust r ial net wor k is not necessar ily compat ible wit h anot her .
Since fact or ies and many ot her net wor ked envir onment s oft en have mult iple
net wor ks and sub-net wor ks, a far mor e flexible solut ion is one wher e sensor s ar e
plug and play compat ible wit h all differ ent field and device net wor ks. The goal of
t he IEEE 1451.2 sensor int er face st andar d is t o make net wor k independent sensor s
a r ealit y.
SMART SENSORS
9.5
SOME OF THE STANDARDS
n Ethernet
n Foundation Fieldbus
n Lonwork
n Profibus
n Interbus-S
n Universal Serial Bus (USB)
n CAN-Bus
n Device-Net
n WorldFIP
n P-NET
n HART
n ASI
Figure 9.5
Figur e 9.6 shows t he basic component s of an IEEE 1451.2 compat ible syst em. The
smar t sensor (or smar t act uat or ) is r efer r ed t o as a STIM (Smar t Tr ansducer
Int er face Module). It cont ains one or mor e sensor s and/or act uat or s in addit ion t o
any signal condit ioning and A/D or D/A conver sion r equir ed t o int er face t he
sensor s/act uat or s wit h t he r esident micr ocont r oller . The micr ocont r oller also has
access t o nonvolat ile memor y t hat cont ains a TEDS field (or Tr ansducer Elect r onic
Dat a Sheet ) which st or es sensor /act uat or specificat ions t hat can be r ead via t he
indust r ial net wor k. The NCAP (Net wor k Capable Applicat ion Pr ocessor ) is basically
a node on t he net wor k t o which a STIM can be connect ed. At t he hear t of t he IEEE
1451.2 is t he st andar dized 10-wir e ser ial int er face bet ween t he sensor and t he
NCAP, called t he TII (or Tr ansducer Independent Int er face). In an envir onment
wit h mult iple net wor ks, t he TII allows any STIM t o be plugged int o any NCAP node
on any net wor k as shown in Figur e 9.7. When t he STIM is fir st connect ed t o t he
new NCAP, t he STIMs digit al infor mat ion (including it s TEDS) is made available t o
t he net wor k. This ident ifies what t ype of sensor or act uat or has just been connect ed
and indicat es what input and out put dat a ar e available, t he unit s of input an out put
dat a (cubic met er s per second, degr ees Kelvin, kilopascals, et c.), t he specified
accur acy of t he sensor (2C, et c.), and var ious ot her infor mat ion about t he sensor or
act uat or . This effect ively eliminat es t he soft war e configur at ion st eps involved in
r eplacing or adding a sensor , t her eby allowing t r ue plug and play per for mance
wit h net wor k independence.
SMART SENSORS
9.6
THE IEEE 1451.2 SENSOR INTERFACE STANDARD
NCAP FIELD NETWORK - OR - DEVICE NETWORK
TII
S
T
I
M
TEDS
Sensor
or
Actuator
n NCAP = Network Capable Application
Processor
n TII = Transducer Independent
Interface
n TEDS = Transducer Electronic Datasheet
n STIM = Smart Transducer Interface
Module
Figure 9.6
TRUE "PLUG AND PLAY"
Lonwork
NCAP
Ethernet
NCAP
Ethernet
NCAP
PC with
Web Browser
Lonwork
NCAP
Ethernet Field Network Lonwork Field Network

F
l
o
w

R
a
t
e

S
T
I
M

T
e
m
p
e
r
a
t
u
r
e

S
T
I
M

P
r
e
s
s
u
r
e

S
T
I
M
Figure 9.7
Most smar t sensor s (not limit ed t o 1451.2 STIMs) cont ain t he pr imar y component s
shown in Figur e 9.8. The Analog Devices Micr oConver t er
TM
pr oduct s ar e t he fir st t o
incor por at e all of t hese component s on a single chip (Figur e 9.9).
SMART SENSORS
9.7
THE SMART SENSOR
Precision Amplifier
High Resolution ADC
Microcontroller Sensor
Pressure Sensor,
RTD,
Thermocouple,
Strain Gage,
etc.
Figure 9.8
THE EVEN SMARTER SENSOR
Sensor MicroConverter
TM
!
Pressure Sensor,
RTD,
Thermocouple,
Strain Gage,
etc.
Figure 9.9
The t hr ee pr imar y funct ions of ever y Micr oConver t er
TM
pr oduct (Figur e 9.10), ar e:
high r esolut ion analog-t o-digit al and digit al-t o-analog conver sion, non-volat ile
FLASH EEPROM for pr ogr am and dat a st or age, and a micr ocont r oller . Of t he fir st
t hr ee Micr oConver t er
TM
pr oduct s t o be int r oduced, all cont ain a 12-bit volt age
out put DAC, a pr ecision bandgap volt age r efer ence, and an on-chip t emper at ur e
SMART SENSORS
9.8
sensor . Figur e 9.11 list s t he basic analog I/O funct ionalit y of each. All t hr ee have
exact ly t he same FLASH memor y and micr ocont r oller cor e, some feat ur es of which
ar e highlight ed in Figur es 9.12 and 9.13.
THE MicroConverter
High Performance Analog I/O
+
On-Chip FLASH Memory
+
On-Chip Microcontroller
1
2
3
=
MicroConverter
Figure 9.10
ANALOG I/O 1
n Dual ADC
u>16 bit
u>100dB SNR (p-p)
uDifferential Inputs
uProg. Gain Amp
uSelf-Calibration
n 12bit V-Out DAC
u< LSB DNL
n Voltage Reference
n Temperature Sensor
n 8 chan SAR ADC
u 10 bit
u < LSB INL
n 12bit V-Out DAC
u < LSB DNL
n Voltage Reference
n 8 chan SAR ADC
u12 bit, 5s
u< LSB INL
uDMA mode
uSelf-Calibration
n Dual 12bit V-Out DAC
u< LSB DNL
n Voltage Reference
ADuC816
ADuC812 ADuC810
Figure 9.11
SMART SENSORS
9.9
ON-CHIP FLASH MEMORY 2
n 8K bytes Nonvolatile FLASH Program Memory
u Stores Program and Fixed Lookup Tables
u In-Circuit Serial Programmable or External Parallel Programmable
u Read-Only to Microprocessor Core
n 640 bytes Nonvolatile FLASH Data Memory
u User Scratch Pad for Storing Data During Program Execution
u Simple Read / Write Access Through SFR Space
n Programming Voltage (V
PP
) Generated On-Chip
ADuC816 ; ADuC812 ; ADuC810
Figure 9.12
ON-CHIP MICROCONTROLLER 3
n Industry Standard 8052 Core
u 12 Clock Machine Cycle w/ up to 16MHz Clock
u 32 Digital I/O Pins
u Three 16bit Counter/Timers
u Universal Asynchronous Receiver/Transmitter
(UART) Serial Port
n ...Plus Some Useful Extras
u SPI or I2C Compatible Serial Interface
u WatchDog Timer
u Power Supply Monitor
u Timer Interval Counter (ADuC816/810)
ADuC816 ; ADuC812 ; ADuC810
Figure 9.13
SMART SENSORS
9.10
The highest r esolut ion Micr oConver t er
TM
pr oduct is t he ADuC816. It s analog fr ont
end consist s of t wo separ at e ADC conver t er s wit h a flexible mult iplexing scheme
t o access it s t wo differ ent ial input channels as illust r at ed in t he funct ional block
diagr am of Figur e 9.14. The pr imar y channel ADC is a 24-bit conver t er t hat
offer s bet t er t han 16-bit signal-t o-noise r at io. This pr imar y channel also feat ur es a
pr ogr ammable gain amplifier (PGA), allowing dir ect conver sion of low-level signals
such as t her mocouples, RTDs, st r ain gages, et c. Two bur n out cur r ent sour ces can
be configur ed t o for ce a ver y small cur r ent t hr ough t he sensor t o det ect open cir cuit
condit ions when t he sensor may have been disconnect ed or bur ned out . The
pr imar y channel ADC can be mult iplexed t o conver t bot h of t he differ ent ial input
channels, or t he second differ ent ial input can be r out ed t o t he auxiliar y channel
ADC which is a 16-bit conver t er wit h bet t er t han 14-bit s of signal-t o-noise r at io.
This auxiliar y channel can also be used t o r ead t he on-chip t emper at ur e sensor . A
pair of 200A cur r ent sour ces (IEXC1 & IEXC2) can be used t o pr ovide excit at ion for
sensor s such as RTDs. Bot h ADCs as well as t he DAC can be oper at ed wit h t he
int er nal 2.5V bandgap r efer ence, or wit h an ext er nal r efer ence.
ADuC816 FUNCTIONAL BLOCK DIAGRAM
AIN
MUX
AIN
MUX
buf pga ADC
ADC
control
and
calibration
ADC
ADC
control
and
calibration
TEMP
sensor
2.5V
bandgap
reference
V
REF
detect
8K x 8
program
FLASH
EEPROM
640 x 8
user FLASH
synchronous
serial interface
(SPI or I2C)
8052
micro-
controller
core
256 x 8
user RAM
watchdog
timer
power supply
monitor
asynchronous
serial port
(UART)
16 bit
counter
timers
timer
interval
counter
OSC &
PLL
DAC
control
DAC1
buf
buf
A
V
D
D
A
G
N
D
D
V
D
D
D
G
N
D
S
C
L
K
S
D
A
T
A
/
M
O
S
I
M
I
S
O
S
S
A
L
E
P
S
E
N
E
A
R
E
S
E
T
R
x
D
T
x
D
X
T
A
L
1
X
T
A
L
2
(primary channel)
(auxilliary channel)
AIN1
AIN2
AIN3
AIN4
V
REF
IN+
V
REF
IN
I
EXC
1
I
EXC
2
DAC
T0
T1
T2
T2EX
INT0
INT1
3.5mV/C
ADuC816
5 6
2
0
3
4
4
7
2
1
3
5
4
8
2
6
2
7
1
4
1
3
4
2
4
1
4
0
1
5
1
6
1
7
3
2
3
3
4
3
4
4
4
5
4
6
4
9
5
0
5
1
5
2
1 2 3 4 9
1
0
1
1
1
2
2
8
2
9
3
0
3
1
3
6
3
7
3
8
3
9
1
6
1
7
1
8
1
9
2
2
2
3
2
4
2
5
9
10
11
12
8
7
3
4
10
22
23
1
2
18
19
P
0
.
0
P
0
.
1
P
0
.
2
P
0
.
3
P
0
.
4
P
0
.
5
P
0
.
6
P
0
.
7
P
1
.
0
P
1
.
1
P
1
.
2
P
1
.
3
P
1
.
4
P
1
.
5
P
1
.
6
P
1
.
7
P
2
.
0
P
2
.
1
P
2
.
2
P
2
.
3
P
2
.
4
P
2
.
5
P
2
.
6
P
2
.
7
P
3
.
0
P
3
.
1
P
3
.
2
P
3
.
3
P
3
.
4
P
3
.
5
P
3
.
6
P
3
.
7
Figure 9.14
SMART SENSORS
9.11
The pr imar y per for mance specificat ions of t he ADuC816 ar e given in Figur e 9.15.
All ADC specificat ions her e r efer t o t he pr imar y channel ADC. Except ionally low
power dissipat ion can be achieved in low bandwidt h applicat ions by keeping t he
ADuC816 in t he power down mode for much of t he t ime. By using an int er nal PLL,
t he chip der ives it s 12MHz clock fr om a 32kHz wat ch cr yst al. When in power down
mode, t he 12MHz clock is disabled, but t he 32kHz cr yst al cont inues t o dr ive a r eal-
t ime count er which can be set t o wake t he chip up at pr edefined int er vals. The
ADuC816 can also be configur ed t o wake up upon r eceiving an ext er nal int er r upt .
ADuC816 - PRIMARY SPECIFICATIONS
n ADC : INL - 30ppm
SNR (p-p) - >102dB (17 Noise Free Bits)
Input Range - 20mV to 2.56V
Conv. Rate - 5.4Hz to 105Hz
n DAC : DNL - LSB
Output Range - 0 to V
REF
-or- 0 to V
DD
Settling Time - <4s
n Power : Specified for 3V or 5V Operation
5V 3V
Normal 7mA 3mA
Idle 4.5mA 1.5mA
Powerdown <20A <20A
Figure 9.15
The ADuC812 offer s a fast (5s) 12-bit 8-channel successive appr oximat ion ADC
wit h many of t he same per ipher al feat ur es of t he ADuC816. The funct ional block
diagr am (Figur e 9.16) illust r at es it s pr imar y component s. Since t he 8-bit 1MIPS
micr ocont r oller cor e cannot gener ally keep up wit h t he 12-bit 200kSPS ADC out put
dat a, a DMA (dir ect memor y access) cont r oller is included on t he ADuC812 t o
aut omat ically wr it e ADC r esult s t o ext er nal memor y, t hus fr eeing t he
micr ocont r oller cor e for ot her t asks. Whet her in DMA mode or in nor mal mode, t he
ADuC812 conver sions can be t r igger ed by sever al means. Conver sions can be
t r igger ed in soft war e, or a t imer can be set t o aut omat ically init iat e a conver sion
each t ime it over flows, t her eby allowing pr ecise cont r ol of sampling r at e. A
har dwar e conver t -st ar t can also be ut ilized for applicat ions r equir ing cr it ical t iming.
SMART SENSORS
9.12
The ADuC812 cont ains t wo 12-bit DACs t hat can be power ed on or off
independent ly of each ot her , and can be updat ed eit her simult aneously or
independent ly. The DACs can be configur ed for an out put r ange of 0 t o VDD or 0 t o
VREF, wher e VREF can be eit her t he int er nal 2.5V bandgap r efer ence or an ext er nally
applied r efer ence volt age. The int er nal r efer ence, if used, can also be buffer ed t o
dr ive ext er nal cir cuit r y.
ADuC812 FUNCTIONAL BLOCK DIAGRAM
AIN
MUX
T/H 12-bit ADC
ADC
control
and
calibration
TEMP
sensor
2.5V
bandgap
reference
8K x 8
program
FLASH
EEPROM
640 x 8
user FLASH
synchronous
serial interface
(SPI or I2C)
8052
micro-
controller
core
256 x 8
user RAM
watchdog
timer
power supply
monitor
asynchronous
serial port
(UART)
16 bit
counter
timers
OSC
DAC
control
DAC1 buf
A
V
D
D
A
G
N
D
S
C
L
K
S
D
A
T
A
/
M
O
S
I
M
I
S
O
S
S
A
L
E
P
S
E
N
E
A
R
E
S
E
T
R
x
D
T
x
D
X
T
A
L
1
X
T
A
L
2
ADC0
ADC1
ADC3
ADC4
V
REF
DAC1
T0
T1
T2
T2EX
INT0
INT1
3.5mV/C
ADuC812
ADC2
ADC5
ADC6
ADC7
C
REF
DAC0 buf
DAC0
buf
CONVST
hardware
4
3
4
4
4
5
4
6
4
9
5
0
5
1
5
2
1 2 3 4
1
1
1
2
1
3
1
4
2
8
2
9
3
0
3
1
3
6
3
7
3
8
3
9
1
6
1
7
1
8
1
9
2
2
2
3
2
4
2
5
23
5
1
2
3
4
11
12
13
14
8
7
6
2
0
3
4
4
7
2
1
3
5
4
8
2
6
2
7
1
9
1
2
4
2
4
1
4
0
1
5
1
6
1
7
3
2
3
3
9
10
22
23
1
2
18
19
P
0
.
0
P
0
.
1
P
0
.
2
P
0
.
3
P
0
.
4
P
0
.
5
P
0
.
6
P
0
.
7
P
1
.
0
P
1
.
1
P
1
.
2
P
1
.
3
P
1
.
4
P
1
.
5
P
1
.
6
P
1
.
7
P
2
.
0
P
2
.
1
P
2
.
2
P
2
.
3
P
2
.
4
P
2
.
5
P
2
.
6
P
2
.
7
P
3
.
0
P
3
.
1
P
3
.
2
P
3
.
3
P
3
.
4
P
3
.
5
P
3
.
6
P
3
.
7
D
V
D
D
D
G
N
D
Figure 9.16
Figur e 9.17 list s some pr imar y per for mance specificat ions of t he ADuC812. The
power specificat ions ar e given assuming a 12MHz cr yst al. Since all on-chip logic is
st at ic, t he clock can be slowed t o any fr equency, allowing except ionally low power
dissipat ion in low bandwidt h applicat ions. For applicat ions r equir ing gr eat er speed,
t he clock can be incr eased t o as much as 16MHz t o achieve slight ly fast er
micr ocont r oller oper at ion (1.33MIPS).
Because Micr oConver t er
TM
pr oduct s ar e based on an indust r y st andar d 8052 cor e,
developer s can dr aw fr om a wealt h of soft war e, r efer ence mat er ial, and t hir d par t y
t ools t hat alr eady exist for 8051/8052 MCUs. The Micr oConver t er
TM
web sit e
pr ovides links t o many sour ces of such mat er ial, in addit ion t o offer ing downloads of
int er nally gener at ed t ools, dat a sheet s, and example soft war e.
SMART SENSORS
9.13
ADuC812 - PRIMARY SPECIFICATIONS
n ADC : INL - LSB
SNR (p-p) - >70dB
Input Range - 0 to V
REF
Conv. Time - <5s (200kSPS)
n DAC : DNL - LSB
Output Range - 0 to V
REF
-or- 0 to V
DD
Settling Time - <4s
n Power : Specified for 3V or 5V Operation
5V 3V
Normal 18mA 12mA
Idle 10mA 6mA
Powerdown <50A <50A
Figure 9.17
MicroConverter DESIGN SUPPORT
MicroConverter
TM
Web Site
QuickStart
TM
Development Kit
Third Party
Development Tools
1
2
3
Figure 9.18
SMART SENSORS
9.14
MicroConverter WEB SITE
www.analog.com
1
n Data Sheets
n Application Notes
n 8051 Reference Material
n Free Windows MicroConverter
TM
Simulator
n Free Keil C Compiler (2K limited version)
Figure 9.19
To get any designer or developer st ar t ed wit h a Micr oConver t er pr oduct , Analog
Devices offer s a QuickSt ar t
TM
Development Kit which cont ains all of t he necessar y
feat ur es for many designer s t o complet e a design wit hout t he added expense of
addit ional simulat ion or in-cir cuit emulat ion packages.
MicroConverter - QuickStart DEVELOPMENT KIT
n Documentation
u Users Guide
u Datasheet
u Tools Tutorial
u Quick Reference Guide
n Evaluation Board
u RS-232 Serial Comms
u 32K External SRAM
u Buffered Analog I/O
n Regulated Power Supply
n Serial Port Cable
n Software
u Metalink Assembler
u C Compiler (Limited 2K)
u Windows Simulator
u Serial Downloader
u Windows Debugger
u Example Code
QuickStart
TM
2
Figure 9.20
SMART SENSORS
9.15
For designs t hat r equir e t he added power of full in-cir cuit emulat ion, or t he added
ease of C coding wit h mixed-mode debugging, Keil and Met alink offer t he fir st of
many t hir d par t y t ools t o be endor sed by Analog Devices. These t ools ar e fully
compat ible wit h t he Micr oConver t er
TM
pr oduct s, and ot her t hir d par t y developer s
will soon offer addit ional Micr oConver t er
TM
-specific t ools t o fur t her expand t he
opt ions available t o designer s.
MicroConverter - THIRD PARTY DEVELOPMENT TOOLS
n Keil Compiler
u A full function windows based C compiler environment featuring
a simulator for source and assembly level debugging.
n MetaLink Emulator
u A high end in circuit emulation system offering a complete
windows based environment for in-system debug sessions.
Power Tools
3
All tools will fully integrate with each MicroConverter product
The First Two of Many Third
Party Tools to Fully Support
MicroConverter
TM
Products:
Figure 9.21
While t he ADuC812, ADuC816, and ADuC810 offer a mix of feat ur es and
per for mance not pr eviously available in a single chip, fut ur e Micr oConver t er
TM
pr oduct s will offer even gr eat er levels of int egr at ion and funct ionalit y. Lar ger
FLASH memor y ver sions will be offer ed t o compliment one or mor e of t he exist ing
pr oduct s. Addit ional har dwar e communicat ions may also be added t o fut ur e
Micr oConver t er
TM
pr oduct s t o allow dir ect communicat ion wit h indust r ial net wor ks
or PC plat for ms. Event ually, t her e will be Micr oConver t er
TM
pr oduct s wit h gr eat er
MCU pr ocessing bandwidt h. However , compar ing t hese devices t o basic
micr ocont r oller s is a mist ake. The per for mance level of Micr oConver t er
TM
analog I/O
is far super ior t o t hat available in micr ocont r oller s wit h analog I/O por t s.
SMART SENSORS
9.16
MicroConverter PRODUCT ROADMAP
n Larger FLASH Memory Capacity
(Data and Program)
n Hardware Communications
Interface Enhancements
(CAN Bus, USB Bus)
n Increased Microcontroller
Horsepower
TIME
1
ADuC812
-
8 Channel
12 bit ADC
-
Dual DAC
3
ADuC810
-
Low Cost
-
10 bit ADC,
Dual DAC
2
ADuC816
-
Dual 16 bit +
ADC
-
Single DAC
. . . . Future Products May Include:
. . . .
Figure 9.22
SMART SENSORS
9.17
REFERENCES
1. Compatibility of Analog S ignals for Electronic Industrial Process
Instruments, ANSI/ISA-S50.1-1982 (Rev. 1992), ht t p://www.isa.or g.
2. Dave Har r old, 4-20mA Transmitters Alive and Kicking, Con t r ol
En gi n eer i n g, Oct ober , 1998, p.109.
3. Paul Br okaw, Versatile Transmitter Chip Links S train Gages and
RTDs to Current Loop, Ap p li ca t i on Not e AN-275, Analog Devices, Inc.,
ht t p://www.analog.com.
4. Alber t O'Gr ady, Adding HART Capability to the AD421, Loop Powered
4-20mA DAC Using the 20C15 HART Modem, Ap p li ca t i on Not e 534,
Analog Devices, Inc., ht t p://www.analog.com.
5. Edit or s, Fieldbuses: Look Before You Leap, EDN, November 5, 1998,
p. 197.
6. MicroConverter Technology Backgrounder, Whit epaper , Analog Devices,
Inc., ht t p://www.analog.com.
7. I. Scot t MacKenzie, Th e 8051 Mi cr ocon t r oller , Secon d Ed i t i on ,
Pr ent ice-Hall, 1995.
10.1
SECTION 10
Walt Kester

RESISTOR AND THERMOCOUPLE ERRORS IN HIGH
ACCURACY SYSTEMS
Walt Kester, Walt Jung, and James Bryant

Resistor accuracy is crucial in precision systems. The circuit element called a
resistor should not be taken for granted! Figure 10.1 shows a simple non-inverting
op amp where the gain of 100 is set by the external resistors R1 and R2. The
temperature coefficients of the two resistors are a somewhat obvious source of error.
Assume that the op amp gain errors are negligible, and that the resistors are
perfectly matched at +25C. If the temperature coefficients of the resistors differ by
only 25ppm/C, the gain of the amplifier will change by 250ppm for a 10C
temperature change. This is about 1 LSB in a 12-bit system, and a major disaster in
a 16-bit system.

RESISTOR TEMPERATURE COEFFICIENT MISMATCHES
CAUSE GAIN VARIATION WITH TEMPERATURE
R1 = 9.9k , 1/4 W
TC = +25ppm/c
R2 = 100, , , , 1/4 W
TC = +50ppm/c
G = 1 +
R1
R2
= 100
Temperature change of 10C causes gain change of 250ppm
This is 1LSB in a 12-bit system and a disaster in a 16-bit system
+
_

Figure 10.1

Even if the temperature coefficients are identical, there still may be significant
errors. Suppose R1 and R2 have identical temperature coefficients of +25ppm/C
and are both W resistors. If the signal input in Figure 10.2 is zero, the resistors
will dissipate no heat, but if it is 100mV there will be 9.9V across R1 which will
dissipate 9.9mW and experience a temperature rise of 1.24C (the thermal
resistance of a W resistor is 125C/W). The 1.24C rise causes a resistance change
10.2
of 31ppm, and a corresponding change in gain. R2, with only 100mV across it, is
only heated 0.0125C, which is negligible. The 31ppm gain error represents a
fullscale error of LSB at 14-bits, and is a disaster for a 16-bit system.

RESISTOR SELF-HEATING EVEN IN MATCHED RESISTORS
CAN CAUSE GAIN VARIATION WITH INPUT LEVEL
R1 = 9.9k , 1/4 W
TC = +25ppm/c
R2 = 100, , , , 1/4 W
TC = +25ppm/c
+100mV
G = 1 +
R1
R2
= 100
+10V
R1, R2 Thermal Resistance = 125c / W
Temperature of R1 will rise by 1.24C, P
D
= 9.9mW
Temperature rise of R2 is negligible, P
D
= 0.1mW
Gain is altered by 31ppm, or 1/2 LSB @ 14-bits
+
_
Assume TC of R1 = TC of R2

Figure 10.2

These, and similar errors, are avoided by selecting critical resistors that are
accurately matched for both value and temperature coefficient, and ensuring tight
thermal coupling between resistors whose matching is important. This is best
achieved by using a resistor network on a single substrate - such a network may be
within an IC or may be a separately packaged thin-film resistor network.

Another more subtle problem with resistors is the thermocouple effect, sometimes
referred to as thermal EMF. Wherever there is a junction between two different
conductors there is a thermoelectric voltage. If two junctions are present in a circuit,
we have a thermocouple, and if these two junctions are at different temperatures,
there will be a net voltage in the circuit. This effect is used to measure temperature,
but is a potential source of inaccuracy in low level circuits, since wherever two
different conductors meet, we have a thermocouple, whether we like it or not. This
will cause errors if the various junctions are at different temperatures. The effect is
hard to avoid, even if we are only making connections with copper wire, since a
copper-to-copper junction formed by copper wire from two different manufacturers
may have a thermoelectric voltage of up to 0.2V/C.

Consider the resistor model shown in Figure 10.3. The connections between the
resistor material and the leads form two thermocouple junctions. The thermocouple
EMF can be as high as 400V/C for carbon composition resistors and as low as
10.3
0.05V/C for specially constructed resistors (Reference 1). Metal film resistors (RN-
types) are typically about 20V/C.

RESISTORS CONTAIN THERMOCOUPLES
RESISTOR
MATERIAL
RESISTOR LEADS
T1 T2
+
TYPICAL RESISTOR THERMOCOUPLE EMFs
CARBON COMPOSITION 400 V/ C
METAL FILM 20 V/ C
EVENOHM OR
MANGANIN WIREWOUND 2 V/ C
RCD Components HP-Series 0.05 V/ C
+ +

Figure 10.3

These thermocouple effects are unimportant at AC or where the resistor is at a
uniform temperature, but if the dissipation in a resistor, or its orientation with
respect to heat sources, can cause one of its ends to be warmer than the other, then
there will be a net thermocouple voltage differential, which will introduce a DC
error into the circuit. For instance, using ordinary metal film resistors, a
temperature differential of 1C will cause a thermocouple voltage of 20V which is
quite significant when compared to the input offset voltage of truly precision op
amps such as the OP177 or the AD707, and extremely significant when compared to
chopper-stabilized op amps.

Figure 10.4 shows how resistor orientation can make a difference in the net
thermocouple voltage. Standing the resistor on end in order to conserve board space
will invariable cause a temperature gradient across the resistor, especially if it is
dissipating any significant power. Placing the resistor flat on the PC board will
eliminate this problem unless there is airflow across the resistor parallel to its axis.
Orienting the resistor axis perpendicular to the airflow will minimize the error,
since this tends to force the resistor ends towards the same temperature.

Figure 10.5 shows how to orient the resistor on a vertically mounted PC board,
where the convection cooling air currents flow up the board. Again, the thermal axis
of the resistor should be perpendicular to the convection flow to minimize the effect.
10.4

Because of their small size, the thermocouple effect in surface mount resistors is
generally less than leaded types because of the tighter thermal coupling between
the ends of the resistor.

AVOIDING THERMAL GRADIENTS MINIMIZES
THERMOCOUPLE ERROR VOLTAGES
T
WRONG RIGHT

Figure 10.4

PROPER ORIENTATION OF SURFACE MOUNT RESISTORS
MINIMIZES THERMOCOUPLE ERROR VOLTAGE
WRONG RIGHT
T

Figure 10.5

10.5
A simple circuit shown in Figure 10.6 will further illustrate the parasitic
thermocouple problem. Here, we have a remote bridge driving an instrumentation
amplifier which has current limiting resistors in each lead. Each resistor has four
thermocouples: two are internal to the resistor, and two are formed where the
resistor leads connect to the copper wires. Another pair of thermocouples is formed
where the copper wire connects to the Kovar pins of the in-amp. The Copper/Kovar
junction has a thermocouple voltage of about 35V/C. Most molded plastic ICs use
copper leadframes which would be an order of magnitude or so less (e.g., the AD620
in-amp).

In addition, the copper wire has a resistance temperature coefficient (TC of 30 gage
copper wire is approximately 0.385%/C) which can introduce error if the
temperature of the wires is significantly different, or if they are different lengths. In
this example, however, this error is negligible because there is minimal current flow
in the wires.

Obviously, this simple circuit must have a good thermal as well as electrical design
in order to maintain microvolt precision. Some good design precautions include
minimizing number of thermocouple junctions, minimizing thermal gradients by
proper layout or blocking airflow to critical devices using metallic or plastic shields,
minimizing power dissipation in sensitive devices, proper selection of precision
resistors, and matching the number of junctions in each half of a differential signal
path by adding "dummy" components if required. Sockets, connectors, switches, or
relays in the critical signal path can introduce unstable contact resistances as well
as "unknown" thermocouple junctions which may not track to the required accuracy.
They should be avoided if possible.

PARASITIC THERMOCOUPLES IN SIMPLE CIRCUIT
KOVAR
PINS
+
THERMOCOUPLE DIFFERENTIAL EMF AT LEAD JUNCTIONS

35V/ C T
IN-AMP
REMOTE
BRIDGE
RESISTOR-TO-LEAD
CONNECTIONS
Cu
Cu
Cu
Cu

Figure 10.6

10.6
REFERENCES: RESISTOR AND THERMOELECTRIC
ERRORS

1. RCD Components, Inc., 520 E. Industrial Park Drive, Manchester NH,
03109, 603-669-0054, http://www.rcd-comp.com.

2. Steve Sockolov and James Wong, High-Accuracy Analog Needs More
Than Op Amps, Electronic Design, Oct.1, 1992, p.53.

3. Doug Grant and Scott Wurcer, Avoiding Passive Component Pitfalls,
The Best of analog Dialogue, Analog Devices, 1991, p. 143.

4. Brian Kerridge, Elegant Architectures Yield Precision Resistors,
EDN, July 20, 1992.

10.7

GROUNDING IN MIXED SIGNAL SYSTEMS
Walt Kester, James Bryant

Today's signal processing systems generally require mixed-signal devices such as
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) as well
as fast digital signal processors (DSPs). Requirements for processing analog signals
having wide dynamic ranges increases the importance of high performance ADCs
and DACs. Maintaining wide dynamic range with low noise in hostile digital
environments is dependent upon using good high-speed circuit design techniques
including proper signal routing, decoupling, and grounding.

In the past, "high precision, low-speed" circuits have generally been viewed
differently than so-called "high-speed" circuits. With respect to ADCs and DACs, the
sampling (or update) frequency has generally been used as the distinguishing speed
criteria. However, the following two examples show that in practice, most of today's
signal processing ICs are really "high-speed," and must therefore be treated as such
in order to maintain high performance. This is certainly true of DSPs, and also true
of ADCs and DACs.

All sampling ADCs (ADCs with an internal sample-and-hold circuit) suitable for
signal processing applications operate with relatively high speed clocks with fast
rise and fall times (generally a few nanoseconds) and must be treated as high speed
devices, even though throughput rates may appear low. For example, the 12-bit
AD7892 successive approximation (SAR) ADC operates on an 8MHz internal clock,
while the sampling rate is only 600kSPS.

Sigma-delta (-) ADCs also require high speed clocks because of their high
oversampling ratios. The AD7722 16-bit ADC has an output data rate (effective
sampling rate) of 195kSPS, but actually samples the input signal at 12.5MSPS (64-
times oversampling). Even high resolution, so-called "low frequency" - industrial
measurement ADCs (having throughputs of 10Hz to 7.5kHz) operate on 5MHz or
higher clocks and offer resolution to 24-bits (for example, the Analog Devices
AD7730 and AD7731).

To further complicate the issue, mixed-signal ICs have both analog and digital
ports, and because of this, much confusion has resulted with respect to proper
grounding techniques. Digital and analog design engineers tend to view these
devices from different perspectives, and the purpose of this section is to develop a
general grounding philosophy that will work for most mixed signal devices, without
having to know the specific details of their internal circuits.

Ground and Power Planes

The importance of maintaining a low impedance large area ground plane is critical
to all analog circuits today. The ground plane not only acts as a low impedance
return path for decoupling high frequency currents (caused by fast digital logic) but
10.8
also minimizes EMI/RFI emissions. Because of the shielding action of the ground
plane, the circuits susceptibility to external EMI/RFI is also reduced.

Ground planes also allow the transmission of high speed digital or analog signals
using transmission line techniques (microstrip or stripline) where controlled
impedances are required.

The use of "buss wire" is totally unacceptable as a "ground" because of its
impedance at the equivalent frequency of most logic transitions. For instance, #22
gauge wire has about 20nH/inch inductance. A transient current having a slew rate
of 10mA/ns created by a logic signal would develop an unwanted voltage drop of
200mV at this frequency flowing through 1 inch of this wire:

v L
i
t
nH
mA
ns
mV 20
10
200 .

For a signal having a 2V peak-to-peak range, this translates into an error of about
200mV, or 10% (approximate 3.5-bit accuracy). Even in all-digital circuits, this error
would result in considerable degradation of logic noise margins.

Figure 10.7 shows an illustration of a situation where the digital return current
modulates the analog return current (top figure). The ground return wire
inductance and resistance is shared between the analog and digital circuits, and
this is what causes the interaction and resulting error. A possible solution is to
make the digital return current path flow directly to the GND REF as shown in the
bottom figure. This is the fundamental concept of a "star," or single-point ground
system. Implementing the true single-point ground in a system which contains
multiple high frequency return paths is difficult because the physical length of the
individual return current wires will introduce parasitic resistance and inductance
which can make obtaining a low impedance high frequency ground difficult. In
practice, the current returns must consist of large area ground planes for low
impedance to high frequency currents. Without a low-impedance ground plane, it is
therefore almost impossible to avoid these shared impedances, especially at high
frequencies.

All integrated circuit ground pins should be soldered directly to the low-impedance
ground plane to minimize series inductance and resistance. The use of traditional
IC sockets is not recommended with high-speed devices. The extra inductance and
capacitance of even "low profile" sockets may corrupt the device performance by
introducing unwanted shared paths. If sockets must be used with DIP packages, as
in prototyping, individual "pin sockets" or "cage jacks" may be acceptable. Both
capped and uncapped versions of these pin sockets are available (AMP part
numbers 5-330808-3, and 5-330808-6). They have spring-loaded gold contacts which
make good electrical and mechanical connection to the IC pins. Multiple insertions,
however, may degrade their performance.

10.9
DIGITAL CURRENTS FLOWING IN ANALOG
RETURN PATH CREATE ERROR VOLTAGES
ANALOG
CIRCUITS
DIGITAL
CIRCUITS
ANALOG
CIRCUITS
DIGITAL
CIRCUITS
V
D
V
D
V
A
V
A
+ +
+ +
I
D
I
A
I
D
I
A
+ I
D
V
IN
V
IN
I
D
I
A
I
D
I
A
GND
REF
GND
REF
INCORRECT
CORRECT

Figure 10.7

Power supply pins should be decoupled directly to the ground plane using low
inductance ceramic surface mount capacitors. If through-hole mounted ceramic
capacitors must be used, their leads should be less than 1mm. The ceramic
capacitors should be located as close as possible to the IC power pins. Ferrite beads
may be also required for additional decoupling.

Double-Sided vs. Multilayer Printed Circuit Boards

Each PCB in the system should have at least one complete layer dedicated to the
ground plane. Ideally, a double-sided board should have one side completely
dedicated to ground and the other side for interconnections. In practice, this is not
possible, since some of the ground plane will certainly have to be removed to allow
for signal and power crossovers, vias, and through-holes. Nevertheless, as much
area as possible should be preserved, and at least 75% should remain. After
completing an initial layout, the ground layer should be checked carefully to make
sure there are no isolated ground "islands," because IC ground pins located in a
ground "island" have no current return path to the ground plane. Also, the ground
plane should be checked for "skinny" connections between adjacent large areas
which may significantly reduce the effectiveness of the ground plane. Needless to
say, auto-routing board layout techniques will generally lead to a layout disaster on
a mixed-signal board, so manual intervention is highly recommended.

10.10

Systems that are densely packed with surface mount ICs will have a large number
of interconnections; therefore multilayer boards are preferred. This allows a
complete layer to be dedicated to ground. A simple 4-layer board would have
internal ground and power plane layers with the outer two layers used for
interconnections between the surface mount components. Placing the power and
ground planes adjacent to each other provides additional inter-plane capacitance
which helps high frequency decoupling of the power supply.

GROUND PLANES ARE MANDATORY!
I Use Large Area Ground (and Power) Planes for Low Impedance
Current Return Paths (Must Use at Least a Double-Sided Board!)
I Double-Sided Boards:
N Avoid High-Density Interconnection Crossovers and
Feedthroughs Which Reduce Ground Plane Area
N Keep > 75% Board Area on One Side for Ground Plane
I Multilayer Boards
N Dedicate at Least One Layer for the Ground Plane
N Dedicate at Least One Layer for the Power Plane
I Use at Least 30% to 40% of PCB Connector Pins for Ground
I Continue the Ground Plane on the Backplane Motherboard to
Power Supply Return

Figure 10.8

Multicard Mixed-Signal Systems

The best way of minimizing ground impedance in a multicard system is to use a
"motherboard" PCB as a backplane for interconnections between cards, thus
providing a continuous ground plane to the backplane. The PCB connector should
have at least 30-40% of its pins devoted to ground, and these pins should be
connected to the ground plane on the backplane mother card. To complete the
overall system grounding scheme there are two possibilities:

1. The backplane ground plane can be connected to chassis ground at numerous
points, thereby diffusing the various ground current return paths. This is commonly
referred to as a "multipoint" grounding system and is shown in Figure 10.9.

2. The ground plane can be connected to a single system "star ground" point
(generally at the power supply).
10.11

MULTIPOINT GROUND CONCEPT
POWER
SUPPLIES
GROUND PLANE
V
A
V
D
V
A
V
D
GROUND PLANE
BACKPLANE
PCB
GROUND PLANE
V
A
V
D
PCB
CHASSIS
GROUND

Figure 10.9

The first approach is most often used in all-digital systems, but can be used in
mixed-signal systems provided the ground currents due to digital circuits are
sufficiently diffused over a large area. The low ground impedance is maintained all
the way through the PC boards, the backplane, and ultimately the chassis.
However, it is critical that good electrical contact be made where the grounds are
connected to the sheet metal chassis. This requires self-tapping sheet metal screws
or "biting" washers. Special care must be taken where anodized aluminum is used
for the chassis material, since its surface acts as an insulator.

The second approach ("star ground") is often used in high speed mixed-signal
systems having separate analog and digital ground systems and warrants
considerable further discussion.

Separating Analog and Digital Grounds

In mixed-signal systems with large amounts of digital circuitry, it is highly
desirable to physically separate sensitive analog components from noisy digital
components. It may also be beneficial to use separate ground planes for the analog
and the digital circuitry. These planes should not overlap in order to minimize
capacitive coupling between the two. The separate analog and digital ground planes
are continued on the backplane using either motherboard ground planes or "ground
10.12
screens" which are made up of a series of wired interconnections between the
connector ground pins. The arrangement shown in Figure 10.10 illustrates that the
two planes are kept separate all the way back to a common system "star" ground,
generally located at the power supplies. The connections between the ground planes,
the power supplies, and the "star" should be made up of multiple bus bars or wide
copper brads for minimum resistance and inductance. The back-to-back Schottky
diodes on each PCB are inserted to prevent accidental DC voltage from developing
between the two ground systems when cards are plugged and unplugged. Schottky
diodes are used because of their low capacitance to prevent coupling between the
analog and digital ground planes. However, Schottky diodes begin to conduct at
about 300mV, so if the total differential peak-to-peak voltage (the sum of the AC
and DC components) between the two ground planes exceeds this value, additional
diodes in series should be used.

SEPARATING ANALOG AND DIGITAL GROUND PLANES
POWER
SUPPLIES
ANALOG
GROUND
PLANE
DIGITAL
GROUND
PLANE
A D
ANALOG
GROUND
PLANE
DIGITAL
GROUND
PLANE
A D
V
A
V
D
V
A
V
A
V
D
V
D
ANALOG GROUND PLANE
DIGITAL GROUND PLANE
BACKPLANE
PCB PCB
SYSTEM
STAR
GROUND

Figure 10.10

Grounding and Decoupling Mixed-Signal ICs

Sensitive analog components such as amplifiers and voltage references are always
referenced and decoupled to the analog ground plane. The ADCs and DACs (and
other mixed-signal ICs) should generally be treated as analog components and also
grounded and decoupled to the analog ground plane. At first glance, this may seem
somewhat contradictory, since a converter has an analog and digital interface and
usually pins designated as analog ground (AGND) and digital ground (DGND). The
diagram shown in Figure 10.11 will help to explain this seeming dilemma.
10.13
PROPER GROUNDING OF MIXED-SIGNAL ICs
ANALOG
CIRCUITS
DIGITAL
CIRCUITS
BUFFER
GATE OR
REGISTER
V
A
A B
V
D
C
STRAY
C
STRAY
R
A A
A A
D
D
V
NOISE
V
A
AIN/
OUT
AGND DGND
DATA
BUS
FERRITE BEAD
DATA
V
D
A = ANALOG GROUND PLANE D = DIGITAL GROUND PLANE
C
IN
10pF
L
P
L
P
L
P
L
P
R
P
R
P
R
P
R
P
SHORT
CONNECTIONS
I
A
I
D

Figure 10.11

Inside an IC that has both analog and digital circuits, such as an ADC or a DAC,
the grounds are usually kept separate to avoid coupling digital signals into the
analog circuits. Figure 10.11 shows a simple model of a converter. There is nothing
the IC designer can do about the wirebond inductance and resistance associated
with connecting the bond pads on the chip to the package pins except to realize it's
there. The rapidly changing digital currents produce a voltage at point B which will
inevitably couple into point A of the analog circuits through the stray capacitance,
C
STRAY
. In addition, there is approximately 0.2pF unavoidable stray capacitance
between every pin of the IC package! It's the IC designer's job to make the chip
work in spite of this. However, in order to prevent further coupling, the AGND and
DGND pins should be joined together externally to the analog ground plane with
minimum lead lengths. Any extra impedance in the DGND connection will cause
more digital noise to be developed at point B; it will, in turn, couple more digital
noise into the analog circuit through the stray capacitance. Note that connecting
DGND to the digital ground plane applies V
NOISE
across the AGND and DGND
pins and invites disaster!

The name "DGND" on an IC tells us that this pin connects to the digital ground of
the IC. This does not imply that this pin must be connected to the digital ground of
the system.

It is true that this arrangement will inject a small amount of digital noise onto the
analog ground plane. These currents should be quite small, and can be minimized
by ensuring that the converter output does not drive a large fanout (they normally
10.14
can't, by design). Minimizing the fanout on the converter's digital port will also keep
the converter logic transitions relatively free from ringing and minimize digital
switching currents, and thereby reducing any potential coupling into the analog port
of the converter. The logic supply pin (V
D
) can be further isolated from the analog
supply by the insertion of a small lossy ferrite bead as shown in Figure 10.11. The
internal digital currents of the converter will return to ground through the V
D
pin
decoupling capacitor (mounted as close to the converter as possible) and will not
appear in the external ground circuit. These decoupling capacitors should be low
inductance ceramic types, typically between 0.01F and 0.1F.

Treat the ADC Digital Outputs with Care

It is always a good idea (as shown in Figure 10.11) to place a buffer register
adjacent to the converter to isolate the converter's digital lines from noise on the
data bus. The register also serves to minimize loading on the digital outputs of the
converter and acts as a Faraday shield between the digital outputs and the data
bus. Even though many converters have three-state outputs/inputs, this isolation
register still represents good design practice.

The series resistors (labeled "R" in Figure 10.11) between the ADC output and the
buffer register input help to minimize the digital transient currents which may
affect converter performance. The resistors isolate the digital output drivers from
the capacitance of the buffer register inputs. In addition, the RC network formed by
the series resistor and the buffer register input capacitance acts as a lowpass filter
to slow down the fast edges.

A typical CMOS gate combined with PCB trace and through-hole will create a load
of approximately 10pF. A logic output slew rate of 1V/ns will produce 10mA of
dynamic current if there is no isolation resistor:

I C
v
t
pF
V
ns
mA 10
1
10 .

A 500 series resistors will minimize this output current and result in a rise and
fall time of approximately 11ns when driving the 10pF input capacitance of the
register:

t
r
R C pF ns 22 22 22 500 10 11 . . . .

TTL registers should be avoided, since they can appreciably add to the dynamic
switching currents because of their higher input capacitance.

The buffer register and other digital circuits should be grounded and decoupled to
the digital ground plane of the PC board. Notice that any noise between the analog
and digital ground plane reduces the noise margin at the converter digital interface.
Since digital noise immunity is of the orders of hundreds or thousands of millivolts,
this is unlikely to matter. The analog ground plane will generally not be very noisy,
but if the noise on the digital ground plane (relative to the analog ground plane)
exceeds a few hundred millivolts, then steps should be taken to reduce the digital
10.15
ground plane impedance, thereby maintaining the digital noise margins at an
acceptable level.

Separate power supplies for analog and digital circuits are also highly desirable.
The analog supply should be used to power the converter. If the converter has a pin
designated as a digital supply pin (V
D
), it should either be powered from a separate
analog supply, or filtered as shown in the diagram. All converter power pins should
be decoupled to the analog ground plane, and all logic circuit power pins should be
decoupled to the digital ground plane as shown in Figure 10.12. If the digital power
supply is relatively quiet, it may be possible to use it to supply analog circuits as
well, but be very cautious.

In some cases it may not be possible to connect V
D
to the analog supply. Some of the
newer, high speed ICs may have their analog circuits powered by +5V, but the
digital interface powered by +3V to interface to 3V logic. In this case, the +3V pin of
the IC should be decoupled directly to the analog ground plane. It is also advisable
to connect a ferrite bead in series with power trace that connects the pin to the +3V
digital logic supply.

GROUNDING AND DECOUPLING POINTS
AMP

V
D
V
A
V
A
A
A A
AGND DGND
ADC
OR
DAC
V
A

A
VOLTAGE
REFERENCE
V
A

A
SAMPLING
CLOCK
GENERATOR
A A
V
A
A

BUFFER
GATE
OR
REGISTER
V
D
D
D
A A
R
R
A
ANALOG
GROUND PLANE
D
DIGITAL
GROUND PLANE
TO OTHER
DIGITAL
CIRCUITS
FERRITE
BEAD

Figure 10.12

The sampling clock generation circuitry should be treated like analog circuitry and
also be grounded and heavily-decoupled to the analog ground plane. Phase noise on
the sampling clock produces degradation in system SNR as will be discussed
shortly.

10.16
The Origins of the Confusion about Mixed-Signal Grounding:
Applying Single-Card Grounding Concepts to Multicard Systems

Most ADC, DAC, and other mixed-signal device data sheets discuss grounding
relative to a single PCB, usually the manufacturer's own evaluation board. This has
been a source of confusion when trying to apply these principles to multicard or
multi-ADC/DAC systems. The recommendation is usually to split the PCB ground
plane into an analog one and a digital one. It is then further recommended that the
AGND and DGND pins of a converter be tied together and that the analog ground
plane and digital ground planes be connected at that same point. This essentially
creates the system "star" ground at the mixed-signal device. While this approach
will generally work in a simple system with a single PCB and single ADC/DAC, it is
not optimum for multicard mixed-signal systems. In systems having several ADCs
or DACs on different PCBs (or on the same PCB, for that matter), the analog and
digital ground planes become connected at several points, creating the possibility of
ground loops and making a single-point "star" ground system impossible. These
ground loops can also occur if there is more than one mixed-signal device on a single
PCB. For these reasons, this grounding approach is not recommended for multicard
systems, and the approach previously discussed should be used.

Sampling Clock Considerations

In a high performance sampled data system a low phase-noise crystal oscillator
should be used to generate the ADC (or DAC) sampling clock because sampling
clock jitter modulates the analog input/output signal and raises the noise and
distortion floor. The sampling clock generator should be isolated from noisy digital
circuits and grounded and decoupled to the analog ground plane, as is true for the
op amp and the ADC.

The effect of sampling clock jitter on ADC Signal-to-Noise Ratio (SNR) is given
approximately by the equation:

SNR
ft
j
]
]
]
]
20
10
1
2
log ,

where SNR is the SNR of a perfect ADC of infinite resolution where the only source
of noise is that caused by the RMS sampling clock jitter, t
j
. Note that f in the above
equation is the analog input frequency. Just working through a simple example, if t
j

= 50ps RMS, f = 100kHz, then SNR = 90dB, equivalent to about 15-bits dynamic
range.

It should be noted that t
j
in the above example is the root-sum-square (RSS) value
of the external clock jitter and the internal ADC clock jitter (called aperture jitter).
However, in most high performance ADCs, the internal aperture jitter is negligible
compared to the jitter on the sampling clock.

Since degradation in SNR is primarily due to external clock jitter, steps must be
taken to ensure the sampling clock is as noise-free as possible and has the lowest
possible phase jitter. This requires that a crystal oscillator be used. There are
several manufacturers of small crystal oscillators with low jitter (less than 5ps
10.17
RMS) CMOS compatible outputs. (For example, MF Electronics, 10 Commerce Dr.,
New Rochelle, NY 10801, Tel. 914-576-6570.)

Ideally, the sampling clock crystal oscillator should be referenced to the analog
ground plane in a split-ground system. However, this is not always possible because
of system constraints. In many cases, the sampling clock must be derived from a
higher frequency multi-purpose system clock which is generated on the digital
ground plane. It must then pass from its origin on the digital ground plane to the
ADC on the analog ground plane. Ground noise between the two planes adds
directly to the clock signal and will produce excess jitter. The jitter can cause
degradation in the signal-to-noise ratio and also produce unwanted harmonics. This
can be remedied somewhat by transmitting the sampling clock signal as a
differential signal using either a small RF transformer as shown in Figure 10.13 or
a high speed differential driver and receiver IC. If an active differential driver and
receiver are used, they should be ECL to minimize phase jitter. In a single +5V
supply system, ECL logic can be connected between ground and +5V (PECL), and
the outputs AC coupled into the ADC sampling clock input. In either case, the
original master system clock must be generated from a low phase noise crystal
oscillator.

SAMPLING CLOCK DISTRIBUTION FROM
DIGITAL TO ANALOG GROUND PLANES
LOW PHASE
NOISE
MASTER CLOCK
SYSTEM CLOCK
GENERATORS
DSP OR MICROPROCESSOR
D A
D A
V
D
V
A
V
D
V
D
V
D
D
D D
+
_
SAMPLING
CLOCK
SAMPLING
CLOCK
METHOD 1
METHOD 2
DIGITAL GROUND PLANE ANALOG GROUND PLANE
1
2 f t
j
SNR = 20 log
10
t
j
= Sampling Clock Jitter
f = Analog Input Frequency

Figure 10.13

10.18
Some PC Board Layout Guidelines for Mixed-Signal Systems

It is evident that noise can be minimized by paying attention to the system layout
and preventing different signals from interfering with each other. High level analog
signals should be separated from low level analog signals, and both should be kept
away from digital signals. We have seen elsewhere that in waveform sampling and
reconstruction systems the sampling clock (which is a digital signal) is as
vulnerable to noise as any analog signal, but is as liable to cause noise as any digital
signal, and so must be kept isolated from both analog and digital systems.

The ground plane can act as a shield where sensitive signals cross. Figure 10.14
shows a good layout for a data acquisition board where all sensitive areas are
isolated from each other and signal paths are kept as short as possible. While real
life is rarely as tidy as this, the principle remains a valid one.

ANALOG AND DIGITAL CIRCUITS
SHOULD BE PARTITIONED ON PCB LAYOUT
REFERENCE ADC
FILTER
AMPLIFIER
SAMPLING
CLOCK GENERATOR
TIMING
CIRCUITS
BUFFER
REGISTER
DSP
OR
P
CONTROL
LOGIC
DEMULTIPLEXER
BUFFER
MEMORY
POWER
ANALOG
INPUT
MULTIPLE
GROUNDS
DATA
BUS
ADDRESS
BUS
MULTIPLE
GROUNDS
ANALOG
DIGITAL

Figure 10.14

There are a number of important points to be considered when making signal and
power connections. First of all a connector is one of the few places in the system
where all signal conductors must run in parallel - it is therefore imperative to
separate them with ground pins (creating a faraday shield) to reduce coupling
between them.

Multiple ground pins are important for another reason: they keep down the ground
impedance at the junction between the board and the backplane. The contact
resistance of a single pin of a PCB connector is quite low (of the order of 10m)
when the board is new - as the board gets older the contact resistance is likely to
10.19
rise, and the board's performance may be compromised. It is therefore well
worthwhile to allocate extra PCB connector pins so that there are many ground
connections (perhaps 30-40% of all the pins on the PCB connector should be ground
pins). For similar reasons there should be several pins for each power connection,
although there is no need to have as many as there are ground pins.

Manufacturers of high performance mixed-signal ICs like Analog Devices offer
evaluation boards to assist customers in their initial evaluations and layout. ADC
evaluation boards generally contain an on-board low-jitter sampling clock oscillator,
output registers, and appropriate power and signal connectors. They also may have
additional support circuitry such as the ADC input buffer amplifier and external
reference.

The layout of the evaluation board is optimized in terms of grounding, decoupling,
and signal routing and can be used as a model when laying out the ADC PC board
in the system. The actual layout is usually available from the ADC manufacturer in
the form of computer CAD files (Gerber files).
10.20

REFERENCES ON GROUNDING:

1. William C. Rempfer, Get All the Fast ADC Bits You Pay For,
Electronic Design, Special Analog Issue, June 24, 1996, p.44.

2. Mark Sauerwald, Keeping Analog Signals Pure in a Hostile Digital
World, Electronic Design, Special Analog Issue, June 24, 1996, p.57.

3. Jerald Grame and Bonnie Baker, Design Equations Help Optimize
Supply Bypassing for Op Amps, Electronic Design, Special Analog
Issue, June 24, 1996, p.9.

4. Jerald Grame and Bonnie Baker, Fast Op Amps Demand More Than
a Single-Capacitor Bypass, Electronic Design, Special Analog Issue,
November 18, 1996, p.9.

5. Walt Kester and James Bryant, Grounding in High Speed Systems,
High Speed Design Techniques, Analog Devices, 1996, Chapter 7, p. 7-27.

6. Jeffrey S. Pattavina, Bypassing PC Boards: Thumb Your Nose at Rules
of Thumb, EDN, Oct. 22, 1998, p.149.

7. Henry Ott, Noise Reduction Techniques in Electronic Systems,
Second Edition, New York, John Wiley and Sons, 1988.

8. Howard W. Johnson and Martin Graham, High-Speed Digital Design,
PTR Prentice Hall, 1993.

9. Paul Brokaw, An I.C. Amplifier User's Guide to Decoupling, Grounding
and Making Things Go Right for a Change, Application Note,
Analog Devices, Inc., http://www.analog.com.

10. Walt Kester, A Grounding Philosophy for Mixed-Signal Systems,
Electronic Design Analog Applications Issue, June 23, 1997, p. 29.

11. Ralph Morrison, Grounding and Shielding Techniques, Fourth Edition,
John Wiley, 1998.

12. Ralph Morrison, Solving Interference Problems in Electronics,
John Wiley, 1995.

13. C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System
Design, John Wiley, 1993.

14. Crystal Oscillators: MF Electronics, 10 Commerce Drive, New Rochelle,
NY, 10801, 914-576-6570.
10.21

POWER SUPPLY NOISE REDUCTION AND
FILTERING
Walt Jung, Walt Kester, Bill Chestnut

Precision analog circuitry has traditionally been powered from well regulated, low
noise linear power supplies. During the last decade however, switching power
supplies have become much more common in electronic systems. As a consequence,
they also are being used for analog supplies. Good reasons for the general popularity
include their high efficiency, low temperature rise, small size, and light weight.

In spite of these benefits, switchers do have drawbacks, most notably high output
noise. This noise generally extends over a broad band of frequencies, resulting in
both conducted and radiated noise, as well as unwanted electric and magnetic
fields. Voltage output noise of switching supplies are short-duration voltage
transients, or spikes. Although the fundamental switching frequency can range
from 20kHz to 1MHz, the spikes can contain frequency components extending to
100MHz or more. While specifying switching supplies in terms of RMS noise is
common vendor practice, as a user you should also specify the peak (or p-p)
amplitudes of the switching spikes, at the output loading of your system.

The following section discusses filter techniques for rendering a switching regulator
output analog ready, that is sufficiently quiet to power precision analog circuitry
with relatively small loss of DC terminal voltage. The filter solutions presented are
generally applicable to all power supply types incorporating switching element(s) in
their energy path. This includes various DC-DC converters as well as popular 5V
(PC type) supplies.

An understanding of the EMI process is necessary to understand the effects of
supply noise on analog circuits and systems. Every interference problem has a
source, a path, and a receptor [Reference 1]. In general, there are three methods for
dealing with interference. First, source emissions can be minimized by proper
layout, pulse-edge rise time control/reduction, filtering, and proper grounding.
Second, radiation and conduction paths should be reduced through shielding and
physical separation. Third, receptor immunity to interference can be improved, via
supply and signal line filtering, impedance level control, impedance balancing, and
utilizing differential techniques to reject undesired common-mode signals. This
section focuses on reducing switching power supply noise with external post filters.

Tools useful for combating high frequency switcher noise are shown by Figure 10.15.
They differ in electrical characteristics as well as practicality towards noise
reduction, and are listed roughly in an order of priorities. Of these tools, L and C
are the most powerful filter elements, and are the most cost-effective, as well as
small in size.

10.22

SWITCHING REGULATOR NOISE REDUCTION TOOLS
I Capacitors
I Inductors
I Ferrites
I Resistors
I Linear Post Regulation
I Proper Layout and Grounding Techniques
I PHYSICAL SEPARATION FROM SENSITIVE
ANALOG CIRCUITS!!

Figure 10.15

Capacitors are probably the single most important filter component for switchers.
There are many different types of capacitors, and an understanding of their
individual characteristics is absolutely mandatory to the design of effective practical
supply filters. There are generally three classes of capacitors useful in 10kHz-
100MHz filters, broadly distinguished as the generic dielectric types; electrolytic,
organic, film, and ceramic. These can in turn can be further sub-divided. A
thumbnail sketch of capacitor characteristics is shown in the chart of Figure 10.16.

TYPES OF CAPACITORS
Aluminum
Electrolytic
(General
Purpose)
Aluminum
Electrolytic
(Switching
Type)
Tantalum
Electrolytic
OS-CON
Electrolytic
Polyester
(Stacked
Film)
Ceramic
(Multilayer)
Size 100 F 120 F 120 F 100 F 1 F 0.1 F
Rated
Voltage
25 V 25 V 20 V 20 V 400 V 50 V
ESR
0.6

@
100 kHz
0.18

@
100 kHz
0.12

@
100 kHz
0.02

@
100 kHz
0.11

@
1 MHz
0.12

@
1 MHz
Operating
Frequency
(*)

100 kHz

500 kHz

1 MHz

1 MHz

10 MHz

1 GHz
(*) Upper frequency strongly size and package dependent

Figure 10.16

10.23
With any dielectric, a major potential filter loss element is ESR (equivalent series
resistance), the net parasitic resistance of the capacitor. ESR provides an ultimate
limit to filter performance, and requires more than casual consideration, because it
can vary both with frequency and temperature in some types. Another capacitor loss
element is ESL (equivalent series inductance). ESL determines the frequency where
the net impedance characteristic switches from capacitive to inductive. This varies
from as low as 10kHz in some electrolytics to as high as 100MHz or more in chip
ceramic types. Both ESR and ESL are minimized when a leadless package is used.
All capacitor types mentioned are available in surface mount packages, preferable
for high speed uses.

The electrolytic family provides an excellent, cost-effective low-frequency filter
component, because of the wide range of values, a high capacitance-to-volume ratio,
and a broad range of working voltages. It includes general purpose aluminum
electrolytic types, available in working voltages from below 10V up to about 500V,
and in size from 1 to several thousand F (with proportional case sizes). All
electrolytic capacitors are polarized, and thus cannot withstand more than a volt or
so of reverse bias without damage. They also have relatively high leakage currents
(up to tens of A, and strongly dependent upon design specifics).

A subset of the general electrolytic family includes tantalum types, generally
limited to voltages of 100V or less, with capacitance of up to 500F [Reference 3]. In
a given size, tantalums exhibit a higher capacitance-to-volume ratios than do
general purpose electrolytics, and have both a higher frequency range and lower
ESR. They are generally more expensive than standard electrolytics, and must be
carefully applied with respect to surge and ripple currents.

A subset of aluminum electrolytic capacitors is the switching type, designed for
handling high pulse currents at frequencies up to several hundred kHz with low
losses [Reference 4]. This capacitor type competes directly with tantalums in high
frequency filtering applications, with the advantage of a broader range of values.

A more specialized high performance aluminum electrolytic capacitor type uses an
organic semiconductor electrolyte [Reference 5]. The OS-CON capacitors feature
appreciably lower ESR and higher frequency range than do other electrolytic types,
with an additional feature of low low-temperature ESR degradation.

Film capacitors are available in a very broad range of values and an array of
dielectrics, including polyester, polycarbonate, polypropylene, and polystyrene.
Because of the low dielectric constant of these films, their volumetric efficiency is
quite low, and a 10F/50V polyester capacitor (for example) is actually the size of
your hand. Metalized (as opposed to foil) electrodes do help to reduce size, but even
the highest dielectric constant units among film types (polyester, polycarbonate) are
still larger than any electrolytic, even using the thinnest films with the lowest
voltage ratings (50V). Where film types excel is in their low dielectric losses, a factor
which may not necessarily be a practical advantage for filtering switchers. For
example, ESR in film capacitors can be as low as 10m or less, and the behavior of
films generally is very high in terms of Q. In fact, this can cause problems of
spurious resonance in filters, requiring damping components.

10.24
Film capacitors using a wound layer-type construction can be inductive. This can
limit their effectiveness for high frequency filtering. Obviously, only non-inductively
made film caps are useful for switching regulator filters. One specific style which is
non-inductive is the stacked-film type, where the capacitor plates are cut as small
overlapping linear sheet sections from a much larger wound drum of dielectric/plate
material. This technique offers the low inductance attractiveness of a plate sheet
style capacitor with conventional leads [see References 4, 5, 6]. Obviously, minimal
lead length should be used for best high frequency effectiveness. Very high current
polycarbonate film types are also available, specifically designed for switching
power supplies, with a variety of low inductance terminations to minimize ESL
[Reference 7].

Dependent upon their electrical and physical size, film capacitors can be useful at
frequencies to well above 10MHz. At the highest frequencies, only stacked film
types should be considered. Some manufacturers are now supplying film types in
leadless surface mount packages, which eliminates the lead length inductance.

Ceramic is often the capacitor material of choice above a few MHz, due to its
compact size, low loss, and availability up to several F in the high-K dielectric
formulations (X7R and Z5U), at voltage ratings up to 200V [see ceramic families of
Reference 3]. NP0 (also called COG) types use a lower dielectric constant
formulation, and have nominally zero TC, plus a low voltage coefficient (unlike the
less stable high-K types). NP0 types are limited to values of 0.1F or less, with
0.01F representing a more practical upper limit.

Multilayer ceramic chip caps are very popular for bypassing/ filtering at 10MHz or
higher, simply because their very low inductance design allows near optimum RF
bypassing. For smaller values, ceramic chip caps have an operating frequency range
to 1GHz. For high frequency applications, a useful selection can be ensured by
selecting a value which has a self-resonant frequency above the highest frequency of
interest.

All capacitors have some finite ESR. In some cases, the ESR may actually be helpful
in reducing resonance peaks in filters, by supplying free damping. For example, in
most electrolytic types, a nominally flat broad series resonance region can be noted
by the impedance vs. frequency plot. This occurs where |Z| falls to a minimum
level, nominally equal to the capacitors ESR at that frequency. This low Q
resonance can generally cover a relatively wide frequency range of several octaves.
Contrasted to the very high Q sharp resonances of film and ceramic caps, the low Q
behavior of electrolytics can be useful in controlling resonant peaks.

In most electrolytic capacitors, ESR degrades noticeably at low temperature, by as
much as a factor of 4-6 times at 55C vs. the room temperature value. For circuits
where ESR is critical to performance, this can lead to problems. Some specific
electrolytic types do address this problem, for example within the HFQ switching
types, the 10C ESR at 100kHz is no more than 2 that at room temperature. The
OSCON electrolytics have a ESR vs. temperature characteristic which is relatively
flat.

10.25
As noted, all real capacitors have parasitic elements which limit their performance.
The equivalent electrical network representing a real capacitor models both ESR
and ESL as well as the basic capacitance, plus some shunt resistance (see Figure
10.17). In such a practical capacitor, at low frequencies the net impedance is almost
purely capacitive. At intermediate frequencies, the net impedance is determined by
ESR, for example about 0.12 to 0.4 at 125kHz, for several types. Above about
1MHz these capacitor types become inductive, with impedance dominated by the
effect of ESL. All electrolytics will display impedance curves similar in general
shape to that of Figure 10.18. The minimum impedance will vary with the ESR, and
the inductive region will vary with ESL (which in turn is strongly effected by
package style).

CAPACITOR EQUIVALENT CIRCUIT
AND PULSE RESPONSE
0
I
PEAK
= 1A
di
dt
A
ns

1
100
Equivalent f = 3.5MHz
0
V
PEAK
ESL
di
dt
ESR I
PEAK
mV

+ ++ + 400
ESL = 20nH
ESR = 0.2
C = 100F
X
C
= 0.0005
@ 3.5MHz
INPUT
CURRENT
OUTPUT
VOLTAGE
v
i
ESR I
PEAK
= 200mV

Figure 10.17

Regarding inductors, Ferrites (non-conductive ceramics manufactured from the
oxides of nickel, zinc, manganese, or other compounds) are extremely useful in
power supply filters [Reference 9]. At low frequencies (<100kHz), ferrites are
inductive; thus they are useful in low-pass LC filters. Above 100kHz, ferrites
become resistive, an important characteristic in high-frequency filter designs.
Ferrite impedance is a function of material, operating frequency range, DC bias
current, number of turns, size, shape, and temperature. Figure 10.19 summarizes a
number of ferrite characteristics, and Figure 10.20 shows the impedance
characteristic of several ferrite beads from Fair-Rite (http://www.fair-rite.com).

10.26
ELECTROLYTIC CAPACITOR
IMPEDANCE VERSUS FREQUENCY
ESR = 0.2
10kHz 1MHz
LOG FREQUENCY
LOG
|Z|
C (100F)
REGION
ESL (20nH)
REGION
ESR (0.2) ) ) )
REGION

Figure 10.18

FERRITES SUITABLE FOR HIGH FREQUENCY FILTERS
I Ferrites Good for Frequencies Above 25kHz
I Many Sizes and Shapes Available Including Leaded "Resistor
Style"
I Ferrite Impedance at High Frequencies Primarily Resistive --
Ideal for HF Filtering
I Low DC Loss: Resistance of Wire Passing Through Ferrite is
Very Low
I High Saturation Current Versions Available
I Choice Depends Upon:
N Source and Frequency of Interference
N Impedance Required at Interference Frequency
N Environmental: Temperature, AC and DC Field Strength,
Size / Space Available
I Always Test the Design!

Figure 10.19

10.27
IMPEDANCE OF FERRITE BEADS
#73
MATERIAL
#43
MATERIAL
#64
MATERIAL
1 10 100 1000
FREQUENCY (MHz)
Z

0
20
40
60
80
Courtesy: Fair-Rite Products Corp, Wallkill, NY
(http://www.fair-rite.com)

Figure 10.20

Several ferrite manufacturers offer a wide selection of ferrite materials from which
to choose, as well as a variety of packaging styles for the finished network (see
References 10 and 11). A simple form is the bead of ferrite material, a cylinder of
the ferrite which is simply slipped over the power supply lead to the decoupled
stage. Alternately, the leaded ferrite bead is the same bead, pre-mounted on a
length of wire and used as a component (see Reference 11). More complex beads
offer multiple holes through the cylinder for increased decoupling, plus other
variations. Surface mount beads are also available.

PSpice ferrite models for Fair-Rite materials are available, and allow ferrite
impedance to be estimated [see Reference 12]. These models have been designed to
match measured impedances rather than theoretical impedances.

A ferrites impedance is dependent upon a number of inter-dependent variables, and
is difficult to quantify analytically, thus selecting the proper ferrite is not
straightforward. However, knowing the following system characteristics will make
selection easier. First, determine the frequency range of the noise to be filtered.
Second, the expected temperature range of the filter should be known, as ferrite
impedance varies with temperature. Third, the peak DC current flowing through
the ferrite must be known, to ensure that the ferrite does not saturate. Although
models and other analytical tools may prove useful, the general guidelines given
above, coupled with some experimentation with the actual filter connected to the
supply output under system load conditions, should lead to a proper ferrite
selection.

10.28

Using proper component selection, low and high frequency band filters can be
designed to smooth a noisy switchers DC output to produce an analog ready 5V
supply. It is most practical to do this over two (and sometimes more) stages, each
stage optimized for a range of frequencies. A basic stage can be used to carry all of
the DC load current, and filter noise by 60dB or more up to a 1-10MHz range. This
larger filter is used as a card entry filter providing broadband filtering for all power
entering a PC card. Smaller, more simple local filter stages are also used to provide
higher frequency decoupling right at the power pins of individual stages.

Switching Regulator Experiments

In order to better understand the challenge of filtering switching regulators, a series
of experiments were conducted with a representative device, the ADP1148
synchronous buck regulator with a 9V input and a 3.3V/1A output.

In addition to observing typical input and output waveforms, the objective of these
experiments was to reduce the output ripple to less than 10mV peak-to-peak, a
value suitable for driving most analog circuits.

Measurements were made using a Tektronix wideband digitizing oscilloscope with
the input bandwidth limited to 20MHz so that the ripple generated by the switching
regulators could be more readily observed. In a system, power supply ripple
frequencies above 20MHz are best filtered locally at each IC power pin with a low
inductance ceramic capacitor and perhaps a series-connected ferrite bead.

Probing techniques are critical for accurate ripple measurements. A standard
passive 10X probe was used with a "bayonet" probe tip adapter for making the
ground connection as short as possible (see Figure 10.21). Use of the "ground clip
lead" is not recommended in making this type of measurement because the lead
length in the ground connection forms an unwanted inductive loop which picks up
high frequency switching noise, thereby corrupting the signal being measured.

Note: Schematic representation of proper physical grounding is almost impossible. In
all the following circuit schematics, the connections to ground are made to the
ground plane using the shortest possible connecting path, regardless of how they are
indicated in the actual circuit schematic diagram.

The circuit for the ADP1148 9V to 3.3V/1A buck regulator is shown in Figure 10.22.
The output waveform of the ADP1148 buck regulator is shown in Figure 10.23. The
fundamental switching frequency is approximately 150kHz, and the output ripple is
approximately 40mV.

Adding an output filter consisting of a 50H inductor and a 100F leaded tantalum
capacitor reduced the ripple to approximately 3mV.

10.29
PROPER PROBING TECHNIQUES
GROUND PLANE
CONTACT
SIGNAL
CONTACT
IC
SLIP-ON
"BAYONET"
GROUND
ADAPTER
"GROUND CLIP"
CONNECTOR
"GROUND CLIP"
LEAD
(DO NOT USE!!)
PROBE

Figure 10.21

ADP1148 BUCK REGULATOR CIRCUIT
P-DRIVE
SENSE (+)
SENSE ()
I
TH
C
T
INT V
CC
N-DRIVE
SGND PGND
P-CH
N-CH
IRF7403
IRF7204
10BQ040
V
IN
ADP1148-3.3
SHUTDOWN
R
C
, 1k
C
C
L, 50H
R
SENSE
0.1
3300pF
C
T
470pF
1000pF
10nF
1F
220F/25V
+
100F
20V
V
IN
, 9V
V
OUT
3.3V/1A
L=COILTRONICS CTX-50-4
+
C1
C2
C1 = 220F/25V GEN PURPOSE AL ELECTROLYTIC
+ 1F CERAMIC
C2 = 100F/20V LEADED TANTALUM, KEMET T356-SERIES, ESR = 0.6

Figure 10.22
10.30
ADP1148 BUCK OUTPUT WAVEFORM
VERTICAL SCALE: 10mV / DIV
HORIZ. SCALE: 5s / DIV
ADP1148
BUCK
REG
CIRCUIT
+
V
IN
9V
V
OUT
3.3V
1A
C1 = 220 F
+1 F
C2 = 100F/20V
1F 220F
25V
+
100F
20V
C1 = 1F CERAMIC + 220F/25V GENERAL PURPOSE AL ELECTROLYTIC
C2 = 100F/20V LEADED TANTALUM, KEMET T356-SERIES (ESR = 0.6 )
40mV p-p

Figure 10.23

ADP1148 BUCK FILTERED OUTPUT
VERTICAL SCALE: 10mV / DIV
HORIZ. SCALE: 5s / DIV
ADP1148
BUCK
REG
CIRCUIT
+
V
IN
9V
V
OUT
3.3V
1A
C1 = 220 F
+1 F
C2 = 100F/20V
1F 220F
25V
+
100F
20V
+
C
F
100F
20V
L
F

50H
OUTPUT FILTER
L
F
=COILTRONICS CTX-50-4
C
F
= 100F/20V LEADED TANTALUM, KEMET T356-SERIES
C1 = 1F CERAMIC + 220F/25V GENERAL PURPOSE AL ELECTROLYTIC
C2 = 100F/20V LEADED TANTALUM, KEMET T356-SERIES (ESR = 0.6 )
3mV p-p

Figure 10.24

Linear regulators are often used following switching regulators for better regulation
and lower noise. Low dropout (LDO) regulators such as the ADP3310 are desirable
in these applications because they require only a small input-to-output series
10.31
voltage to maintain regulation. This minimizes power dissipation in the pass device
and may eliminate the need for a heat sink. Figure 10.25 shows the ADP1148 buck
regulator configured for a 9V input and a 3.75V/1A output. The output drives an
ADP3310 linear LDO regulator configured for 3.75V input and 3.3V/1A output. The
input and output of the ADP3310 is shown in Figure 10.26. Notice that the
regulator reduces the ripple from 40mV to approximately 5mV.

ADP1148 BUCK REGULATOR DRIVING
ADP3310 LOW DROPOUT REGULATOR
P-DRIVE
SENSE (+)
SENSE ()
I
TH
C
T
INT V
CC
N-DRIVE
SGND PGND
P-CH
N-CH
IRF7403
IRF7204
10BQ040
V
IN
ADP1148
SD
R
C
, 1k
C
C
L, 68H
R
SENSE
0.1
2200pF
C
T
470pF
1000pF
10nF
1F 220F
35V
+
100F
20V
V
IN
, 9V
3.75V
+
C1
C2
FB
GATE
IN OUT
GND
IFR7404
R1
20k
R2
10k
3.3V
1A
ADP3310-3.3 C3
10F
35V
WAVEFORMS

Figure 10.25

WAVEFORMS FOR ADP1148 BUCK REGULATOR
DRIVING ADP3310 LOW DROPOUT REGULATOR
ADP1148 OUTPUT
(ADP3310 INPUT)
ADP3310 OUTPUT
VERTICAL SCALE: 10mV/DIV
HORIZ. SCALE: 5s/DIV
VERTICAL SCALE: 10mV/DIV
HORIZ. SCALE: 5s/DIV
5mV p-p
40mV p-p

Figure 10.26

10.32
There are many tradeoffs in designing power supply filters. The success of any
filter circuit is highly dependent upon a compact layout and the use of a large area
ground plane. As has been stated earlier, all connections to the ground plane should
be made as short as possible to minimize parasitic resistance and inductance.

Output ripple can be reduced by the addition of low ESL/ESR capacitors to the
output. However, it may be more efficient to use an LC filter to accomplish the
ripple reduction. In any case, proper component selection is critical. The inductor
should not saturate under the maximum load current, and its DC resistance should
be low enough as not to induce significant voltage drop. The capacitors should have
low ESL and ESR and be rated to handle the required ripple current.

Low dropout linear post regulators provide both ripple reduction as well as better
regulation and can be effective, provided the sacrifice in efficiency is not excessive.

Finally, it is difficult to predict the output ripple current analytically, and there is
no substitute for a prototype using the real-world components. Once the filter is
proven to provide the desired ripple attenuation (with some added safety margin),
care must be taken that parts substitutions or vendor changes are not made in the
final production units without first testing them in the circuit for equivalent
performance.

SWITCHING SUPPLY FILTER SUMMARY
I Proper Layout and Grounding (using Ground Plane) Mandatory
I Low ESL/ESR Capacitors Give Best Results
I Parallel Capacitors Lower ESR/ESL and Increase Capacitance
I External LC Filters Very Effective in Reducing Ripple
I Linear Post Regulation Effective for Noise Reduction and Best
Regulation
I Completely Analytical Approach Difficult, Prototyping is
Required for Optimum Results
I Once Design is Finalized, Do Not Switch Vendors or Use Parts
Substitutions Without First Verifying Their Performance in
Circuit
I High Frequency Localized Decoupling at IC Power Pins is Still
Required

Figure 10.27

Localized High Frequency Power Supply Filtering

The LC filters described in the previous section are useful in filtering switching
regulator outputs. However, it may be desirable to place similar filters on the
individual PC boards where the power first enters the board. Of course, if the
switching regulator is placed on the PC board, then the LC filter should be an
integral part of the regulator design.
10.33

Localized high frequency filters may also be required at each IC power pin (see
Figure 10.28). Surface mount ceramic capacitors are ideal choices because of their
low ESL. It is important to make the connections to the power pin and the ground
plane as short as possible. In the case of the ground connection, a via directly to the
ground plane is the shortest path. Routing the capacitor ground connection to
another ground pin on the IC is not recommended due to the added inductance of
the trace. In some cases, a ferrite bead in series with the power connection may also
be desirable.

LOCALIZED DECOUPLING TO GROUND PLANE
USING SHORTEST PATH
V+
GND
VIAS TO
GROUND
PLANE
DECOUPLING
CAPACITOR
V+
GND
DECOUPLING
CAPACITOR
VIA TO
GROUND
PLANE
PCB
TRACE
IC
IC
POWER
SUPPLY
TRACE
POWER
SUPPLY
TRACE
CORRECT INCORRECT
OPTIONAL
FERRITE BEADS

Figure 10.28

The following list summarizes the switching power supply filter layout/construction
guidelines which will help ensure that the filter does the best possible job:

(1) Pick the highest electrical value and voltage rating for filter capacitors which is
consistent with budget and space limits. This minimizes ESR, and maximizes filter
performance. Pick chokes for low L at the rated DC current, as well as low DCR.

(2) Use short and wide PCB tracks to decrease voltage drops and minimize
inductance. Make track widths at least 200 mils for every inch of track length for
lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and
inductance.

(3) Use short leads or better yet, leadless components, to minimize lead inductance.
This minimizes the tendency to add excessive ESL and/or ESR. Surface mount
packages are preferred. Make all connections to the ground plane as short as
possible.
10.34

(4) Use a large-area ground plane for minimum impedance.

(5) Know what your components do over frequency, current and temperature
variations! Make use of vendor component models for the simulation of prototype
designs, and make sure that lab measurements correspond reasonably with the
simulation. While simulation is not absolutely necessary, it does instill confidence in
a design when correlation is achieved (see Reference 15).

Filtering the AC Power Lines

The AC power line can also be an EMI entry/exit path! To remove this noise path
and reduce emissions caused by the switching power supply or other circuits, a
power line filter is required.

Figure 10.29 is an example of a hybrid power transient protection network
commonly used in many applications where lightning transients or other power-line
disturbances are prevalent. These networks can be designed to provide protection
against transients as high as 10kV and as fast as 10ns. Gas discharge tubes
(crowbars) and large geometry zener diodes or Transient Voltage Suppressers
(TVSs) are used to provide both differential and common-mode protection. Metal-
oxide varistors (MOVs) can be substituted for the zener diodes or TVSs in less
critical, or in more compact designs. Chokes are used to limit the surge current until
the gas discharge tubes fire.

POWER LINE DISTURBANCES CAN GENERATE EMI
Reprinted from EDN Magazine (January 20, 1994), CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
COMMON-MODE AND DIFFERENTIAL MODE PROTECTION
GAS DISCHARGE
TUBES
"CROWBARS"
CHOKES
TRANSIENT
SUPPRESSORS
BIG ZENERS
OR MOVs
V
N
G
LINE
LOAD

Figure 10.29

Commercial EMI filters, as illustrated in Figure 10.30, can be used to filter less
catastrophic transients or high-frequency interference. These EMI filters provide
both common-mode and differential mode filtering. An optional choke in the safety
ground can provide additional protection against common-mode noise. The value of
10.35

this choke cannot be too large, however, because its resistance may affect power-line
fault clearing. These filters work in both directions: they not only protect the
equipment from surges on the power line but also prevent transients from the
internal switching power supplies from corrupting the power line.

SCHEMATIC FOR A COMMERCIAL POWER LINE FILTER
NOTE: OPTIONAL CHOKE ADDED FOR COMMON-MODE PROTECTION
HOT
NEU
GND
LINE
OPTIONAL
HOT
NEU
LOAD

Figure 10.30

Transformers provide the best common-mode power line isolation. They provide
good protection at low frequencies (<1MHz), and for transients with rise and fall
times greater than 300ns. Most motor noise and lightning transients are in this
range, so isolation transformers work well for these types of disturbances. Although
the isolation between input and output is galvanic, isolation transformers do not
provide sufficient protection against extremely fast transients (<10ns) or those
caused by high-amplitude electrostatic discharge (1 to 3ns). Isolation transformers
can be designed for various levels of differential- or common-mode protection. For
differential-mode noise rejection, the Faraday shield is connected to the neutral,
and for common-mode noise rejection, the shield is connected to the safety ground.

It is important to remember that AC line power can potentially be lethal! Do not
experiment without proper equipment and training! All components used in power
line filters should be UL approved, and the best way to provide this is to specify a
packaged UL approved filter. It should be installed in such a manner that it is the
first circuit the AC line sees upon entering the equipment. Standard three wire IEC
style line cords are designed to mate with three terminal male connectors integral
to many line filters. This is the best way to achieve this function, as it automatically
grounds the third wire to the shell of the filter and equipment chassis via a low
inductance path.

10.36
Commercial power line filters are quite effective in reducing AC power-line noise.
This noise generally has both common-mode and differential-mode components.
Common-mode noise is noise that is found on any two of the three power
connections (black, white, or green) with the same amplitude and polarity. In
contrast, differential-mode noise is noise found only between two lines. By design,
most commercially available filters address both noise modes (see Reference 16).

10.37

REFERENCES: NOISE REDUCTION AND FILTERING

1. EMC Design Workshop Notes, Kimmel-Gerke Associates, Ltd.,
St. Paul, MN. 55108, (612) 330-3728.

2. Walt Jung, Dick Marsh, Picking Capacitors, Parts 1 & 2, Audio,
February, March, 1980.

3. Tantalum Electrolytic and Ceramic Capacitor Families, Kemet
Electronics, Box 5928, Greenville, SC, 29606, (803) 963-6300.

4. Type HFQ Aluminum Electrolytic Capacitor and type V Stacked
Polyester Film Capacitor, Panasonic, 2 Panasonic Way, Secaucus,
NJ, 07094, (201) 348-7000.

5. OS-CON Aluminum Electrolytic Capacitor 93/94 Technical Book,
Sanyo, 3333 Sanyo Road, Forrest City, AK, 72335, (501) 633-6634.

6. Ian Clelland, Metalized Polyester Film Capacitor Fills High Frequency
Switcher Needs, PCIM, June 1992.

7. Type 5MC Metallized Polycarbonate Capacitor, Electronic Concepts, Inc.,
Box 1278, Eatontown, NJ, 07724, (908) 542-7880.

8. Walt Jung, Regulators for High-Performance Audio, Parts 1 and 2,
The Audio Amateur, issues 1 and 2, 1995.

9. Henry Ott, Noise Reduction Techniques in Electronic Systems,
2d Ed., 1988, Wiley.

10. Fair-Rite Linear Ferrites Catalog, Fair-Rite Products, Box J, Wallkill,
NY, 12886, (914) 895-2055, http://www.fair-rite.com.

11. Type EXCEL leaded ferrite bead EMI filter, and type EXC L leadless
ferrite bead, Panasonic, 2 Panasonic Way, Secaucus, NJ, 07094,
(201) 348-7000.

12. Steve Hageman, Use Ferrite Bead Models to Analyze EMI Suppression,
The Design Center Source, MicroSim Newsletter, January, 1995.

10.38
13. Type 5250 and 6000-101K chokes, J. W. Miller, 306 E. Alondra Blvd.,
Gardena, CA, 90247, (310) 515-1720.

14. DIGI-KEY, PO Box 677, Thief River Falls, MN, 56701-0677,
(800) 344-4539.

15. Tantalum Electrolytic Capacitor SPICE Models, Kemet Electronics,
Box 5928, Greenville, SC, 29606, (803) 963-6300.

16. Eichhoff Electronics, Inc., 205 Hallene Road, Warwick, RI., 02886,
(401) 738-1440, http://www.eichhoff.com.

17. Practical Design Techniques for Power and Thermal Management,
Analog Devices, 1998, Chapter 8.
10.39

PREVENTING RFI RECTIFICATION
Walt Kester, Walt Jung, Chuck Kitchin

High frequency radio frequency interference (RFI) can seriously affect the DC
performance of high accuracy circuits. Because of their relatively low bandwidth,
precision operational amplifiers and instrumentation amplifiers will not accurately
amplify RF signals in the MHz range. However, if these out-of-band signals are
allowed to couple into the precision amplifier through either its input, output, or
power supply pins, they can be rectified by various junctions in the amplifier and
ultimately cause an unexplained and unwanted DC offset at the output. An
excellent analysis of the phenomenon is found in Reference 1, but the purpose here
is to show how proper filtering can be used to minimize or prevent these errors.

We have previously discussed how proper power supply decoupling techniques will
minimize RFI on the IC power pins. Further discussion is required with respect to
the amplifier inputs and outputs.

The best way to prevent rectification due to input RFI is to use a filter located close
to the op amp input as shown in Figure 10.31. In the case of the inverting op amp,
the filter capacitor C1 is placed between R1 and R2. The DC closed loop gain of the
circuit is R3/(R1+R2). C1 is not connected directly to the inverting input of the op
amp because that would result in instability. The filter bandwidth is chosen to be at
least 100 times larger than the actual signal bandwidth to prevent signal
attenuation. For the non-inverting configuration, the filter capacitor can be
connected directly to the op amp input as shown.

It should be noted that a ferrite bead can be used instead of R1, however ferrite
bead impedance is not well controlled and is generally no greater than 100 at
10MHz to 100MHz. This requires a large value capacitor to attenuate the lower
frequencies.

Precision instrumentation amplifiers are particularly sensitive to common-mode
RFI. Proper filtering is shown in Figure 10.32. Note that there is both common-
mode filtering (R1/C1, R2/C2) and differential mode filtering (R1+R2, and C3). If
R1/R2 and C1/C2 are not well matched, some of the input common-mode signal at
V
IN
will be converted to a differential one at the in-amp inputs. For this reason, C1
and C2 should be matched to within at least 5% of each other. R1 and R2 should be
1% metal film resistors to insure matching. Capacitor C3 attenuates the differential
signal which can result from imperfect matching of the common-mode filters. In this
type of filter, C3 should be much larger than C1 or C2 in order to ensure that any
differential signal due to mismatching of the common-mode signals is sufficiently
attenuated.

The overall filter bandwidth should be chosen to be at least 100 times the input
signal bandwidth. The components should be symmetrically mounted on a PC board
with a large area ground plane and placed very close to the in-amp input for
optimum performance of the filter.

10.40
FILTERING AMPLIFIER INPUTS
TO PREVENT RFI RECTIFICATION
R1 = 2R R2 = 2R
R3
C1
_
+
C1
R1 = R
+
_
R3
R2
FILTER BANDWIDTH =
1
2 R C1
> 100 SIGNAL BANDWIDTH

Figure 10.31

FILTERING IN-AMP INPUTS
IN-AMP
R1
R2
C1
C2
C3
+
_
R1 = R2
C1 = C2

DIFF
= (R1 + R2) C3

CM
= R1C1 = R2C2
DIFF
>>
CM
R1 = R2 SHOULD BE 1% RESISTORS
C1 = C2 SHOULD BE 5% CAPACITORS
DIFFERENTIAL
FILTER BANDWIDTH
V
IN
1
2 (R1 + R2)
R1C1 SHOULD MATCH R2C2
C1C2
C1 + C2
+ C3
=

Figure 10.32

10.41
Figure 10.33 shows an actual filter for use with the AD620 in-amp. The common-
mode rejection was tested by applying a 1V p-p common-mode signal to the input
resistors. The AD620 gain was 1000. The RTI offset voltage of the in-amp was
measured as the frequency of the sinewave source was varied from DC to 20MHz.
The maximum RTI input offset voltage shift was 1.5V. The filter bandwidth was
approximately 400Hz.

Common-mode chokes offer a simple, one component alternative to RC passive
filters. Selecting the proper common-mode choke is critical, however. The choke
used in the circuit of Figure 10.34 was a Pulse Engineering B4001 designed for
XDSL data receivers (through-hole mount). The B4003 is an equivalent surface
mount choke. The maximum RTI offset shift measured from DC to 20MHz was
4.5V. Unlike the RC filter of Figure 10.32, the choke-based filter offers no
differential mode filtration, as shown.

COMMON AND DIFFERENTIAL MODE FILTER WITH AD620
AD620
R1
R2
C1
C2
C3
+
_
4.02k
1%
4.02k
1%
1000pF, 5%
1000pF, 5%
0.047F
R
G
= 49.9 G = 1000
SINEWAVE
SOURCE
50
DC TO 20MHz
1V p-p
FILTER BANDWIDTH 400Hz
OFFSET SHIFT RTI < 1.5 V

Figure 10.33

In addition to filtering the inputs and the power pins, amplifier outputs need to be
protected from RFI, especially if they must drive long lengths of cable. RFI on the
output can couple into the amplifier where it is rectified and appears again on the
output as a DC offset shift. A resistor or ferrite bead in series with the output is the
simplest output filter. Adding a capacitor as shown in Figure 10.35 improves this
filter, but the capacitor should not be connected to the op-amp side of the resistor
because it may cause the amplifier to become unstable. Many amplifiers are
sensitive to direct output capacitive loads, so this condition should be avoided unless
the amplifier data sheet clearly specifies that the output is insensitive to capacitive
loading.

10.42
COMMON MODE CHOKE WITH AD620
AD620
+
_
R
G
= 49.9 G = 1000
SINEWAVE
SOURCE
50
DC TO 20MHz
1V p-p
COMMON MODE CHOKE:
PULSE ENGINEERING B4001
http://www.pulseeng.com
OFFSET SHIFT RTI < 4.5 V

Figure 10.34

FILTERING AMPLIFIER OUTPUTS PROTECTS
AGAINST EMI/RFI EMISSION AND SUSCEPTIBILITY
AMP
RESISTOR OR
FERRITE BEAD
AMP
RESISTOR OR
FERRITE BEAD
AMP
RESISTOR OR
FERRITE BEAD
C
C
MAY CAUSE
INSTABILITY

Figure 10.35

10.43
REFERENCES ON RFI RECTIFICATION

1. System Applications Guide, Analog Devices, Inc., 1993, Section 1,
pp. 1.37-1.55.

2. Pulse Engineering, Inc., 12220 World Trade Drive, San Diego, CA
92128, 619-674-8100, http://www.pulseeng.com.
10.44

DEALING WITH HIGH SPEED LOGIC

Much has been written about terminating printed circuit board traces in their
characteristic impedance to avoid reflections. A good rule-of-thumb to determine
when this is necessary is as follows: Terminate the line in its characteristic
impedance when the one-way propagation delay of the PCB track is equal to or
greater than one-half the applied signal rise/fall time (whichever edge is faster). A
conservative approach is to use a 2 inch (PCB track length)/nanosecond (rise-, fall-
time) criterion. For example, PCB tracks for high-speed logic with rise/fall time of
5ns should be terminated in their characteristic impedance if the track length is
equal to or greater than 10 inches (including any meanders). The 2 inch/nanosecond
track length criterion is summarized in Figure 10.36 for a number of logic families.

LINE TERMINATION SHOULD BE USED WHEN
LENGTH OF PCB TRACK EXCEEDS 2 inches/ns
DIGITAL IC
FAMILY
t
r
, t
s
(ns)
PCB TRACK LENGTH
(inches)
PCB TRACK LENGTH
(cm)
GaAs 0.1 0.2 0.5
ECL 0.75 1.5 3.8
Schottky 3 6 15
FAST 3 6 15
AS 3 6 15
AC 4 8 20
ALS 6 12 30
LS 8 16 40
TTL 10 20 50
HC 18 36 90
t
r
= rise time of signal in ns
t
f
= fall time of signal in ns
For analog signals @ f
max
, calculate t
r
= t
f
= 0.35 / fmax

Figure 10.36

This same 2 inch/nanosecond rule of thumb should be used with analog circuits in
determining the need for transmission line techniques. For instance, if an amplifier
must output a maximum frequency of f
max
, then the equivalent risetime, t
r
, can be
calculated using the equation t
r
= 0.35/f
max
.

10.45
The maximum PCB track length is then calculated by multiplying the risetime by 2
inch/nanosecond. For example, a maximum output frequency of 100MHz
corresponds to a risetime of 3.5ns, and a track carrying this signal greater than 7
inches should be treated as a transmission line.

Equation 10.1 can be used to determine the characteristic impedance of a PCB track
separated from a power/ground plane by the boards dielectric (microstrip
transmission line):

( ) Z
o
r
+1.41
5.98d
0.89w+ t

]
]
]
87
ln Eq. 10.1

where
r
= dielectric constant of printed circuit board material;
d = thickness of the board between metal layers, in mils;
w = width of metal trace, in mils; and
t = thickness of metal trace, in mils.

The one-way transit time for a single metal trace over a power/ground plane can be
determined from Eq.10.2:

( ) t
pd
ns / ft 1.017 0.475
r
0.67 + Eq. 10.2

For example, a standard 4-layer PCB board might use 8-mil wide, 1 ounce (1.4 mils)
copper traces separated by 0.021" FR-4 (
r
=4.7) dielectric material. The
characteristic impedance and one-way transit time of such a signal trace would be
88 and 1.7ns/ft (7"/ns), respectively.

The best ways to keep sensitive analog circuits from being affected by fast logic are
to physically separate the two and to use no faster logic family than is dictated by
system requirements. In some cases, this may require the use of several logic
families in a system. An alternative is to use series resistance or ferrite beads to
slow down the logic transitions where the speed is not required. Figure 10.37 shows
two methods. In the first, the series resistance and the input capacitance of the gate
form a lowpass filter. Typical CMOS input capacitance is 10pF. Locate the series
resistor close to the driving gate. The resistor minimizes transient currents and may
eliminate the necessity of using transmission line techniques. The value of the
resistor should be chosen such that the rise and fall times at the receiving gate are
fast enough to meet system requirement, but no faster. Also, make sure that the
resistor is not so large that the logic levels at the receiver are out of specification
because of the source and sink current which must flow through the resistor.

10.46
SLOW DOWN FAST LOGIC EDGES
TO MINIMIZE EMI/RFI PROBLEMS
LOGIC
GATE
LOGIC
GATE
R
C C
IN
LOGIC
GATE
LOGIC
GATE
R
C
IN
Risetime = 2.2 RC
IN
Risetime = 2.2 R(C + C
IN
)
< 2 inches
> 2 inches

Figure 10.37

10.47
A REVIEW OF SHIELDING CONCEPTS

The concepts of shielding effectiveness presented next are background material.
Interested readers should consult References 1,3, and 4 cited at the end of the
section for more detailed information.

Applying the concepts of shielding requires an understanding of the source of the
interference, the environment surrounding the source, and the distance between the
source and point of observation (the receptor or victim). If the circuit is operating
close to the source (in the near-, or induction-field), then the field characteristics are
determined by the source. If the circuit is remotely located (in the far-, or radiation-
field), then the field characteristics are determined by the transmission medium.

A circuit operates in a near-field if its distance from the source of the interference is
less than the wavelength () of the interference divided by 2, or /2. If the
distance between the circuit and the source of the interference is larger than this
quantity, then the circuit operates in the far field. For instance, the interference
caused by a 1ns pulse edge has an upper bandwidth of approximately 350MHz. The
wavelength of a 350MHz signal is approximately 32 inches (the speed of light is
approximately 12"/ns). Dividing the wavelength by 2 yields a distance of
approximately 5 inches, the boundary between near- and far-field. If a circuit is
within 5 inches of a 350MHz interference source, then the circuit operates in the
near-field of the interference. If the distance is greater than 5 inches, the circuit
operates in the far-field of the interference.

Regardless of the type of interference, there is a characteristic impedance associated
with it. The characteristic, or wave impedance of a field is determined by the ratio
of its electric (or E-) field to its magnetic (or H-) field. In the far field, the ratio of the
electric field to the magnetic field is the characteristic (wave impedance) of free
space, given by Z
o
= 377. In the near field, the wave-impedance is determined by
the nature of the interference and its distance from the source. If the interference
source is high-current and low-voltage (for example, a loop antenna or a power-line
transformer), the field is predominately magnetic and exhibits a wave impedance
which is less than 377. If the source is low-current and high-voltage (for example,
a rod antenna or a high-speed digital switching circuit), then the field is
predominately electric and exhibits a wave impedance which is greater than 377.

Conductive enclosures can be used to shield sensitive circuits from the effects of
these external fields. These materials present an impedance mismatch to the
incident interference because the impedance of the shield is lower than the wave
impedance of the incident field. The effectiveness of the conductive shield depends
on two things: First is the loss due to the reflection of the incident wave off the
shielding material. Second is the loss due to the absorption of the transmitted wave
within the shielding material. Both concepts are illustrated in Figure 10.38. The
amount of reflection loss depends upon the type of interference and its wave
impedance. The amount of absorption loss, however, is independent of the type of
interference. It is the same for near- and far-field radiation, as well as for electric or
magnetic fields.

10.48

REFLECTION AND ABSORPTION ARE THE TWO
PRINCIPAL SHIELDING MECHANISMS
INCIDENT RAY
REFLECTED RAY
ABSORPTIVE
REGION
SHIELD
MATERIAL
TRANSMITTED
RAY

Figure 10.38

Reflection loss at the interface between two media depends on the difference in the
characteristic impedances of the two media. For electric fields, reflection loss
depends on the frequency of the interference and the shielding material. This loss
can be expressed in dB, and is given by:

( ) R
e
dB = 322 +10log
10
r
r
f
3
r
2
]
]
]
]
Eq. 10.3

where
r
= relative conductivity of the shielding material, in Siemens per meter;
r
= relative permeability of the shielding material, in Henries per meter;
f = frequency of the interference, and
r = distance from source of the interference, in meters

For magnetic fields, the loss depends also on the shielding material and the
frequency of the interference. Reflection loss for magnetic fields is given by:

( ) R
m
dB =14.6 +10log
10
f r
2
r
r
]
]
]
]
Eq. 10.4

10.49

and, for plane waves ( r > /2), the reflection loss is given by:

( ) R
pw
dB =168 +10log
10
r
r
f
]
]
]
Eq. 10.5

Absorption is the second loss mechanism in shielding materials. Wave attenuation
due to absorption is given by:

( ) A dB = 3.34 t
r r
f Eq. 10.6

where t = thickness of the shield material, in inches. This expression is valid for
plane waves, electric and magnetic fields. Since the intensity of a transmitted field
decreases exponentially relative to the thickness of the shielding material, the
absorption loss in a shield one skin-depth () thick is 9dB. Since absorption loss is
proportional to thickness and inversely proportional to skin depth, increasing the
thickness of the shielding material improves shielding effectiveness at high
frequencies.

Reflection loss for plane waves in the far field decreases with increasing frequency
because the shield impedance, Z
s
, increases with frequency. Absorption loss, on the
other hand, increases with frequency because skin depth decreases. For electric
fields and plane waves, the primary shielding mechanism is reflection loss, and at
high frequencies, the mechanism is absorption loss. For these types of interference,
high conductivity materials, such as copper or aluminum, provide adequate
shielding. At low frequencies, both reflection and absorption loss to magnetic fields
is low; thus, it is very difficult to shield circuits from low-frequency magnetic fields.
In these applications, high-permeability materials that exhibit low-reluctance
provide the best protection. These low-reluctance materials provide a magnetic
shunt path that diverts the magnetic field away from the protected circuit. Some
characteristics of metallic materials commonly used for shielded enclosures are
shown in Figure 10.39.

A properly shielded enclosure is very effective at preventing external interference
from disrupting its contents as well as confining any internally-generated
interference. However, in the real world, openings in the shield are often required to
accommodate adjustment knobs, switches, connectors, or to provide ventilation.
Unfortunately, these openings may compromise shielding effectiveness by providing
paths for high-frequency interference to enter the instrument.

10.50
CONDUCTIVITY AND PERMEABILITY FOR
VARIOUS SHIELDING MATERIALS
MATERIAL RELATIVE
CONDUCTIVITY
RELATIVE
PERMEABILITY
Copper 1 1
Aluminum 1 0.61
Steel 0.1 1,000
Mu-Metal 0.03 20,000
Conductivity: Ability to Conduct Electricity
Permeability: Ability to Absorb Magnetic Energy

Figure 10.39

The longest dimension (not the total area) of an opening is used to evaluate the
ability of external fields to enter the enclosure, because the openings behave as slot
antennas. Equation 10.7 can be used to calculate the shielding effectiveness, or the
susceptibility to EMI leakage or penetration, of an opening in an enclosure:

( ) Shielding Effectiveness dB = 20log
10
2 L
|
(
'
`
J
J
Eq. 10.7

where = wavelength of the interference and
L = maximum dimension of the opening

Maximum radiation of EMI through an opening occurs when the longest dimension
of the opening is equal to one half-wavelength of the interference frequency (0dB
shielding effectiveness). A rule-of-thumb is to keep the longest dimension less than
1/20 wavelength of the interference signal, as this provides 20dB shielding
effectiveness. Furthermore, a few small openings on each side of an enclosure is
preferred over many openings on one side. This is because the openings on different
sides radiate energy in different directions, and as a result, shielding effectiveness
is not compromised. If openings and seams cannot be avoided, then conductive
gaskets, screens, and paints alone or in combination should be used judiciously to
limit the longest dimension of any opening to less than 1/20 wavelength. Any cables,
wires, connectors, indicators, or control shafts penetrating the enclosure should
have circumferential metallic shields physically bonded to the enclosure at the point
of entry. In those applications where unshielded cables/wires are used, then filters
are recommended at the point of shield entry.

10.51
General Points on Cables and Shields

Although covered in more detail later, the improper use of cables and their shields
is a significant contributor to both radiated and conducted interference. Rather than
developing an entire treatise on these issues, the interested reader should consult
References 1,2, 4, and 5. As illustrated in Figure 10.40, effective cable and enclosure
shielding confines sensitive circuitry and signals within the entire shield without
compromising shielding effectiveness. As shown in the diagram, the enclosures and
the shield must be grounded properly, otherwise they will act as an antenna and
make the radiated and conducted interference problem worse.

"ELECTRICALLY LONG" OR "ELECTRICALLY SHORT"
APPLICATION
SHIELDED ENCLOSURE A SHIELDED ENCLOSURE B
LENGTH
SHIELDED
CABLE
FULLY SHIELDED ENCLOSURES CONNECTED BY FULLY
SHIELDED CABLE KEEP ALL INTERNAL CIRCUITS AND
SIGNAL LINES INSIDE THE SHIELD.
TRANSITION REGION: 1/20 WAVELENGTH

Figure 10.40

Depending on the type of interference (pickup/radiated, low/high frequency), proper
cable shielding is implemented differently and is very dependent on the length of
the cable. The first step is to determine whether the length of the cable is
electrically short or electrically long at the frequency of concern. A cable is
considered electrically short if the length of the cable is less than 1/20 wavelength of
the highest frequency of the interference, otherwise it is electrically long. For
example, at 50/60Hz, an electrically short cable is any cable length less than 150
miles, where the primary coupling mechanism for these low frequency electric fields
is capacitive. As such, for any cable length less than 150 miles, the amplitude of the
interference will be the same over the entire length of the cable.

In those applications where the length of the cable is electrically long, or protection
against high-frequency interference is required, then the preferred method is to
connect the cable shield to low-impedance points at both ends (direct connection at
the driving end, and capacitive connection at the receiver). Otherwise, unterminated
10.52
transmission lines effects can cause reflections and standing waves along the cable.
At frequencies of 10MHz and above, circumferential (360) shield bonds and metal
connectors are required to main low-impedance connections to ground.

In summary, for protection against low-frequency (<1MHz), electric-field
interference, grounding the shield at one end is acceptable. For high-frequency
interference (>1MHz), the preferred method is grounding the shield at both ends,
using 360 circumferential bonds between the shield and the connector, and
maintaining metal-to-metal continuity between the connectors and the enclosure.

Grounding the shield at both ends, however, can create a low frequency ground loop
in a practical situation as shown in Figure 10.41.

GROUND LOOPS IN SHIELDED TWISTED PAIR CABLE
A2 A1
V
N
I
N
V
N
Causes Current in Shield (Usually 50/60Hz)
Differential Error Voltage is Produced at Input of A2 Unless:
A1 Output is Perfectly Balanced and
A2 Input is Perfectly Balanced and
Cable is Perfectly Balanced
GND 1 GND 2

Figure 10.41

As discussed above, cable shields can be subjected to both low and high frequency
interference. Good design practice requires that the shield be grounded at both ends
if the cable is electrically long to the interference frequency, as is usually the case
with RF interference.

When two systems A1 and A2 are remote from each other, however, there is usually
a difference in the ground potentials at each system. The frequency of this potential
difference is generally the line frequency (50Hz or 60Hz) and multiples thereof. If
the shield is grounded at both ends as shown, however, a noise current flows
through the shield. In a perfectly balanced system, the common-mode rejection of
the system is infinite, and this current produces no differential error at the receiver
A2. However, perfect balance is never achieved in the driver, its impedance, the
cable, or the receiver, so a certain portion of the shield current will appear as a
10.53
differential signal at the input of A2. The following examples illustrate the correct
way to ground the shield under various conditions.

Figure 10.42 shows a remote passive RTD sensor connected to a bridge and
conditioning circuit by a shielded cable. The proper grounding method is shown in
the upper part of the figure, where the shield is grounded at the receiving end.
However, safety considerations may require that the remote end of the shield be
grounded. If this is the case, the receiving end can be grounded with a low
inductance ceramic capacitor (0.01F to 0.1F) . The capacitor acts as a ground to
RF signals on the shield but blocks line frequency current to flow in the shield. This
technique is often referred to as a hybrid ground.

In the case of an active remote sensor (Figure 10.43), the hybrid ground is also
appropriate, either for a balanced or single-ended driver. The capacitor breaks the
DC ground loop in both cases. In both cases, the line is driven from an impedance of
R
S
, split between legs. In the case of the bottom diagram, the R
S
/2 resistor in the
return leg can only be used for applications with a balanced receiver, as shown.

GROUNDING SHIELDED CABLE WITH
REMOTE PASSIVE SENSOR
NC
C
RTD
RTD
BRIDGE
AND
CONDITIONING
CIRCUITS
BRIDGE
AND
CONDITIONING
CIRCUITS
"HYBRID
GROUND

Figure 10.42

Coaxial cables are different from shielded twisted pair cables in that the signal
return current path is through the shield. For this reason, the ideal situation is to
ground the shield at the driving end and allow the shield to float at the differential
receiver (A2) as shown in Figure 10.44. For this technique to work, however, the
receiver must be differential and have good high frequency common mode rejection.
If the receiver is a single-ended type, there is no choice but to ground the coaxial
cable shield at both ends.

10.54
GROUNDING SHIELDED CABLE
WITH REMOTE ACTIVE SENSOR
A2
C
A1
A1 A2
C
R
S
/2
R
S
/2
R
S
/2
R
S
/2

Figure 10.43

COAXIAL CABLE GROUNDING
A1 A2
COAX CABLE
Shield Carries Signal Return Current
A1 A2
DIFF
AMP
SINGLE-
ENDED
AMP

Figure 10.44

10.55
Digital Isolation Techniques

Another way to break ground loops is to use isolation techniques. Analog isolation
amplifiers find many applications where a high degree of isolation is required, such
as in medical instrumentation. Digital isolation techniques offer a reliable method
of transmitting digital signals over interfaces without introducing ground noise.

Optoisolators are useful and available in a wide variety of styles and packages.
Current is applied to an LED transmitter as shown in Figure 10.45. The light
output is received by a phototransistor. Isolation voltages range from 5000V to
7000V. In the circuit, the LED is driven with a current of approximately 10mA. This
produces a light output sufficient to saturate the phototransistor. Although
excellent for digital signals, optoisolators are too nonlinear for most analog
applications. One should realize that since the phototransistor is operated in a
saturated mode, rise and fall-times can range from 10s to 20s in some slower
devices, so the proper optoisolator for the application must be selected.

ISOLATION USING OPTOISOLATORS
I
OUT
HIGH VOLTAGE
ISOLATION BARRIER
Uses Light for Transmission Over a High Voltage Barrier
The LED is the Transmitter, and the Phototransistor is the Receiver
High Voltage Isolation: 5000V to 7000V
Non-Linear -- Best for Digital or Frequency Information
Rise and Fall-times can be 10 to 20s in Slower Devices
Example: Siemens IL-1 (http://www.siemens.com)
+V, (5V) 10k
I
IN
+V, (5V) 425
G1
G2
CMOS
GATE
V
OUT

Figure 10.45

The AD260/AD261 family of digital isolators isolates five digital control signals
to/from high speed DSPs, microcontrollers, or microprocessors. The AD260 also has
a 1.5W transformer for a 3.5kV isolated external DC/DC power supply circuit.
10.56

Each line of the AD260 can handle digital signals up to 20MHz with a propagation
delay of only 14ns which allows for extremely fast data transmission. Output
waveform symmetry is maintained to within 1ns of the input so the AD260 can be
used to accurately isolate time-based pulse width modulator (PWM) signals.

A simplified schematic of one channel of the AD260/AD261 is shown in Figure
10.46. The data input is passed through a schmitt trigger circuit, through a latch,
and a special transmitter circuit which differentiates the edges of the digital input
signal and drives the primary winding of a proprietary transformer with a "set-
high/set-low" signal. The secondary of the isolation transformer drives a receiver
with the same "set-hi/set-low" data which regenerates the original logic waveform.
An internal circuit operates in the background which interrogates all inputs about
every 5s and in the absence of logic transitions, sends appropriate "set-hi/set-low"
data across the interface. Recovery time from a fault condition or at power-up is
thus between 5s and 10s.

The power transformer (available on the AD260) is designed to operate between
150kHz and 250kHz and will easily deliver more than 1W of isolated power when
driven push-pull (5V) on the transmitter side. Different transformer taps, rectifier
and regulator schemes will provide combinations of 5V, 15V, 24V, or even 30V or
higher. The output voltage when driven with a low voltage-drop drive will be
37V p-p across the entire secondary with a 5V push-pull drive.

AD260/AD261 DIGITAL ISOLATORS
D
CONTINUOUS
UPDATE
CIRCUIT
E
SCHMITT
TRIGGER
LATCH
XMTR RCVR
TRI STATE
ENABLE
ENABLE
ISOLATED POWER
XFMR (AD260)
37V p-p, 1.5W
NOTE: SINGLE DATA CHANNEL SHOWN
3.5kV RMS ISOLATION BARRIER
(AD260B/AD261B)
DATA
IN DATA
OUT

Figure 10.46

10.57
AD260/AD261 DIGITAL ISOLATOR KEY SPECIFICATIONS
I Isolation Test Voltage to 3.5kV RMS (AD260B/AD261B)
I Five Isolated Digital Lines Available in 6 Input/Output Configurations
I Logic Signal Frequency: 20MHz Max.
I Isolated Power Transformer: 37V p-p, 1.5W (AD260)
I Waveform Edge Transmission Symmetry: 1ns
I Propagation Delay: 14ns
I Rise and Fall-Times < 5ns

Figure 10.47

REFERENCES ON EMI/RFI AND SHIELDING

1. EDNs Designers Guide to Electromagnetic Compatibility, EDN,
January, 20, 1994, material reprinted by permission of Cahners Publishing
Company, 1995.

2. Designing for EMC (Workshop Notes), Kimmel Gerke Associates, Ltd., 1994.

3. Systems Application Guide, Chapter 1, pg. 21-55, Analog Devices,
Incorporated, Norwood, MA, 1994.

4. Henry Ott, Noise Reduction Techniques In Electronic Systems,
Second Edition, New York, John Wiley & Sons, 1988.

5. Ralph Morrison, Grounding And Shielding Techniques In
Instrumentation, Fourth Edition, New York, John Wiley & Sons, 1998.

6. Amplifier Applications Guide, Chapter XI, pg. 61, Analog Devices,

7. B.Slattery and J.Wynne, Design and Layout of a Video Graphics
System for Reduced EMI, Analog Devices Application Note AN-333.
10.58

8. Paul Brokaw, An IC Amplifier User Guide To Decoupling, Grounding,
And Making Things Go Right For A Change, Analog Devices
Application Note, Order Number E1393-5-590.

9. A. Rich, Understanding Interference-Type Noise, Analog Dialogue, 16-3,
1982, pp. 16-19.

10. A. Rich, Shielding and Guarding, Analog Dialogue, 17-1, 1983, pp. 8-13.

11. EMC Test & Design, Cardiff Publishing Company, Englewood, CO.
An excellent, general purpose trade journal on issues of EMI and EMC.

12. A. Rich, Understanding Interference-Type Noise, Analog Dialogue,
16-3, 1982, pp. 16-19.

13. James Bryant and Herman Gelbach, High Frequency Signal
Contamination, Analog Dialogue, Vol. 27-2, 1993.

14. Walt Jung, System RF Interference Prevention, Analog Dialogue,
Vol. 28-2, 1994.

15. Neil Muncy, Noise Susceptibility in Analog and Digital Signal
Processing Systems, presented at 97th Audio Engineering Society
Convention, Nov. 1994.

16. Ralph Morrison, Solving Interference Problems in Electronics,
John Wiley, 1995.

17. Siemens Optoisolator Products, http://www.siemens.com.

10.59

OVERVOLTAGE PROTECTION
Walt Kester, Wes Freeman, Joe Buxton

Op amps and instrumentation amplifiers must often interface to the outside world,
which may entail handling voltages that exceed their absolute maximum ratings.
Sensors are often placed in an environment where a fault may connect the sensor to
high voltages: if the sensor is connected to an amplifier, the amplifier inputs may
see voltages exceeding its power supplies. Whenever its input voltage goes outside
its supply range, an op amp may be damaged, even when they are turned off.
Almost all op amps' input absolute maximum ratings limit the maximum allowable
input voltage to the positive and negative supplies or possibly 0.3V outside these
supplies. A few exceptions to this rule do exist, which can be identified from
individual data sheets, but the vast majority of amplifiers require input protection if
over-voltage can possibly occur.

Any op amp input will break down to the positive rail or the negative rail if it
encounters sufficient over-voltages. The breakdown voltage is entirely dependent on
the structure of the input stage. It may be equivalent to a diode drop of 0.7V or to a
process breakdown voltage of 50V or more. The danger of an over-voltage is that
when conduction occurs large currents may flow, which can destroy the device. In
many cases, over-voltage results in current well in over 100mA, which can destroy a
part almost instantly.

To avoid damage, input current should be limited to less than 5mA unless otherwise
stated on the relevant data sheet. This value is a conservative rule of thumb based
on metal trace widths in a typical op amp input stage. Higher levels of current can
cause metal migration, which will eventually lead to an open trace. Migration is a
cumulative effect that may not result in a failure for a long period of time. Failure
may occur due to multiple over-voltages, which is a difficult failure mode to identify.
Thus, even though an amplifier may appear to withstand over-voltage currents well
above 5mA for a short period of time, it is important to limit the current to
guarantee long term reliability.

Two types of conduction occur in over-voltage conditions, forward biasing of PN
junctions inherent in the structure of the input stage or, given enough voltage,
reverse junction breakdown. The danger of forward biasing a PN-junction is that
excessive current will flow and damage the part. As long as the current is limited no
damage should occur. However, when the conduction is due to the reverse
breakdown of a PN junction, the problem can be more serious. In the case of a base-
emitter junction break down, even small amounts of current can cause degradation
in the beta of the transistor. After a breakdown occurs, input parameters such as
offset and bias current may be well out of specification. Diode protection is needed
to prevent base-emitter junction breakdown. Other junctions, such as base-collector
junctions and JFET gate-source junctions do not exhibit the same degradation in
performance on break down, and for these the input current should be limited to
5mA, unless the data sheet specifies a larger value.

10.60
INPUT OVERVOLTAGE
I INPUT SHOULD NOT EXCEED ABSOLUTE MAXIMUM RATINGS
(Usually Specified With Respect to Supply Voltages)
I A Common Specification Requires the Input Signal Remain
Within 0.3V of the Supply Rails
I Input Stage Conduction Current Should Be Limited
(Rule of Thumb: < 5mA Unless Otherwise Specified)
I Avoid Reverse Bias Junction Breakdown in Input Stage Junctions
I Differential and Common Mode Ratings May Differ
I No Two Amplifiers are Exactly the Same
I Some ICs Contain Input Protection (Voltage Clamps, Current Limits,
or Both), but Absolute Maximum Ratings Must Still Be Observed

Figure 10.48

A generalized external protection circuit using two Schottky diodes and an external
current limiting resistor can be used to ensure input protection as shown in Figure
10.49. If the op amp has internal protection diodes to the supplies, they will conduct
at about 0.6V forward drop above or below the supply rails. The external current
limit resistor must be chosen so that the maximum amount of input current is
limited to 5mA. This can result in large values of R
LIMIT
, and the resulting
increase in noise and offset voltage may not be acceptable. For instance, to protect
against a 100V input at V
IN
, R
LIMIT
must be greater than 20k (assuming a worst
case condition where the supply voltages are at zero volts). The external Schottky
protection diodes will begin to conduct at about 0.3V, and overvoltage current is
shunted through them to the supply rails rather than through the internal ones.
This allows R
LIMIT
to be set by the maximum allowable diode current, which can
be much larger than the internal limit of 5mA. For instance, a 500 R
LIMIT

resistor would limit the diode current to 200mA for a V
IN
of 100V.
A protection resistor in series with an amplifier input will also produce a voltage
drop due to the amplifier bias current flowing through it. This drop appears as an
increase in the circuit offset voltage (and, if the bias current changes with
temperature, offset drift). In amplifiers where bias currents are approximately
equal, a resistor in series with each input will tend to balance the effect and reduce
the error.

When using external Schottky clamp diodes to protect operational amplifier inputs,
the effects of diode junction capacitance and leakage current should be evaluated in
the application. Diode junction capacitance and R
LIMIT
will add an additional pole
in the signal path, and diode leakage currents will double for every 10C rise in
ambient temperature. Therefore, low leakage diodes should be used such that, at
the highest ambient temperature for the application, the total diode leakage current
is less than one-tenth of the input bias current for the device at that temperature.
Another issue with regard to the use of Schottky diodes is the change in their
10.61
forward voltage drop as a function of temperature. These diodes do not, in fact, limit
the signal to 0.3V at all ambient temperatures, but if the Schottky diodes are at
the same temperature as the op amp, they will limit the voltage to a safe level, even
if they do not limit it at all times to within the data sheet rating. This is true if
over-voltage is only possible at turn-on, when the diodes and the op amp will always
be at the same temperature. If the op amp is warm when it is repowered, however,
steps must be taken to ensure that diodes and op amp are at the same temperature.

GENERALIZED EXTERNAL OVERVOLTAGE
PROTECTION CIRCUIT FOR OP AMPS
D1
D2
R
LIMIT
V
IN
R
FB
V
POS
V
OUT
I
LIMIT
I
IN(MAX)
< 5mA
+
_
V
NEG

Figure 10.49

A simplified schematic of the AD620 instrumentation amplifier is shown in Figure
10.50. The 400 input resistors are thin-film, and therefore do not behave as
junctions, as would be the case with diffused resistors. The input transistors Q1 and
Q2 have diodes D1 and D2 across their base-emitter junctions to prevent reverse
breakdown. Figure 10.51 shows an equivalent input circuit for an overvoltage
condition. The common-mode voltage at +V
IN
or V
IN
should be limited to 0.3V
above V
POS
and 0.3V below V
NEG
. In addition, the differential input voltage
should be limited to a value which limits the input current to 10mA maximum. The
equivalent circuit shows that the input current flows through the two external
R
LIMIT
resistors, the two internal R
S
resistors, the gain-setting resistor R
G
, and
two diode drops (Q2 and D1). For a given differential input voltage, the input
current is a function of R
G
and hence the gain. For a gain of 1000, R
G
= 49.9, and
therefore has more of an impact on the input current than for a gain of 10, where
R
G
= 5.49k.

10.62
AD620 SIMPLIFIED SCHEMATIC
V
B
400 400
24.7k 24.7k
10k
10k
10k
10k
V
O
V
REF
+V
IN
V
IN
R
G
+
_
+
_
_
+
V
POS
A1 A2
A3
Q1 Q2
R
G
=
49.4k
G 1
D1
D2
V
NEG

Figure 10.50

AD620 EQUIVALENT INPUT CIRCUIT WITH OVERVOLTAGE
D2
Q2
D1
Q1
V
DIFF
R
S
R
S
400
400
R
G
V
DIFF
= I
IN
( 2R
S
+2R
LIMIT
+ R
G
) + 1.2V
I
IN
V
DIFF(MAX)
< I
IN(MAX)
( 2R
S
+2R
LIMIT
+ R
G
) + 1.2V
I
IN(MAX)

< 10mA
+V
IN
V
IN
R
LIMIT
R
LIMIT
AT +V
IN
AND V
IN
:
V
NEG
0.3V < V
CM
< V
POS
+ 0.3V

Figure 10.51
10.63

A generalized external voltage protection circuit for an in-amp is shown in Figure
10.52. The R
LIMIT
resistors are chosen to limit the maximum current through the
diodes connected to V
POS
and V
NEG
. The Zener diodes or Transient Voltage
Suppressers (TVSs, or TransZorbs) are selected to limit the maximum differential
input voltage to less than |V
POS
V
NEG
| if required.

GENERALIZED EXTERNAL PROTECTION
FOR INSTRUMENTATION AMPLIFIER INPUTS
IN-AMP
R
LIMIT
R
LIMIT
+
_
V
POS
V
IN
V
OUT
*
R
G
V
REF
V
NEG
*ZENER DIODES
OR TVSs (TransZorbs)
LIMIT V
DIFF
IF REQUIRED

Figure 10.52

The two op amp instrumentation (see Figure 10.53) can generally be protected with
external Schottky diodes to the supplies and current limit resistors. The input
current is not a function of the gain-setting resistor as in the case of the three op
amp in-amp configuration.

ADCs whose input range falls between the supply rails can generally be protected
with external Schottky diodes and a current limit resistor as shown in Figure 10.54.
Even if internal ESD protection diodes are provided, the use of the external ones
allows smaller values of R
LIMIT
and lower noise and offset errors. ADCs with thin-
film input attenuators, such as the AD7890-10 (see Figure 10.55), can be protected
with Zener diodes on TVSs with an R
LIMIT
resistor to limit the current through
them.

10.64
INPUT PROTECTION FOR TWO OP AMP IN-AMP (AD627)
+
_
+
_
A1
A2
R2'
R1'
R2
R1
R
G
V
OUT
V
REF
V
2
1 +
R2
R1
+
2R2
R
G
G =
R
LIMIT
R
LIMIT
V
POS
V
IN
V
NEG

Figure 10.53

INPUT PROTECTION FOR ADCs WITH INPUT RANGES
WITHIN SUPPLY VOLTAGES
V
POS
R
LIMIT
V
IN
AIN
*
*
INTERNAL
ESD PROTECTION
DIODES (0.6V)
I
IN
Choose R
LIMIT
to Limit I
IN
Current to 5mA
*Additional External Schottky Diodes Allow Lower
Values of R
LIMIT
V
NEG
ADC

Figure 10.54

10.65
INPUT PROTECTION FOR SINGLE-SUPPLY ADCs WITH
THIN FILM RESISTOR INPUT ATTENUATORS
V
POS
= +5V
AD7890-10
+2.5V
REF
30k
7.5k
10k
10V
RANGE
17V
ABS. MAX.
1N4745
16V, 1W
OR
TVSs
R
LIMIT
R
LIMIT
<< 30k
V
IN
V
NEG

Figure 10.55

Overvoltage Protection Using CMOS Channel Protectors

The ADG465/ADG466/ADG467 are CMOS channel protectors which are placed in
series with the signal path. The channel protector will protect sensitive components
from voltage transients whether the power supplies are present or not. Because the
channel protection works whether the supplies are present or not, the channel
protectors are ideal for use in applications where correct power sequencing cannot
always be guaranteed (e.g., hot-insertion rack systems) to protect analog inputs.

Each channel protector (see Figure 10.56) has an independent operation and
consists of four MOS transistors - two NMOS and two PMOS. One of the PMOS
devices does not lie directly in the signal path but is used to connect the source of
the second PMOS device to its backgate. This has the effect of lowering the
threshold voltage and so increasing the input signal range of the channel for normal
operation. The source and backgate of the NMOS devices are connected for the same
reason.

The channel protector behaves just like a series resistor (60 to 80) during normal
operation, i.e., (V
SS
+ 2V) < V
D
< (V
DD
1.5V). When a channel's analog input
voltage exceeds this range, one of the MOSFETs will switch off, clamping the output
at either V
SS
+ 2V or V
DD
1.5V. Circuitry and signal source protection is
provided in the event of an overvoltage or power loss. The channel protectors can
withstand overvoltage inputs from V
SS
20V to V
DD
+ 20V with power on (V
DD

V
SS
= 44V maximum). With power off (V
DD
= V
SS
= 0V), maximum input voltage
is 35V. The channel protectors are very low power devices, and even under fault
conditions, the supply current is limited to sub microampere levels. All transistors
10.66
are dielectrically isolated from each other using a trench isolation method thereby
ensuring that the channel protectors cannot latch up.

Figure 10.58 shows a typical application that requires overvoltage and power supply
sequencing protection. The application shows a hot-insertion rack system. This
involves plugging a circuit board or module into a live rack via an edge connector. In
this type of application it is not possible to guarantee correct power supply
sequencing. Correct power supply sequencing means that the power supplies should
be connected before any external signals. Incorrect power sequencing can cause a
CMOS device to latch up. This is true of most CMOS devices regardless of the
functionality. RC networks are used on the supplies of the channel protector to
ensure that the rest of the circuit is powered up before the channel protectors. In
this way, the outputs of the channel protectors are clamped well below V
DD
and
V
SS
until the capacitors are charged. The diodes ensure that the supplies on the
channel protector never exceed the supply rails when it is being disconnected. Again
this ensures that signals on the inputs of the CMOS devices never exceed the
supplies.

ADG465, ADG466, and ADG467
SINGLE, TRIPLE, AND OCTAL CHANNEL PROTECTORS
V
DD
V
SS
V
D V
S
V
DD
1.5V
V
SS
+ 2V
V
SS
V
SS
V
D
V
S
V
DD
V
DD
NMOS
PMOS
PMOS
NMOS

Figure 10.56

10.67
ADG465, ADG466, and ADG467
CHANNEL PROTECTORS KEY SPECIFICATIONS
I Low On-Resistance (50 for ADG465, 80 for ADG466/467)
I On-Resistance Match: 3%
I 44V Maximum Supply Voltage, V
DD
V
SS
I Fault and Overvoltage Protection up to 40V
I Positive Overvoltages Clamped at V
DD
1.5V
I Negative Overvoltages Clamped at V
SS
+ 2V
I Signal Paths Open-Circuit with Power Off
I Latch-Up Proof Construction

Figure 10.57

OVERVOLTAGE AND POWER SUPPLY SEQUENCING
PROTECTION USING THE ADG466
EDGE CONNECTOR
+5V
5V
ANALOG IN
2.5V TO +2.5V
LOGIC
LOGIC
GND
ADG466
V
DD
V
SS
ADC
CONTROL
LOGIC

Figure 10.58

10.68
ELECTROSTATIC DISCHARGE
Walt Kester, Wes Freeman, James Bryant

Electrostatic discharge is a single, fast, high current transfer of electrostatic charge
that results from:

(1) Direct contact transfer between two objects at different potentials (sometimes
called contact discharge), or
(2) A high electrostatic field between two objects when they are in close proximity
(sometimes called air discharge)

The prime sources of static electricity are mostly insulators and are typically
synthetic materials, e.g., vinyl or plastic work surfaces, insulated shoes, finished
wood chairs, Scotch tape, bubble pack, soldering irons with ungrounded tips, etc.
Voltage levels generated by these sources can be extremely high since their charge
is not readily distributed over their surfaces or conducted to other objects.

The generation of static electricity caused by rubbing two substances together is
called the triboelectric effect. Examples are shown in Figure 10.59.

EXAMPLES OF ELECTROSTATIC CHARGE GENERATION
I Walking Across a Carpet
N 1000V - 1500V Generated
I Walking Across a Vinyl Floor
I Handling Material Protected by Clear Plastic Covers
I Handling Polyethylene Bags
I Pouring Polyurethane Foam Into a Box
I Note: Assume 60% RH. For Low RH (30%), Generated
Voltages Can Be >10 Times Those Listed Above

Figure 10.59

Integrated circuits can be damaged by the high voltages and high peak currents
that can be generated by electrostatic discharge. Precision analog circuits, which
often feature very low bias currents, are more susceptible to damage than common
digital circuits, because the traditional input-protection structures which protect
against ESD damage also increase input leakage.

10.69
For the design engineer or technician, the most common manifestation of ESD
damage is a catastrophic failure of the IC. However, exposure to ESD can also cause
increased leakage or degrade other parameters. If a device appears to not meet a
data sheet specification during evaluation, the possibility of ESD damage should be
considered.

UNDERSTANDING ESD DAMAGE
I ESD Failure Mechanisms:
N Dielectric or junction damage
N Surface charge accumulation
N Conductor fusing
I ESD Damage Can Cause:
N Increased leakage
N Degradation in performance
N Functional failures of ICs.
I ESD Damage is often Cumulative:
N For example, each ESD "zap" may increase junction
damage until, finally, the device fails.

Figure 10.60

All ESD sensitive devices are shipped in protective packaging. ICs are usually
contained in either conductive foam or antistatic tubes. Either way, the container is
then sealed in a static-dissipative plastic bag. The sealed bag is marked with a
distinctive sticker, such as that shown in Figure 10.61, which outlines the
appropriate handling procedures. In addition, the data sheets for ESD sensitive ICs
generally have a statement to that effect (see Figure 10.62).

Once ESD-sensitive devices are identified, protection is relatively easy. Obviously,
keeping ICs in their original protective packaging as long as possible is the first
step. The second step is to discharge potential ESD sources before damage to the IC
can occur. Discharging a potentially dangerous voltage can be done quickly and
safely through a high impedance.

The key component required for safe ESD handling is a workbench with a static-
dissipative surface, as shown in Figure 10.63. This surface is connected to ground
through a 1M resistor, which dissipates static charge while protecting the user
from electrical shock hazards caused by ground faults. If existing bench tops are
nonconductive, a static-dissipative mat should be added, along with a discharge
resistor.

10.70

RECOGNIZING ESD SENSITIVE DEVICES
All static sensitive devices are sealed in
protective packaging and marked with
special handling instructions
CAUTION
SENSITIVE ELECTRONIC DEVICES
CAUTION
SENSITIVE ELECTRONIC DEVICES
DO NOT SHIP OR STORE NEAR STRONG
ELECTROSTATIC, ELECTROMAGNETIC,
MAGNETIC, OR RADIOACTIVE FIELDS
DO NOT OPEN EXCEPT AT
APPROVED FIELD FORCE
PROTECTIVE WORK STATION

Figure 10.61

ESD STATEMENT ON DATA SHEETS
OF MOST LINEAR AND MIXED-SIGNAL ICs
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (Electrostatic Discharge) sensitive device. Electrostatic charges as
high as 4000 V readily accumulate on the human body and test equipment
and can discharge without detection. Although the ADXXX features
proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Figure 10.62

10.71
WORKSTATION FOR HANDLING
ESD-SENSITIVE DEVICES
BUILDING FLOOR
ESD
PROTECTIVE
FLOOR OR
MAT
ESD PROTECTIVE
TABLE TOP
ESD PROTECTIVE
TRAYS, SHUNTS, ETC.
PERSONNEL
GROUND STRAP
Note: Conductive Table Top Sheet Resistance 1M /

Figure 10.63

Notice that the surface of the workbench has a moderately high sheet resistance. It
is neither necessary nor desirable to use a low-resistance surface (such as a sheet of
copper-clad PC board) for the work surface. Remember, a high peak current may
flow if a charged IC is discharged through a low impedance. This is precisely what
happens when a charged IC contacts a grounded copper clad board. When the same
charged IC is placed on the surface shown in Figure 10.63, however, the peak
current is not high enough to damage the device.

A conductive wrist strap is also recommended while handling ESD-sensitive
devices. The wrist strap ensures that normal tasks, such as peeling tape off of
packages, will not cause damage to ICs. Again, a 1M resistor, from the wrist strap
to ground, is required for safety.

When building prototype breadboards or assembling PC boards which contain ESD-
sensitive devices, all passive components should be inserted and soldered before the
ICs. This procedure minimizes the ESD exposure of the sensitive devices. The
soldering iron must, of course, have a grounded tip.

Protecting ICs from ESD requires the participation of both the IC manufacturer and
the customer. IC manufacturers have a vested interest in providing the highest
possible level of ESD protection for their products. IC circuit designers, process
engineers, packaging specialists and others are constantly looking for new and
improved circuit designs, processes, and packaging methods to withstand or shunt
ESD energy.

10.72
A complete ESD protection plan, however, requires more than building-ESD
protection into ICs. Users of ICs must also provide their employees with the
necessary knowledge of and training in ESD handling procedures (Figure 10.64).

ESD PROTECTION REQUIRES A PARTNERSHIP
BETWEEN THE IC SUPPLIER AND THE CUSTOMER
I Circuit Design and Fabrication -
I Pack and Ship -
I Incoming Inspection -
I Inventory Control -
I Manufacturing -
I Pack and Ship -
ANALOG DEVICES:
CUSTOMERS:
Design and manufacture products with the highest level of ESD
protection consistent with required analog and digital performance.
Pack in static dissipative material. Mark packages with ESD warning.
Inspect at grounded workstation. Minimize handling.
Store in original ESD-safe packaging. Minimize handling.
Deliver to work area in original ESD-safe packaging. Open packages only at
grounded workstation. Package subassemblies in static dissipative packaging.
Pack in static dissipative material if required. Replacement or optional
boards may require special attention.

Figure 10.64

Special care should be taken when breadboarding and evaluating ICs. The effects of
ESD damage can be cumulative, so repeated mishandling of a device can eventually
cause a failure. Inserting and removing ICs from a test socket, storing devices
during evaluation, and adding or removing external components on the breadboard
should all be done while observing proper ESD precautions. Again, if a device fails
during a prototype system development, repeated ESD stress may be the cause.

The key word to remember with respect to ESD is prevention. There is no way to
undo ESD damage, or to compensate for its effects.

ESD Models and Testing

Some applications have higher ESD sensitivity than others. ICs which are located
on a PC board surrounded by other circuits are generally much less susceptible to
ESD damage than circuits which must interface with other PC boards or the outside
world. These ICs are generally not specified or guaranteed to meet any particular
ESD specification (with the exception of MIL-STD-883 Method 3015 classified
devices). A good example of an ESD-sensitive interface is the RS-232 port on a
computer (see Figure 10.65). The RS-232 driver and receiver ICs are directly in the
firing line for voltage transients as well as ESD. In order to guarantee ESD
performance for such devices, the test methods and limits must be specified.
10.73

RS-232 PORT IS VERY SUSCEPTIBLE TO ESD
I I-O Transceiver Is Directly in the Firing Line for Transients - RS-232
Port Is Particularly Vulnerable
I I-O Port Is an Open Gateway in the Enclosure
I Harmonised Standards Are Now Mandatory Requirements in
European Community

Figure 10.65

A host of test waveforms and specifications have been developed to evaluate the
susceptibility of devices to ESD. The three most prominent of these waveforms
currently in use for semiconductor or discrete devices are: The Human Body Model
(HBM), the Machine Model (MM), and the Charged Device Model (CDM). Each of
these models represents a fundamentally different ESD event, consequently,
correlation between the test results for these models is minimal.

Since 1996, all electronic equipment sold to or within the European Community
must meet Electromechanical Compatibility (EMC) levels as defined in specification
IEC1000-4-x. This does not apply to individual ICs, but to the end equipment. These
standards are defined along with test methods in the various IEC1000 specifications
shown in Figure 10.66.

IEC1000-4-2 specifies compliance testing using two coupling methods, contact
discharge and air-gap discharge. Contact discharge calls for a direct connection to
the unit being tested. Air-gap discharge uses a higher test voltage, but does not
make direct contact with the unit under test. With air discharge, the discharge gun
is moved toward the unit under test, developing an arc across the air gap, hence the
term air discharge. This method is influenced by humidity, temperature, barometric
pressure, distance and rate of closure of the discharge gun. The contact-discharge
method, while less realistic, is more repeatable and is gaining acceptance in
preference to the air-gap method.

10.74

IEC 1000-4-x BASIC IMMUNITY STANDARDS
FOR ELECTRONIC EQUIPMENT (NOT ICs!)
I IEC1000-4 Electromagnetic Compatibility EMC
I IEC1000-4-1 Overview of Immunity Tests
I IEC1000-4-2 Electrostatic Discharge Immunity (ESD)
I IEC1000-4-3 Radiated Radio-Frequency Electromagnetic
Field Immunity
I IEC1000-4-4 Electrical Fast Transients (EFT)
I IEC1000-4-5 Lightening Surges
I IEC1000-4-6 Conducted Radio Frequency Disturbances
above 9kHz
I Compliance Marking:

Figure 10.66

Although very little energy is contained within an ESD pulse, the extremely fast
risetime coupled with high voltages can cause failures in unprotected ICs.
Catastrophic destruction can occur immediately as a result of arcing or heating.
Even if catastrophic failure does not occur immediately, the device may suffer from
parametric degradation, which may result in degraded performance. The
cumulative effects of continuous exposure can eventually lead to complete failure.

I-O lines are particularly vulnerable to ESD damage. Simply touching or plugging in
an I-O cable can result in a static discharge that can damage or completely destroy
the interface product connected to the I-O port (such as RS-232 line drivers and
receivers). Traditional ESD test methods such as MIL-STD-883B Method 3015.7 do
not fully test a product's susceptibility to this type of discharge. This test was
intended to test a product's susceptibility to ESD damage during handling. Each pin
is tested with respect to all other pins. There are some important differences
between the MIL-STD-883B Method 3015.7 test and the IEC test:

(1) The IEC test is much more stringent in terms of discharge energy. The peak
current injected is over four times greater.
(2) The current risetime is significantly faster in the IEC test.
(3) The IEC test is carried out while power is applied to the device.

10.75

It is possible that ESD discharge could induce latch-up in the device under test.
This test is therefore more representative of a real-world I-O discharge where the
equipment is operating normally with power applied. For maximum confidence,
however, both tests should be performed on interface devices, thus ensuring
maximum protection both during handling, and later, during field service.

A comparison of the test circuit values for the IEC1000-4-2 model versus the MIL-
STD-883B Method 3015.7 Human Body Model is shown in Figure 10.67, and the
ESD waveforms are compared in Figure 10.68.

MIL STD 883B METHOD 3015.7 HUMAN BODY MODEL
VERSUS IEC 1000-4-2 ESD TESTING
HIGH
VOLTAGE
GENERATOR
DEVICE
UNDER TEST
R1 R2
C1
ESD TEST METHOD
Human Body Model MIL STD 883B
Method 3015.7
IEC 1000-4-2
R2
1.5k
330
C1
100pF
150pF
NOTE: CONTACT DISCHARGE VOLTAGE SPEC FOR IEC 1000-4-2 IS 8kV

Figure 10.67

Suitable ESD-protection design measures are relatively easy to incorporate, and
most of the over-voltage protection methods previously discussed in this section will
help. Additional protection can be obtained by the addition of TransZorbs at
appropriate places in the system. For RS-232 and RS-485 line drivers and receivers,
the ADMXXX-E series is supplied with guaranteed 15kV (HBM) ESD specifications.

10.76
MIL-STD-883B, METHOD 3015.7 HUMAN BODY MODEL
AND IEC 1000-4-2 ESD WAVEFORMS
HUMAN BODY MODEL
MIL-STD-883B, METHOD 3015.7
IEC 1000-4-2
30ns 60ns
100%
0.1to 1 ns
90%
10%
Time
100%
90%
10%
Time
36.8%
I Voltage : 8 kV
I Peak Current :
N MIL-883B, Method 3015.7 HBM : 5 A
N IEC 1000-4-2 : 25 A
%
I
PEAK
%
I
PEAK
t
RL
t
DL

Figure 10.68

CUSTOMER DESIGN PRECAUTIONS FOR ICs WHICH
MUST OPERATE AT ESD-SUSCEPTIBLE INTERFACES
I Observe all Absolute Maximum Ratings on Data Sheet!
I Follow General Overvoltage Protection Recommendations
N Add Series Resistance to Limit Currents
N Add Zeners or Transient Voltage Supressors (TVS) TransZorbs
for Extra Protection (http://www.gensemi.com)
I Purchase ESD-Specified Digital Interface Devices Such as
N ADMXXX-E Series of RS-232 / RS-485 Drivers / Receivers
(MIL-883B, Method 3015.7: 15kV, IEC 1000-4-2: 8kV)
I Read AN-397, "Electrically Induced Damage to Standard Linear
Integrated Circuits: The Most Common Causes and the Associated
Fixes to Prevent Reocurrence," by Niall Lyne - Available from Analog
Devices, http://www.analog.com

Figure 10.69

10.77
REFERENCES ON ESD AND OVERVOLTAGE:

1. Amplifier Applications Guide, Section XI, pp. 1-10, Analog Devices,

2. Systems Applications Guide, Section 1, pp. 56-72, Analog Devices,

3. Linear Design Seminar, Section 1, pp. 19-22, Analog Devices,

4. ESD Prevention Manual, Analog Devices, Inc.

5. MIL-STD-883 Method 3015, Electrostatic Discharge Sensitivity
Classification. Available from Standardization Document Order Desk,
700 Robbins Ave., Building #4, Section D, Philadelphia, PA 19111-5094.

6. EIAJ ED-4701 Test Method C-111, Electrostatic Discharges. Available from
the Japan Electronics Bureau, 250 W 34th St., New York NY 10119, Attn.:
Tomoko.

7. ESD Association Standard S5.2 for Electrostatic Discharge (ESD) Sensitivity
Testing -Machine Model (MM)- Component Level. Available from the ESD
Association, Inc., 200 Liberty Plaza, Rome, NY 13440.

8. ESD Association Draft Standard DS5.3 for Electrostatic Discharge (ESD)
Sensitivity Testing - Charged Device Model (CDM) Component Testing.
Available from the ESD Association, Inc., 200 Liberty Plaza, Rome, NY
13440.

9. Niall Lyne, Electrical Overstress Damage to CMOS Converters, Application
Note AN-397, Analog Devices, 1995, http://www.analog.com.

10. How to Reliably Protect CMOS Circuits Against Power Supply
Overvoltaging, Application Note AN-311, Analog Devices,
http://www.analog.com

11. ADM3311E RS-232 Port Transceiver Data Sheet, Analog Devices, Inc.,
http://www.analog.com.

12. TransZorbs Available from General Semiconductor, Inc., 10 Melville
Park Road, Melville, NY, 11747-3113, 516-847-3000,
http://www.gensemi.com.
I NDEX
I n d ex-1
Su bject I n d ex
A
Aavid 5801, heat sink, 5.28
Absor pt ion, 10.47-49
AC induct ion mot or cont r ol, block diagr am,
6.18-19
AC power supply:
filt er ing, 10.34-36
noise filt er ing, 10.36
Acceler omet er , 1.2, 5.1, 5.26, 6.1, 6.19-23
applicat ions, 6.20
basic sensor unit , 6.19-20
DC acceler at ion measur ement , 6.19
int er nal signal condit ioning, 6.21
micr omachining, 6.20
t ilt measur ement , 6.21-22
Act ive sensor , 1.1-2
Act uat or , 1.3-4
AD210:
isolat ion amplifier :
t hr ee-por t , 3.54-55
applicat ions, 3.55-56
cir cuit , 3.54
key feat ur es, 3.55
AD260:
digit al isolat or , 10.55-57
key specificat ions, 10.57
schemat ic, 10.56
AD261:
digit al isolat or , 10.55-57
schemat ic, 10.56
AD420:
4-20mA DAC, 9.1-2
16-bit sigma-delt a DAC, 9.2
AD421:
loop-power ed 16-bit DAC, 9.2
smar t sensor , 9.2
AD524, in amp, ser ies-pr ot ect ion FETs,
3.48
AD524C, pr ecision in amp, per for mance,
3.47
AD549, BiFET op amp, low bias cur r ent
pr ecision, 5.6
AD588, pr ecision volt age r efer ence, 4.10
AD592:
cur r ent out put t emper at ur e sensor ,
7.21-22
specificat ions, 7.22
AD594, in amp, t ype J t her mocouple, 7.9-10
AD595, in amp, t ype K t her mocouple,
7.9-10
AD598, LVTD signal condit ioner , 6.3, 6.5
AD598 and AD698 Dat a Sheet , 6.24
AD620:
in amp, 2.7, 3.38-39, 3.42, 10.5
br idge signal condit ioning cir cuit ,
4.9-10
common mode choke, 10.42
composit e, per for mance summar y, 3.40
equivalent input cir cuit , over volt age,
10.61-62
er r or analysis, 3.45-46
schemat ic, 10.61-62
t hr ee op amp:
over volt age pr ot ect ion, 3.36
schemat ic, 3.36-37
single-supply, r ail-t o-r ail input , 3.39
Super bet a input , 3.36
AD620B:
br idge amplifier , er r or budget , t able, 3.46
pr ecision in amp, per for mance, 3.47
AD621, in amp, pin-pr ogr ammable, gain,
3.42
AD621B, pr ecision in amp, per for mance,
3.47
AD622, pr ecision in amp, per for mance, 3.47
AD623:
in amp, 2.7, 3.40-41, 3.46
dat a sheet , 3.40
single-supply, ar chit ect ur e, 3.41
AD623 and AD627 Inst r ument at ion
Amplifier
Dat a Sheet s, 3.58
AD623B, in amp, single-supply,
per for mance,
3.47
AD624C:
in amp, 3.47
pr ecision in amp, per for mance, 3.47
AD625C, pr ecision in amp, per for mance,
3.47
AD626:
in amp, 3.46
common mode volt age at t enuat ion, 3.23
AD626B, in amp, single-supply,
per for mance,
3.47
AD627:
in amp, 2.7, 3.34
ar chit ect ur e, 3.35
dat a sheet , 3.34
key specificat ions, 3.34-35
r ail-t o-r ail out put , 3.34
t wo op amp in-amp, 10.64
AD627B:
in amp:
I NDEX
I n d ex-2
CMR, 3.34
single-supply, per for mance, 3.47
AD645:
BiFET op amp, low bias cur r ent , 5.6
J FET amplifier , 3.15
AD688, st able volt age r efer ence, 3.9
AD698:
half-br idge LVDT, 6.5-6
LVDT signal condit ioner , 6.5-6
AD707:
op amp, bias-cur r ent compensat ed
bipolar , 3.6
pr ecision bipolar amplifier , noise, 3.51
pr ecision op amp, 2.16, 10.3
1/f cor ner fr equency, 3.11
CMR, 3.16
input volt age noise, 3.11
offset adjust ment , 3.5
PSR, 3.17-18
st abilit y, 3.4
AD743:
BiFET amplifier :
char act er ist ics, 5.29
low noise, 5.28-29
FET-input op amp, 3.11-12, 3.15
J FET input , 5.29-30
phot odiode pr eamplifier , 5.22
AD744:
J FET amplifier , 3.15
AD745:
BiFET amplifier :
char act er ist ics, 5.29-30
low noise, 5.28-29
FET-input op amp, 3.11-12, 3.15
J FET input , 5.29-30
op amp, high input impedance, 5.27-30
AD795:
BiFET op amp:
low bias cur r ent , 5.6-9
buffer amplifier , low input cur r ent , 5.30
DIP package, guar ding t echniques, 5.6,
5.8-9
guar ding t echniques, vir gin Teflon
insulat ion, 5.8, 5.10
pr eamplifier :
cir cuit per for mance summar y, 5.18-19
DC offset er r or s, cir cuit , 5.11
noise gain plot , 5.14
offset null adjust ment , 5.18
volt age and cur r ent noise spect r al
densit ies,
5.14-15
pr ecision BiFET op amp:
low input cur r ent , 5.30-31
pH pr obe buffer , 5.30-31
AD795K, pr eamplifier , t ot al out put offset
er r or ,
5.11
AD820:
op amp, single supply, 8.8-9
pr ecision op amp, single-supply,
per for mance
AD822:
in amp, composit e, per for mance
summar y, 3.40
pr ecision op amp:
J FET-input dual r ail-t o-r ail out put ,
3.38,
3.40
single-supply, per for mance
char act er ist ics,
3.27-28
AD823, phot odiode pr eamplifier , 5.21-25
AD824, pr ecision op amp, single-supply,
per for mance char act er ist ics, 3.27-28
AD843, phot odiode pr eamplifier , 5.22
AD845, phot odiode pr eamplifier , 5.22
AD974, 16-bit SAR ADC, 8.5
AD77XX family:
sigma-delt a ADCs, 7.11, 7.14-15, 8.22
equivalent input cir cuit s, 8.32
AD77XX-Ser ies Dat a Sheet s, 8.38
AD789X family, SAR ADC, single supply,
8.8
AD1879, 18-bit sigma-delt a ADC, 8.22
AD7710, sigma-delt a ADC, 8.23
AD7714, sigma-delt a ADC, 8.23, 9.2
AD7716:
quad sigma-delt a ADC, 8.32
funct ional diagr am, 8.33
AD7722, 16-bit ADC, 10.7
AD7730:
24-bit sigma-delt a ADC, 4.12
int er nal pr ogr ammable gain amplifier ,
4.12
load-cell applicat ion, 4.13
sigma-delt a ADC, 2.14, 8.23, 10.7
br idge applicat ion, schemat ic, 8.31
calibr at ion opt ions, 8.29-30
I NDEX
I n d ex-3
cir cuit , 8.26
ext er nal volt age r efer ence, 8.30
FASTSt ep mode, 8.28
filt er set t ling t ime, 8.29
high impedance input buffer , 8.31
int er nal pr ogr ammable digit al filt er ,
8.27
fr equency r esponse, 8.28
over sampling fr equency, 8.27
AD7730 Dat a Sheet , 2.19, 4.14
AD7731, sigma-delt a ADC, 8.23, 10.7
AD7750:
sigma-delt a ADC, 8.34-37
block diagr am, 8.35-36
power met er single-phase applicat ion,
diagr am, 8.37
AD7751, Ener gy Met er ing IC, 8.36
AD7816:
digit al t emper at ur e on-chip sensor ,
7.32-34
block diagr am, 7.33
AD7817:
7.32-34
AD7818:
7.32-34
AD7858:
12-bit SAR ADC, 8.5
cir cuit , 8.8-9
12-bit single-supply ADC, 8.14-15
int egr at ed IC dat a acquisit ion syst em,
8.14-15
AD7858L:
12-bit single-supply ADC, 8.14-15
int egr at ed IC dat a acquisit ion syst em,
8.14-15
AD7859:
12-bit SAR ADC, 8.5
cir cuit , 8.8-9
par allel out put device, key specificat ions,
8.15
AD7859L, par allel out put device, key
AD7890-10:
12-bit ADC, 8.8-9
diagr am, 8.9
t hin-film input at t enuat or , 10.63, 10.65
AD7892, 12-bit SAR ADC, 10.7
AD8531, op amp, r ail-t o-r ail input , 3.23
AD8551:
chopper -st abilized ADC, 2.16-17
noise, 3.51
AD8552:
noise, 3.51
AD8554:
noise, 3.51
AD9814, 14-bit ADC, analog fr ont end
solut ion,
5.37
AD9816:
12-bit ADC:
analog fr ont end solut ion, 5.37
char ge coupled device/cont act image
sensor pr ocessor , 5.37
AD22103:
r at iomet r ic volt age out put sensor , 7.22-23
AD22151:
linear magnet ic field sensor , 6.8
cir cuit , 6.9
AD22151 Dat a Sheet , 6.24
Adams, R.W., 8.38-39
ADC:
12-bit , t wo-st age pipelined, 8.6-7
digit al out put , Far aday shield, 10.14
fir st -or der sigma-delt a, diagr am, 8.18
high speed ar chit ect ur e, 8.2
high-r esolut ion, out put code hist ogr am,
8.23-24
input r ange wit hin supply volt age, input
pr ot ect ion, 10.64
mult iple sigma-delt a, in simult aneous
sampling, 8.33
on-chip t emper at ur e sensor , 7.32-34
SAR:
mult iplexed, filt er ing and t iming,
8.11-12
mult iplexed input s, 8.10-14
single-pole filt er set t ling, 8.13
single-supply, r esolut ion/conver sion
t ime
I NDEX
I n d ex-4
compar ison, 8.5
swit ched capacit or , 8.8
t iming, 8.6
second-or der sigma-delt a, diagr am,
8.20-21
sigma-delt a, 8.1-2, 8.16-37
high r esolut ion, low fr equency, 8.23-34
over sampling, 8.22
in power met er s, 8.34-37
signal condit ioning, 8.1-2, 8.16-37
signal condit ioning, 8.1-37
design issues, 8.1
high speed ar chit ect ur e, 8.2
successive appr oximat ion, 8.1-9
single-supply, t hin film r esist or input
at t enuat or , input pr ot ect ion, 10.65
subr anging, pipelined, 8.6-7
successive appr oximat ion, 8.1-8
basic diagr am, 8.3
SAR r eset , 8.2
SHA in hold, 8.2
t r acking, for r esolver -t o-digit al conver t er ,
6.14
ADG7XX family, swit ch/mult iplex, 8.12
ADG451, swit ch/mult iplex, 8.12
ADG465:
CMOS channel pr ot ect or , 10.65-67
ADG466:
over volt age and power supply
sequencing,
10.67
ADG467:
ADG508F, swit ch/mult iplex, 8.12
ADM1021:
micr opr ocessor t emper at ur e monit or ,
7.35-38
input signal condit ioning cir cuit s, 7.36
on-chip t emper at ur e sensor , 7.37
ADM3311E RS-232 Por t Tr ansceiver Dat a
Sheet , 10.77
ADMC300, 16-bit ADC syst em, 6.18-19
ADP1148:
synchr onous buck r egulat or , 10.28-31
cir cuit , 10.29
dr iving low dr opout r egulat or , 10.31
wavefor ms, 10.31
filt er ed out put , 10.30
out put wavefor m, 10.30
ADP3310:
low dr opout buck r egulat or , 10.30-31
dr iven by synchr onous buck r egulat or ,
10.31
wavefor ms, 10.31
ADS290:
int egr at ed r esolver -t o-digit al conver t er ,
6.14
ADT05, t her most at ic swit ch, 7.29-30
ADT14, quad set point cont r oller , 7.32
ADT22, pr ogr ammable set point cont r oller ,
7.32
ADT23, pr ogr ammable set point cont r oller ,
7.32
ADT45, absolut e volt age out put
t emper at ur e
sensor , 7.24-25
ADT50, absolut e volt age out put
t emper at ur e
sensor , 7.24-25
ADT70, RTD signal condit ioner , 7.14
ADuC810:
Micr oConver t er :
basic analog I/O funct ionalit y, 9.8
on-chip flash memor y, 9.9
on-chip micr ocont r oller , 9.9
ADuC812:
Micr oConver t er :
12-bit successive appr oximat ion ADC,
9.11
funct ional block diagr am, 9.12
per for mance specificat ions, 9.12-13
ADuC816:
Micr oConver t er :
funct ional block diagr am, 9.10
highest r esolut ion pr oduct , 9.10
per for mance specificat ions, 9.11
ADXL202, dual axis acceler omet er , 6.22-23
Air dischar ge, 10.68
Air -gap dischar ge, 10.73
Aluminum elect r olyt ic capacit or , 10.22-23
AMP01A, pr ecision in amp, per for mance,
3.47
AMP02, in amp, ser ies-pr ot ect ion FETs,
3.48
I NDEX
I n d ex-5
AMP02E, pr ecision in amp, per for mance,
3.47
AMP04E, in amp, single-supply,
per for mance,
3.47
Amplifier :
bipolar ver sus chopper , input volt age
noise,
3.51
chopper st abilized, 3.49-52
cr it ical par amet er s, signal condit ioning,
3.1-58
DC er r or budget analysis, 3.19
r esolut ion er r or , 3.19
t emper at ur e, 3.19
isolat ion, 3.52-56
noise model, 5.15-16
offset volt age, er r or sour ce, 2.16
select ion cr it er ia, 3.1-2
t ypes, 3.1
see also In amp; Op amp
Amplifier Applicat ions Guide (1992), 3.57,
10.57, 10.77
Analog fr ont end solut ion, for signal
pr ocessing
pr oblems, 5.36
Analog gr ound, 10.12-14
Analog-t o-digit al conver t er , see: ADC
Andr eas, D., 8.38
Aper t ur e jit t er , 10.16
ASI, indust r ial net wor k st andar d, 9.5
Aut o-focus device, 5.2
Aver age r eal power , 8.35
B
Baker , Bonnie, 10.20
Bandgap t emper at ur e sensor , 7.21
Bar code scanner , 5.2
Bar nes, Er ik, 5.40
Base-emit t er junct ion br eakdown, 10.59
Bell 202 Communicat ions St andar d, 9.2
Bias cur r ent , er r or sour ce, 2.16
Blood par t icle analyzer , 5.2
Bode plot , 5.12-13, 5.16, 5.20
Bolt zmann's const ant , 3.13, 5.15, 7.19
Bonded st r ain gage, 4.2
Boser , B., 8.38
Br idge:
AC, dr ive cir cuit , diagr am, 2.18
AC excit at ion, offset volt age
minimizat ion,
2.17
all-element var ying, 2.4, 2.6
six-lead assemblies, 2.13
amplifier , 2.8
consider at ions, 2.7
const ant cur r ent :
all-element var ying, 2.6
configur at ions, 2.6
single-element var ying, 2.6
sour ces, 2.5-6
t wo-element var ying, 2.6
const ant volt age:
all-element var ying, 2.4
linear , 2.4
configur at ions, 2.4
er r or , 2.4
single-element var ying, 2.4
t wo-element var ying, 2.4
dr iving, 2.11-18
er r or minimizing, r at iomet r ic t echnique,
2.14-15
four -wir e sensing, 2.13-14
Kelvin sensing, 2.13-14
linear izat ion met hods, 2.5
linear izing, 2.9-11
nonlinear it y, 2.5
offset er r or , sour ces, 2.16
out put , amplifying and linear izing, 2.7-11
out put amplifying, by in-amp, 2.7-8
out put volt age, linear it y er r or , 2.4
r emot e:
dr iving:
Kelvin sensing, 2.15
r at iomet r ic connect ion, 2.15
single-element var ying, t hr ee-wir e
connect ion, 2.13
r esist ance, null, 2.3
r esist ance measur ement , 2.3
sensit ivit y, 2.4
sensor applicat ions, 2.4
single-element var ying, 2.4, 2.6
op-amp, null, 2.9
out put , amplifying, 2.7-8
t wo-element var ying, 2.4, 2.6
Wheat st one, 2.2-3
wir ing r esist ance, effect s, 2.12
Br idge cir cuit , 1.3, 2.1-19
fundament als, 2.1
Br idge signal condit ioning cir cuit , 4.9-13
all-element var ying, 4.9-10
Br okaw cell, 7.20-21
Br okaw, Paul, 7.39, 9.17, 10.20, 10.58
Br yant , J ames, 3.1, 7.1, 8.1, 8.16 10.1,
10.7, 10.20,10.58, 10.68
Br yant , J ames M., 8.16
Buxt on, J oe, 2.19, 3.57, 8.1, 10.59
C
Cable:
I NDEX
I n d ex-6
coaxial, gr ounding, 10.53-54
"elect r ical lengt h", 10.51-52
shielded:
gr ounding, 10.53-54
r emot e passive sensor , 10.53
shielding, 10.51-54
gr ounding, 10.52
t wist ed pair , shielded, gr ound loops, 10.52
Cage jack, 10.8
CAN-Bus, indust r ial net wor k st andar d, 9.5
Capacit or , 10.22
equivalent cir cuit and pulse r esponse,
10.25
ESR degr adat ion wit h t emper at ur e, 10.24
finit e ESR, 10.24
impedance ver sus fr equency, 10.26
low ESL/ESR, 10.32
noise r egulat ion, 10.22
par asit ic element s, 10.25
shunt r esist ance, 10.25
t ypes, 10.22
Car d ent r y filt er , 10.28
CAT scanner , 5.2
CCD, see: char ge coupled device
Cer amic capacit or , 10.9, 10.22, 10.24
advant ages, 10.24
mult ilayer "chip caps",
bypassing/filt er ing,
10.24
Char ge coupled device, 5.1
CMOS fabr icat ion, 5.33
image pr ocessing, 5.31-38
kT/C noise, 5.33-35
linear ar r ays, 5.33
out put st age, 5.33-34
Char ged Device Model, ESD model, 10.73
Char pent ier , A., 8.38
Chemical sensor , 5.1
Chest nut , Bill, 9.1, 10.21
Choke, common mode, 10.41
Chop mode, 8.27
Chopper -st abilized amplifier , 3.49-52
ar chit ect ur e, 3.50
cir cuit , 3.49
input signal, 3.50
low fr equency 1/f noise, 3.51
nulling, 3.50
Chr ist ie, S.H., developer of Wheat st one
br idge,
2.2
Cir cuit :
br idge, 2.1-19
ESD-suscept ible int er faces, design
pr ecaut ions, 10.76
shielding, conduct ive enclosur es, 10.47
signal condit ioning, 1.3
Cir cuit boar d:
double-sided ver sus mult ilayer pr int ed,
10.9-10
gr ound planes, 10.18
layout guidelines, 10.18-19
mult icar d, mixed signal syst ems, 10.10-11
mult ilayer , 10.10
noise minimizat ion, 10.18
par t it ioning, 10.18
t r aces, t er minat ion, 10.44
t r ack impedance, calculat ion, 10.45
CIS, see: cont act image sensor
Clelland, Ian, 10.37
applicat ion, 10.66-67
cir cuit , 10.66
pr oper t ies, 10.65-66
CMRR:
definit ion, 3.16
offset er r or calculat ion, 3.17
out put offset volt age er r or , 3.16
Coaxial cable, gr ounding, 10.53-54
Code flicker , 8.25
Cold junct ion, 7.6
ice point r efer ence, 7.7
t emper at ur e sensor , 7.7
Columbia Resear ch Labs 2682 st r ain
sensor ,
4.10
Common mode r eject ion, see: CMR
Common mode r eject ion r at io, see: CMRR
Compatibility of Analog S ignals for
Electronic
Industrial Process Instruments, 9.17
Conduct ion, 10.59
Connelly, J .A., 10.20
Const ant an wir e, 4.2
Cont act dischar ge, 10.68, 10.73
Cont act image sensor , 5.1
applicat ions, 5.35
image pr ocessing, 5.31-38
wavefor ms, 5.36
Cont r ol loop, 4-20mA, 9.1-3
Cor r elat ed double sampling, t o r educe kT/C
noise, 5.34-36
Count s, Lew, 2.19, 3.57
Coussens, P.J .M., 6.24
Cr osst alk, 8.10
Cr yst al Oscillat or s: MF Elect r onics, 10.20
D
DAC:
3-bit swit ched capacit or , t r ack (sample)
mode,
8.4
4-20mA, 9.2-3
I NDEX
I n d ex-7
Dar k cur r ent , phot odiode, 5.3
Dat a acquisit ion syst em, on chip, 8.14
Dat t or r o, J ., 8.38
Decimat ion, 8.16, 8.18
Decoupling:
cir cuit point s, 10.15
mixed-signal ICs, 10.12-14
Del Signor e, B.P., 8.38
Designing for EMC (Workshop Notes), 10.57
Designing a Watt-Hour Energy Meter
Based on
the AD7750, 8.39
Device-Net , indust r ial net wor k st andar d,
9.5
DIGI-KEY, 10.38
Digit al camer a, imaging syst em, gener ic,
5.32
Digit al cur r ent , in analog r et ur n pat h,
10.8-9
Digit al filt er ing, 8.16
Digit al gr ound, 10.12-14
Digit al-t o-analog conver t er , see: DAC
DIP packaging, 5.6, 5.8-9, 10.8
guar ding, PCB layout , 5.9
Doebelin, Er nest O., 4.14
Dost al, J ., 2.19, 3.57
E
E-Ser ies LVDT Dat a Sheet , 6.24
Ear ly effect s, 7.19
ECG, isolat ion amplifier s, 3.52
Eckbauer , F., 8.38
EDN' s Designer' s Guide to Electromagnetic
Compatibility, 10.57
EEG, isolat ion amplifier s, 3.52
EEPROM, 8.29
Effect ive input noise, 8.23
Effect ive number of bit s, see: ENOB
Effect ive r esolut ion, 8.17
definit ion, 8.24
ENOB, 8.24
EIAJ ED-4701 Test Method C-111,
Electrostatic
Discharges, 10.77
Eichhoff Elect r onics, Inc., 10.38
80C51, micr ocont r oller , 7.28
Elect r ic mot or , t ypes, oper at ions, 6.17-18
Elect r ocar diogr aph, isolat ion amplifier s,
3.52
Elect r oencephalogr aph, isolat ion
amplifier s, 3.52
Elect r olyt ic capacit or , 10.22
swit ching, 10.23
Elect r omagnet ic int er fer ence, see: EMI
Elect r ost at ic dischar ge, see: ESD
EMC Design Wor kshop Not es, 10.37
EMC Test & Design, 10.58
EMG, isolat ion amplifier s, 3.52
EMI:
maximum r adiat ion t hr ough opening,
10.50
pat h, 10.21
r ecept or , 10.21
sour ce, 10.21
Ener gy Met er ing IC, 8.36
Engelhar dt , E., 8.38
ENOB, 8.17-18
effect ive r esolut ion, 8.24
Equivalent ser ies r esist ance, see: ESR
ESD, 10.68-76
cat ast r ophic dest r uct ion, fr om ar cing or
heat ing, 10.74
damage, 10.69
examples, 10.68
gener at ion, 10.68
models and t est ing, 10.72-76
pr ot ect ion plan, 10.72
t est ing st andar ds, compar ison, 10.74
see also Elect r ost at ic dischar ge
ES D Association Draft S tandard DS 5.3 for
Electrostatic Discharge (ES D) S ensitivity
Testing--Charged Device Model(CDM)--
Component Testing, 10.77
ES D Association S tandard S 5.2 for
Electrostatic
Discharge (ES D)S ensitivity
Testing--Machine
Model (MM)--Component Level, 10.77
ESD Pr event ion Manual, 10.77
ESD-sensit ive device:
assembling wit h ot her component s, 10.71
labeling, 10.70
packaging and handling, 10.69-71
wor kbench, 10.69, 10.71
Et her net , indust r ial net wor k st andar d, 9.5
F
Fair -Rit e Linear Fer r it es Cat alog, 10.37
Far aday shield, 10.35
ADC digit al out put , 10.14
FASTSt ep mode, 8.28
Fat igue monit or , br idge signal condit ioning
cir cuit , 4.9-10
Fer guson, P. J r ., 8.39
Fer guson, P.F. J r ., 8.38
Fer r it e:
bead, 10.9
impedance, 10.27
leaded, 10.27
impedance, calculat ion;, 10.27-28
power supply filt er s, 10.25
I NDEX
I n d ex-8
sur face mount bead, 10.27
Fiber opt ic r eceiver , 5.2
Fieldbuses: Look Before You Leap, 9.17
Film capacit or , 10.22-24
limit ing fr equencies, 10.24
st acked, 10.24
Filt er :
analog, quant izat ion noise, 8.20
car d ent r y, 10.28
common and differ ent ial mode, 10.41
localized high fr equency, for decoupling
t o
gr ound plane, 10.33
swit ching supply:
layout /const r uct ion guidelines, 10.33-34
summar y, 10.32
Fisher , J ., 8.38
Flash cont r ol, 5.2
FLASH Memor y, 1.4
Flat ness, 8.10
Flet t , F.P., 6.24
The Flow and Level Handbook, Vol. 29,
4.14
Flow measur ement :
bending vane wit h st r ain gage, 4.9
pit ot t ube, 4.7-8
pr essur e sensor s, 4.7-9
vent ur i effect , 4.7-8
Foundat ion Fieldbus, indust r ial net wor k
st andar d, 9.5
Four -wir e sensing, 2.13-14
Fr aden, J acob, 4.14
Fr anco, Ser gio, 2.19, 3.57
Fr edr ickson, Thomas M., 3.57, 5.39
Fr eeman, Wes, 10.59, 10.68
Fr equency shift keying, 9.2
Fu, Dennis, 6.24
G
Ganesan, A., 8.39
Gelbach, Her man, 10.58
Ger ber file, 10.19
Goodenough, Fr ank, 6.25
Gr aeme, J er ald, 5.40, 10.20
Gr aham, Mar t in, 10.20
Gr ant , Doug, 10.6
Gr ay code, used in opt ical encoder , 6.10
Gr ay, Paul R., 3.57
Gr ound:
digit al noise, 10.13-14
separ at ing analog and digit al, 10.11-12
Gr ound pin:
IC, 10.8
mult iple, 10.18-19
Gr ound plane, 10.7-9
backplane, 10.10
digit al, 10.14
islands, 10.9
mandat or y on cir cuit boar ds, 10.10
separ at ion of analog and digit al, 10.12
Gr ound scr een, 10.11-12
Gr ounding:
cir cuit , pr ecaut ions, 10.28-29
cir cuit point s, 10.15
mixed-signal ICs, 10.12-14
mixed-signal syst ems, 10.7-20
H
Hageman, St eve, 10.37
Hall effect magnet ic sensor , 6.1, 6.7-9
diagr am, 6.7
as r ot at ion sensor , 6.8
Hall volt age, 6.7
Handbook of Chemist r y and Physics, 7.39
Har dwar e, design t echniques, 10.1-77
Har r ingt on, M.B., 6.25
Har r is, St even, 8.39
Har r old, Dave, 9.17
HART:
indust r ial net wor k st andar d, 9.4-5
int elligent r emot e t r ansmit t er :
block diagr am, 9.3
using AD421 loop-power ed 4-20mA
DAC,
9.3
HART pr ot ocol, 9.2-4
Hauser , Max W., 8.39
Headlight dimmer , 5.2
Heise, B., 8.38
High impedance char ge out put sensor ,
5.26-31
High Speed Design Techniques (1996), 3.57
High-speed digit al signal pr ocessor , 6.18
High-speed r esolver -t o-digit al conver t er ,
6.18
How to Reliably Protect CMOS Circuits
Against
Power S upply Overvoltaging, 10.77
HP5082-4204 PIN Phot odiode, 5.22-23
Human Body Model, ESD model, 10.73
Humidit y monit or , 5.1
Hydr ophone, 5.1, 5.26, 5.28
Hyst er esis, pr ogr ammed, 7.31
I
I-O lines, ESD vulner abilit y, 10.74
IC, mixed-signal, decoupling and
gr ounding,
10.12-14
Ice point junct ion, 7.6
IEC1000-4-2:
compar ison wit h MIL-STD Human Body
I NDEX
I n d ex-9
Model, 10.75
wavefor ms, 10.76
Eur opean Communit y ESD st andar d,
t est ing,
10.73
IEC1000-4-x, Eur opean Communit y ESD
st andar ds, t able, 10.74
IEEE 1451.2, sensor int er face st andar d,
9.4-6
Imaging syst em, light -sensing element ,
5.32
iMEMS, Analog Devices' acceler omet er ,
6.19
Impedance, and noise sour ces, 3.14
In amp, 3.30-48
as amplifier , in single-element var ying
br idge,
2.8
br idge amplifier , er r or budget analysis,
3.45-46
cir cuit diagr am, 3.30
CMR, 3.30, 3.43
composit e:
single-supply:
per for mance summar y, 3.40
r ail-t o-r ail out put , schemat ic, 3.39
configur at ions, 3.31-41
DC er r or sour ces, 3.42-44
gain, 3.42
er r or specificat ions, 3.42
nonlinear it y, 3.42
RTI, summar y, 3.44
definit ion, 3.30
dual-supply, r ail-t o-r ail op amp gain
st age,
3.38
ext er nal volt age pr ot ect ion cir cuit , 10.63
input bias cur r ent s, offset er r or s, 3.43
input over volt age, 3.48
input over volt age pr ot ect ion, 3.48
int er nal feedback r esist or net wor k, 3.30
noise sour ces, 3.44-45
gain, 3.45
model, 3.44-45
t ot al out put noise calculat ion, 3.44
offset volt age model, 3.43
per for mance t ables, 3.46-47
pr ecision:
common mode RFI, 10.39
fer r it e bead filt er , 10.41
filt er ing, 10.40
against EMI/RFI, 10.42
per for mance, t able, 3.47
PSR, 3.43
RTI CMR, 3.43
single-supply, per for mance, t able, 3.47
t hr ee op amp, 3.35-36
cir cuit , 3.36
CMR, 3.36
int er nal node volt ages, 3.37
single-supply oper at ion, 3.37
r est r ict ions, 3.37
t ot al input offset volt age, 3.43
t ot al out put offset er r or , 3.43
t wo op amp:
cir cuit , 3.32
CMR, 3.33
disadvant age, 3.32-33
input pr ot ect ion, 10.64
single supply:
high gain, 3.33-34
low gain, 3.33
zer o-volt common mode input volt ages,
r est r ict ion, 3.34
Indir ect field-or ient ed cont r ol, 6.18
Induct osyn, 6.1, 6.15-17
component s, 6.15
diagr am, 6.16
linear posit ion measur ement , 6.15
oper at ion similar t o r esolver , 6.16
r ot ar y, 6.17
Indust r ial net wor k st andar d, list ing, 9.5
Indust r ial pr ocess cont r ol, sensor
applicat ion,
1.3-4
Input bias cur r ent :
models, 3.5-7
offset er r or s, 3.5-6
pr ecision op amp, PNP or NPN st andar d
bipolar input st age, 3.6
Input offset volt age:
air flow effect s, 3.4
change wit h t ime, 3.4
cont r ol by device select ion, 3.4
long-t er m st abilit y, 3.4
measur ement , 3.3-5
mechanical boar d layout , 3.3
RTI, 3.3
models, 3.5-7
diagr am, 3.6
par asit ic t her mocouple junct ions, 3.3
pr ecision amplifier er r or sour ce, 3.2
t emper at ur e effect s, 3.4
Input over volt age, 10.60
Input -r efer r ed noise, 8.23
Inst ant aneous power , 8.34-35
Inst ant aneous r eal power , 8.34-36
Inst r ument at ion amplifier , see: In amp
Int er bus-S, indust r ial net wor k st andar d,
9.5
Int er fer ence:
impedance, 10.47
sour ces, 10.47
An Int r oduct ion t o t he Imaging CCD Ar r ay,
I NDEX
I n d ex-10
5.39
Isolat ed gat e bipolar t r ansist or , 6.18
Isolat ion, as for m of shielding, 10.55
Isolat ion amplifier , 3.52-56
applicat ions, 3.53-54
input cir cuit , 3.53
linear it y, 3.53
t hr ee-por t , 3.54
J
J ant zi, S.A., 8.38
J it t er , sampling clock, 10.16
J ohnson noise, 3.13, 3.14, 5.15, 8.23
fr om feedfor war d r esist or , 5.17
op amp, 3.11, 3.13, 3.14
J ohnson, Howar d W., 10.20
J ung, Walt , 3.1, 7.1, 10.1, 10.21, 10.37,
10.39,
10.58
J ung, Walt er G., 3.57
K
Kaufman, M., 2.19, 3.57
Keil, t hir d-par t y t ools for Micr oConver t er ,
9.15
Kelvin connect ion, RTD, 7.14
Kelvin sensing, 2.13-14
Ker r idge, Br ian, 10.6
Kest er , Walt , 1.1, 2.1, 2.19, 3.1, 4.1, 4.14,
5.1,
5.39, 6.1, 7.1, 7.39, 8.1, 9.1, 10.1, 10.7,
10.20, 10.21, 10.39, 10.59, 10.68
Ket t le, P., 6.25
King, Gr ayson, 9.1, 9.4
Kit chin, Char les, 2.19, 3.57, 5.1, 10.39
Koch, R., 8.38
kT/C noise, 8.23
r educt ion, by cor r elat ed double sampling,
5.34-36
L
Laser pr int er , 5.2
Law of Int er mediat e Met als, 7.6
Lee, Wai Laing, 8.38
Lee, W.L., 8.38
Light met er , 5.2
Light -sensing element , 5.32
Linear Design Seminar (1994), 10.77
Linear Design Seminar (1995), 3.57, 8.38
The Linear Variable Differential
Transformer,
by Her man Schaevit z, in 1946, 6.1-2
Linear var iable differ ent ial t r ansfor mer ,
see:
LVDT
Load cell, sensor , all-element var ying
br idge,
2.5
Load-cell amplifier , cir cuit , 4.10-11
Logic:
cir cuit separ at ion, 10.45
families, cir cuit boar d t er minat ion, 10.44
high speed, 10.44-46
slowing, EMI/RFI minimizat ion, 10.47
Lonwor k, indust r ial net wor k st andar d, 9.5
Lucey, D.J ., 6.25
LVDT, 1.2, 6.1-7
advant ages, 6.2
impr oved, signal pr ocessing out put , 6.3-4
linear dist ance measur ement ,
applicat ions, 6.1
measur ement r anges, 6.2
posit ion-t o-elect r ical sensor , 6.2
pr ecision r ect ifier , 6.3-4
Lyne, Niall, 6.25, 10.77
M
Machine Model, ESD model, 10.73
MacKenzie, I. Scot t , 9.17
Mar sh, Dick, 10.37
Mat suya, Y., 8.38-39
Melsa, J ames L., 3.57, 5.39
Met alink, t hir d-par t y t ools for
Micr oConver t er ,
9.15
Meyer , Rober t G., 3.57
Micr oConver t er :
12-bit volt age out put DAC, 9.7-8
based on 8052 cor e, 9.12
design suppor t mat r ix, 9.13
fut ur e development s, 9.15
pr oduct r oadmap, 9.16
QuickSt ar t development kit , 9.14
smar t sensor , 1.6, 9.6-8
pr imar y funct ions, 9.7-8
t hir d-par t y t ools, 9.15
Web sit e, 9.14
MicroConverter Technology Backgrounder,
9.17
Micr opr ocessor :
supply volt age and t emper at ur e, cr it ical
par amet er s, 7.35
t emper at ur e monit or ing, 7.35-38
Micr ost r ain, 4.2
Migr at ion, 10.59
MIL-STD-883 Met hod 3015, for ESD
sensit ivit y, 10.72, 10.74
MIL-S TD-883 Method 3015, Electrostatic
Discharge S ensitivity Classification,
10.77
I NDEX
I n d ex-11
MIL-STD-883 Met hod 3015.7:
Human Body Model:
compar ison wit h IEC, 10.75
wavefor ms, 10.76
Mixed Signal Design Seminar (1991), 8.38
Mixed signal syst em, gr ounding, 10.7-20
Mixed-signal gr ounding, t echniques, 10.16
Modulat ion, 8.10
Modulat or :
sigma-delt a:
linear ized model, 8.19
quant izat ion noise shaping, 8.21
Mor r ison, Ralph, 10.20, 10.57, 10.58
MOSFET:
Kelvin sensing, 2.17
N-Channel, 2.17
P-Channel, 2.17
Mot chenbacher , C.D., 10.20
Mot or cont r ol cur r ent sensing, isolat ion
amplifier , cir cuit , 3.56
Mult iplexed SAR ADC, filt er ing and
t iming,
8.11-12
Mult iplexer :
analog, diagr am, 8.11
Mult iplexing, 8.10
Mult ipoint gr ound, diagr am, 10.11
Muncy, Neil, 10.58
Mur r ay, Aengus, 6.25
MUX, see also Mult iplex
N
N-Channel MOSFET swit ch, 8.10
Nash, Eamon, 3.58
Negat ive t emper at ur e coefficient , see: NTC
Net wor k:
indust r ial, diagr am, 9.4
st andar d, HART, 9.2-4
Nichr ome wir e, 4.2
Noise:
RMS, equat ion, 3.12
swit cher , high fr equency, t ools, 10.21-22
whit e, 3.11-12
Noise shaping, 8.19
Noise-fr ee code r esolut ion, definit ion,
8.24-25
Nonlinear it y:
closed loop gain:
calculat ions, 3.10
op amp, 3.8
definit ion, 3.42
open loop gain, calculat ions, 3.10
Null measur ement , feedback syst em, 2.3
Nyquist band, 8.17
Nyquist cr it er ion, 8.18
O
Offset er r or s, AC excit at ion, offset volt age
minimizat ion, 2.17
Offset r efer r ed t o input , see: RTI
O'Gr ady, Alber t , 9.17
OMEGA Temperature Measurement
Handbook,
7.39
On-chip pr ogr ammable-gain amplifier , see:
PGA
OP07:
bipolar op amp:
ult r a-low offset volt age, 5.5
open-loop gain, 3.21
volt age noise, 3.12
OP27:
bipolar op amp:
bias-cur r ent compensat ed, 5.29-30
low volt age noise, 3.12, 3.14-15
OP42, phot odiode pr eamplifier , 5.22
OP97, super -bet a bipolar op amp, bias
cur r ent
compensat ion, 5.5
OP113:
pr ecision op amp:
high open-loop gain, 3.21
3.27-28
OP177:
pr ecision bipolar op amp, 2.18, 10.3
bias-cur r ent compensat ed bipolar , 3.6
CMR, 3.16
gain nonlinear it y, 3.10
noise, 3.51
offset adjust ment , 3.5
PSR, 3.17-18
st abilit y, 3.4
OP177A, op amp, r oom t emper at ur e er r or
budget analysis, 3.19
OP181, pr ecision op amp, single-supply,
OP184:
pr ecision op amp:
r ail-t o-r ail input , 3.24
3.27-28
OP191:
pr ecision op amp:
common mode cr ossover t hr eshold, 3.24
I NDEX
I n d ex-12
3.27-28
OP213:
pr ecision op amp, high open-loop gain,
3.21
t wo op amp in-amp, 4.11
3.27-28, 3.37
OP250, op amp, r ail-t o-r ail input , 3.23
OP279, op amp, common mode cr ossover
t hr eshold, 3.24
OP282, op amp, P-channel J FET input
pair ,
3.23
OP284:
pr ecision op amp:
3.27-28, 3.37
OP291:
pr ecision op amp:
3.27-28, 3.37
OP413:
pr ecision op amp:
high open-loop gain, 3.21
3.27-28
OP450, op amp, r ail-t o-r ail input , 3.23
OP482, op amp, P-channel J FET input
pair ,
3.23
OP484:
pr ecision op amp:
3.27-28
OP491:
pr ecision op amp:
3.27-28
Op amp:
1/f noise, 3.11
as amplifier , in single-element var ying
br idge,
2.8
bias compensat ed, low volt age noise, 3.14
BiFET:
input st age, cir cuit , 5.6
bipolar :
bias-cur r ent compensat ed, 3.6
br eakdown volt age, 10.59
chopper st abilized, 3.1
no 1/f noise, 3.51
noise r educt ion, 3.12
CMRR, definit ion, 3.16
cur r ent noise, 3.11
DC open loop gain nonlinear it y,
measur ement ,
3.8-9
decoupling t echniques, 3.18
input bias cur r ent compensat ed, diagr am,
3.7
J FET, specificat ions, 3.15
J FET ver sus bipolar , 5.29-30
sour ce r esist ance, effect s on noise and
offset
volt age, 5.30
low-fr equency CMR, 3.31
noise, 3.11-15
J ohnson, volt age, 3.13
low fr equency, 3.11
model, 3.13
noise model, 5.15-16
non-inver t ing:
gain var iat ion wit h t emper at ur e, 10.1
r esist or t emper at ur e coefficient
mismat ches,
10.1
noninver t ing mode, 3.16-17
offset adjust ment pins, diagr am, 3.5
offset dr ift wit h t emper at ur e, 3.5
over volt age:
conduct ion, 10.59
pr ot ect ion cir cuit , 10.61
pr ecision:
I NDEX
I n d ex-13
CMR, 3.16-18
DC open loop gain nonlinear it y,
3.7-10
measur ement , 3.8-9
input bias cur r ent , models, 3.5-7
input offset volt age, 3.2-5
models, 3.5-7
noise, 3.11-15
PSR, 3.16-18
CMR, 3.16
gain nonlinear it y, plot , 3.10
gain uncer t aint y, 3.7-8
key per for mance specificat ions, 3.2
noise gain, 3.7
offset null, 3.4
open loop gain, 3.7
PNP or NPN bipolar input st age, input
bias
cur r ent s, 3.6
PSR, 3.17-18
PSRR, 3.17
fr equency dependent , 3.17
r amp gener at or out put , 3.9
fr equency, 3.9
r esist ance, J ohnson noise, 3.11
r esist or J ohnson noise, 5.15
single supply, 3.20-29
advant ages, 3.20
design t r adeoffs, 3.20
gain accur acy, 3.21
input bias cur r ent , CMR, 3.24
input st ages, 3.22-25
N-channel J FET, 3.22-23
offset volt age, 3.25
over volt age, 3.22
par allel NPN and PNP, 3.21
t r ansient r esponse, 3.25
out put st ages, 3.25-28
"almost " r ail-t o-r ail, 3.27
asymmet r y, 3.25
bipolar pr ocesses, 3.25
CMOS FETs, 3.26
complement ar y common-
emit t er /common-sour ce, 3.26-27
per for mance char act er ist ics, summar y,
3.27-28
pr ocess t echnologies, 3.28-29
BiMOS or CBCMOS use, 3.29
J FET use, 3.29
summar y, 3.28-29
PSR, 3.17
r ail-t o-r ail, 3.20
gr ound r efer ence, 3.21
input st age:
design, 3.24
long-t ailed pair s, 3.23-24
out put st ages, 3.22
select ion cr it er ia, 3.27-28
SNR, 3.22
per for mance, 3.21
volt age noise incr ease, 3.21
subt r act or , 3.31
t emper at ur e, offset dr ift , 3.5
t ypes, null capabilit y, 3.5
volt age noise, 3.11
whit e noise, 3.11
Opt ical encoder :
absolut e, expense, 6.10
diagr ams, 6.10
disadvant ages, 6.9-10
incr ement al, 6.9-10
posit ion measur ement , 6.9-10
use of Gr ay code, 6.10
Opt ical r ot at ional encoder , 6.1
Opt oelect r onics Dat a Book, 5.39
Opt oisolat or , 3.53, 10.55
Or ganic semiconduct or elect r olyt ic
capacit or ,
10.22-23
OS-CON Aluminum Elect r olyt ic Capacit or
93/94 Technical Book, 10.37
OS-CON elect r olyt ic capacit or , 10.22-23
Ot t , Henr y, 10.20, 10.37, 10.57
Out put r ipple, 10.32
Over sampling, 8.16-17
r at io, 8.17
Over volt age:
pr ot ect ion, 10.59-67
Schot t ky diode, 10.60-61
P
P-Channel MOSFET swit ch, 8.10
P-NET, indust r ial net wor k st andar d, 9.5
Pallas-Ar eny, Ramon, 2.19, 4.14, 5.39, 6.24,
7.39
Par asit ic t her mocouples, er r or sour ces, 2.16
Par zefall, F., 8.38
Passive sensor , 1.1-2
Pat t avina, J effr ey S., 10.20
Per manent magnet synchr onous mot or ,
6.18
pH monit or , 5.1
pH pr obe buffer amplifier , 5.30-31
Phase jit t er , 10.16-17
Phot odiode 1991 Cat alog, 5.39
Phot odiode, 1.2
amplifier :
low noise:
cir cuit s, 5.27-28
sour ce impedance balancing, 5.27
applicat ions, 5.2
I NDEX
I n d ex-14
cir cuit , leakage pat hs, 5.7-8
cur r ent pr opor t ional t o illuminat ion, 5.1-2
cur r ent -t o-volt age conver t er , 5.4-5
SNR, 5.5
equivalent cir cuit , 5.1-3
shunt r esist ance, 5.3
high speed cur r ent -t o-volt age conver t er :
compensat ion, 5.20-25
input capacit ance compensat ion, 5.20
high speed pr eamplifier :
dar k cur r ent compensat ion, cir cuit , 5.24
design, 5.22-24
dynamic r ange, 5.22
equivalent noise bandwidt h, 5.24
noise analysis, 5.24-25
out put noise analysis, equivalent
cir cuit ,
5.25
out put volt age, 5.23
t ot al RMS noise, 5.25
modes of oper at ion, cir cuit s, 5.3
op amp, cur r ent -t o-volt age conver t er ,
5.4-5
par asit ic leakage, 5.7-8
phot oconduct ive mode, 5.3
phot ovolt aic mode, 5.3
shor t cir cuit cur r ent , light int ensit y, 5.4
pr eamplifier , 5.1
Bode plot , 5.12-13
cir cuit noise:
gain ver sus fr equency, 5.12-13
summar y, 5.17
cir cuit per for mance summar y, 5.18-19
cir cuit t r adeoffs, 5.19
closed loop bandwidt h, 5.13-14
design, 5.1-19
design, bandwidt h, and st abilit y,
5.12-14
Bode plot , 5.12-13
cir cuit noise gain ver sus fr equency,
5.12-13
FET-input op amp, compar isons, 5.22
input bias cur r ent , funct ion of
t emper at ur e,
5.10-11
Bode plot , 5.16
J ohnson noise fr om feedfor war d
r esist or ,
5.17
J ohnson noise of r esist or in
non-inver t ing
input , 5.17
noise analysis, 5.14-18
noise gain plot , 5.13-14
noise r educt ion, via out put filt er ing,
5.18
non-inver t ing input cur r ent noise, 5.17
offset null adjust ment , 5.18
offset volt age and dr ift analysis, 5.10-11
offset volt age er r or s, summar y, 5.10-11
shunt r esist ance, funct ion of
t emper at ur e,
5.10-11
signal bandwidt h, 5.13-14
r ever se bias, 5.3
dar k cur r ent , 5.3
t her moelect r ic volt age, sour ce of input
offset
volt age, 5.12
wideband conver t er , op amp select ion,
5.21-22
zer o bias, 5.3
Piezoelect r ic, 1.2
sensor amplifier , 5.28
Piezoelect r ic sensor , 5.26
Piezoelect r ic t r ansducer :
amplifier , lower bias cur r ent , 5.28
displacement t ype, 4.4
out put volt age, 4.4-5
Piezor esist ance, semiconduct or st r ain gage,
4.4
Pin socket , 10.8
Pit ot t ube, flow measur ement , 4.7-8
Plug and play, 9.5-6
Polyest er capacit or , 10.22-23
Posit ion sensor , 5.2
Power :
aver age r eal, 8.35
inst ant aneous, 8.34-35
inst ant aneous r eal, 8.34-35
measur ement basics, 8.35
Power met er , single-phase applicat ion,
8.36-37
Power plane, 10.7-9
Power supply:
AC, filt er ing, 10.34-36
commer cial EMI filt er , 10.34-35
EMI gener at ion, 10.34
filt er , fer r it es, 10.25
localized high fr equency, filt er ing,
10.32-34
noise r educt ion and filt er ing, 10.21-38
separ at e for analog and digit al cir cuit s,
10.15
swit ching, 10.21
analog r eady, 10.21
dr awbacks, 10.21
filt er s, 10.21
Power supply r eject ion, see: PSR
Power supply r eject ion r at io, see: PSRR
Pr act ical Analog Design Techniques (1996),
3.57
I NDEX
I n d ex-15
Pr act ical Design Techniques for Power and
Ther mal Management , 10.38
Pr ecision load-cell amplifier , 4.11-12
single-supply, 4.12-13
cir cuit , 4.13
Pr ecision Resist or Co., Inc., 5.40
PT146, 5.30
Pr essur e sensor :
r esist ance, 2.1
t r ansducer s, 4.7
The Pr essur e, St r ain, and For ce Handbook,
Vol.
29, 4.14
Pr oduct -t o-Fr equency Conver t er , 8.34, 8.36
Pr ofibus, indust r ial net wor k st andar d, 9.5
Pr ogr ammable-gain amplifier , see: PGA
Pr oximit y det ect or , 6.1
PT146, Pr ecision Resist or Co., 5.30
Pulse Engineer ing, Inc., 10.43
Q
Quant izat ion er r or , 8.17
Quant izat ion noise, 8.17-18
Quant izat ion noise shaping, 8.16
R
Radiofr equency int er fer ence, see: RFI
Ramp gener at or , fr equency, 3.9
RCD Component s, Inc., 10.6
REF195, br idge dr ive, 4.11
Reflect ion, 10.47-49
Relat ive humidit y sensor , r esist ance, 2.1
Rempfer , William C., 10.20
Resist ance:
measur ement :
br idge, 2.2-3
indir ect , 2.2
Resist ance t emper at ur e device, see: RTD
Resist ive st r ain gage, 4.1
Resist or :
er r or , high accur acy syst em, 10.1-6
J ohnson noise, 3.13, 5.15
model, wit h t her mocouples, 10.2-3
or ient at ion, er r or minimizat ion, 10.3-4
self-heat ing, gain var iat ion wit h input
level,
10.2
Resolver , 6.10-15
br ushless, 6.11
diagr am, 6.11
r ot at ing t r ansfor mer , 6.11
RFI r ect ificat ion:
pr event ion, 10.39-43
Rich, A., 10.58
RMS noise:
equat ion, 3.12
gaussian dist r ibut ion, 8.24
Rober ge, J .K., 3.57
Roche, P.J ., 6.25
Rot ar y var iable differ ent ial t r ansfor mer ,
6.1
LVDT var iant , 6.7
RS-232 por t , ESD-sensit ive, 10.72-73, 10.75
RS-485 por t , ESD-sensit ive, 10.75
RTD, 1.1-3, 2.1-2
demodulat es AC er r or signal, 6.13
diagr am, 6.12-13
four -r esist or br idge cir cuit , 7.13-14
measur ement er r or s, 7.12-13
passive t emper at ur e sensor , 7.11-15
plat inum, 2.2
int er faced t o high r esolut ion ADC,
cir cuit ,
7.15
r esist ance, 2.1
r esist ance ver sus Seebeck coefficient , 7.12
single-element var ying br idge, 2.4-5
t emper at ur e sensor , 7.2, 7.11-15
t r acking, 6.14
S
Sample-and-hold, see: SHA
Sampling clock:
gr ound planes, 10.17
gr ounding and decoupling, 10.15
jit t er , 10.16
SNR, 10.16
Sauer wald, Mar k, 10.20
Scannell, J .R., 6.25
Scanner , imaging syst em, gener ic, 5.32
Schaevit z E100 LVTD:
diagr am, 6.2
Schaevit z, Her man, 6.24
Schmidt , Er nest D.D., 6.24
Schot t ky diode, 3.48, 10.12, 10.60-61,
10.63-64
Schult z, Donald G., 3.57, 5.39
Scot t -T t r ansfor mer , in synchr o, 6.12
Seebeck coefficient :
and RTD, 7.12
t emper at ur e var iat ion, 7.3-4
Self-gener at ing sensor , 1.1-2
Semiconduct or :
st r ain gage, 4.4
advant ages, 4.4
piezor esist ance, 4.4
advant ages, 7.19
basic r elat ionships, 7.19-20
Sensor :
I NDEX
I n d ex-16
act ive, 1.1-2
char ge coupled device, 5.1
char ge out put , 5.1
classificat ion, 1.1, 1.3
definit ion, 1.1
digit al int er face, st andar dizat ion, 1.5
elect r ical char act er , 1.3
ext er nal act ive cir cuit r y, 1.1
high impedance, 5.1-38
char ge amplifier , 5.26
cir cuit s, 5.27-28
char ge out put , 5.26-31
int er faced wit h net wor k, 9.4-16
out put , 1.2
over view, 1.2
passive, 1.1-2
examples, 1.1
piezoelect r ic, 5.1
popular , r esist ances, 2.1
posit ion and mot ion, 6.1-23
pr ocess cont r ol syst em applicat ion, 1.3-4
r emot e r esist ive br idge, er r or s, 2.12
r esist ive element s, 2.1
self-gener at ing, 1.1-2
smar t , 9.1-16
t emper at ur e, 7.1-38
applicat ions, 7.1
see also Temper at ur e sensor
t ypes, 1.3
uses, 1.1
Set point cont r oller , t emper at ur e sensor ,
7.29-32
Sheingold, Dan, 2.19, 3.57, 4.14, 5.39, 6.24,
7.39, 8.39
Shielded cable, gr ounding, 10.53-54
Shielding:
absor pt ion, 10.47-49
effect iveness, calculat ion, 10.50
magnet ic fields, loss, 10.48
mat er ials, conduct ivit y and per meabilit y,
summar y, 10.50
r eflect ion, 10.47-48
r eview, 10.47-58
Siemens Opt oisolat or Pr oduct s, 10.58
Sigma-delt a ADC, 24 bit s, int er nal PGA, for
br idges, 2.14
Signal condit ioning:
amplifier s, 3.1-58
cir cuit , 1.3
Signal-t o-noise r at io, see: SNR
Silicon Det ect or Cor por at ion, 5.39
Silicon Det ect or Par t Number
SD-020-12-001,
5.4
Silicon sensor , 1.2
68HC11, micr ocont r oller , 7.28
Slat t er y, B., 10.57
Smar t sensor , 9.1-16
4-20mA loop power ed, 9.2
applicat ions, 1.5
basic element s, 1.5
Smar t Tr ansducer Int er face Module, smar t
sensor , 9.5-6
Smit h, Lewis, 3.57, 5.39
Smoke det ect or , 5.1
Snelgr ove, M., 8.38
SNR ver sus over sampling r at io, 8.22
SO-8 packaging, 7.27
Sockolov, St eve, 10.6
Sodini, C.G., 8.38
SOIC packaging, 5.6, 5.8-9, 5.19, 8.26
guar ding, PCB layout , 5.9
SOT-23-3 packaging, t emper at ur e sensor s,
7.24-26
St andar d, indust r ial net wor k, list ing, 9.5
St ar gr ound, 10.10-11
STIM, smar t sensor , 9.5-6
St out , D., 2.19, 3.57
St r ain gage, 1.2, 4.1-9
bonded, 4.2-3
diagr am, 4.3
br idge cir cuit , 4.9-10
compar isons, 4.4
flow devices, 4.1
foil-t ype, 4.2-3
for ce measur ement , 4.5
fullscale var iat ion, 2.12
gas and liquid pr essur e measur ement s,
4.6
load cell, 4.1, 4.5-6
pr ecision amplifier , 4.11
low impedance, 4.5
met al foil, diagr am, 4.3
piezoelect r ic t r ansducer s, 4.1
pr ecision, sensor amplifier , 4.10
pr essur e devices, 4.1
r esist ance, 2.1
r esist ive, 4.1
semiconduct or , 4.4
unbonded, 4.1-2
Successive appr oximat ion r egist er , see: SAR
Swanson, E.J ., 8.38
Swit ch, CMOS analog, basic, 8.10
Swit ching r egulat or , exper iment , 10.28-32
Synchr o, 6.10-15
diagr am, 6.11
r ot at ing t r ansfor mer , 6.11
Scot t -T t r ansfor mer , 6.12
t hr ee st at or coils, 6.11
Synchr o and r esolver , 6.1
Syst em, definit ion, 1.1
Syst em Applicat ions Guide (1993), 8.38,
10.43,
10.77
I NDEX
I n d ex-17
Syst em Applicat ions Guide (1994), 3.57,
10.57
T
Tant alum elect r olyt ic capacit or , 10.22-23
Tant alum Elect r olyt ic Capacit or SPICE
Models,
10.38
Tant alum Elect r olyt ic and Cer amic
Capacit or
Families, 10.37
TEDS, in micr ocont r oller , 9.5
Temper at ur e monit or ing, micr opr ocessor ,
7.35-38
Temper at ur e sensor , 7.1-38
applicat ions, 7.1
bandgap, 7.21
cur r ent and volt age out put , 7.21-25
digit al out put , 7.26-29
dir ect digit izat ion, by ADCs, 7.2
EMI/RFI effect s, 7.25
nonlinear t r ansfer funct ions, 7.1
RTD, 7.2, 7.11-15
semiconduct or , 7.2, 7.19-34
set point cont r oller , 7.29-32
t her mist or , 7.2, 7.16-19
t her mocouple, 7.2-11
t her most at ic swit ch, 7.29-32
t ypes, 7.2
Tesla, Nikola, 6.17
Ther mal EMF, t her mocouple effect , 10.2
Ther mist or , 1.2
amplifier , linear ized, 7.19
definit ion, 7.16
fr agilit y, 7.17
NTC, 7.16
linear izat ion, 7.18
r esist ance char act er ist ics, 7.16
t emper at ur e coefficient , 7.17
r esist ance, 2.1
sensit ivit y, 7.17
single-element var ying br idge, 2.4-5
Ther mocouple, 1.2
basic pr inciples, 7.5-6
cold-junct ion compensat ion, 7.2-11
effect , t her mal EMF, 10.2
er r or , high accur acy syst em, 10.1-6
isot her mal block, 7.8
par asit ic, cir cuit , 10.5
r efer ence cold junct ion, 7.3-4
r efer ence junct ion, 7.6
Seebeck coefficient and t emper at ur e,
7.3-4
t her moelect r ic emf, 7.5
t ype J :
Seebeck coefficient , 7.5
sensit ivit y, 7.3-4
t ype K, 7.5
Seebeck coefficient , 7.8
t ype S, 7.5
t ypes, 7.2-3
volt age gener at ion, 7.6
volt age-t emper at ur e cur ves, 7.3-4
Ther moelect r ic emf, t her mocouple, 7.5
Ther most at ic swit ch, t emper at ur e sensor ,
7.29-32
Ther most r eam-t ype heat er /cooler , amplifier
t emper at ur e cont r oller , 3.4
TII, in sensor , 9.5
TMP01:
pr ogr ammable set point cont r oller , 7.31-32
key feat ur es, 7.32
TMP03:
digit al out put sensor , 7.26-29
diagr am, 7.27
out put for mat , 7.27
t her mal monit or ing, 7.29
TMP04:
digit al out put sensor , 7.26-29
diagr am, 7.27
high power micr opr ocessor monit or ing,
7.29
out put for mat , 7.27
t her mal monit or ing, 7.29
micr ocont r oller int er facing, 7.28
TMP17:
cur r ent out put t emper at ur e sensor ,
7.21-22
TMP35:
absolut e volt age out put t emper at ur e
sensor ,
7.23
volt age out put sensor , 7.8-9, 7.11
TMP36, absolut e volt age out put
t emper at ur e
sensor , 7.23
TMP37, absolut e volt age out put
t emper at ur e
sensor , 7.23
TO-92 packaging, 7.27
TO-99 packaging, 5.6, 5.12
Tr ansducer , 1.2
Tr ansducer Elect r onic Dat a Sheet , in
micr ocont r oller , 9.5
Tr ansducer Independent Int er face, in
sensor , 9.5
Tr ansfor mer , best common-mode power line
isolat ion, 10.35
Tr ansient Volt age Suppr esser , 3.48, 10.63
Tr ansZor b, 10.63, 10.75
I NDEX
I n d ex-18
Tr ansZor bs Available fr om Gener al
Semiconduct or , Inc., 10.77
Tr avis, Bill, 6.24
Tr iboelect r ic effect , 10.68
Tr iet ley, Har r y L., 4.14, 6.24
TSSOP packaging, 7.27, 8.26
TVS, see: Tr ansient Volt age Suppr esser
Twilight det ect or , 5.2
Two op amp in amp, cir cuit , 3.32
Type 5MC Met allized Polycar bonat e
Capacit or ,
10.37
Type 5250 and 6000-101K chokes, 10.38
Type EXCEL leaded fer r it e bead EMI filt er ,
and
t ype EXC L leadless fer r it e bead, 10.37
Type HFQ Aluminum Elect r olyt ic
Capacit or
and Type V St acked Polyest er Film
Capacit or ,
10.37
U-V
Unbonded st r ain gage, 4.1-2
wir e, 4.2
Univer sal Ser ial Bus, indust r ial net wor k
st andar d, 9.5
USB, indust r ial net wor k st andar d, 9.5
Vect or AC induct ion mot or cont r ol, 6.17-19
Vect or cont r ol, 6.18
Vent ur i effect , flow measur ement , 4.7-8
VLSI mixed-signal pr ocessing, 8.14
W-Z
Webst er , J ohn G., 2.19, 4.14, 5.39, 6.24,
7.39
Weigh-scale load cell, r esist ance, 2.1
Welland, D.R., 8.38
Wheat st one br idge, 2.2-3
cir cuit , 2.3
Williams, J im, 7.39
Wong, J ames, 7.39, 10.6
Wooley, Br uce, 8.38
Wor ldFIP, indust r ial net wor k st andar d, 9.5
Wur cer , Scot t , 5.1, 10.6
Wynne, J ., 10.57
Zener diode, 10.63
I NDEX
I n d ex-19
An a log Devi ces
P a r t s I n d ex
A
AD210, 3.54-56
AD260, 10.55-57
AD261, 10.55-57
AD2S90, 6.14-15
AD420, 9.1-2
AD421, 9.2-3
AD524, 3.48
AD524C, 3.47
AD549, 5.6, 5.8
AD588, 4.10-11
AD592, 7.21-22
AD592CN, 7.21
AD594, 7.9
AD595, 7.9
AD598, 6.3, 6.5
AD620, 2.7, 3.36-40, 3.42, 3.45-46,
3.55-56,
4.9-11, 10.5, 10.41-42, 10.61-62
AD620B, 3.46-47
AD621, 3.42
AD621B, 3.47
AD622, 3.47
AD623, 2.7, 3.40-41, 3.46
AD623B, 3.47
AD624C, 3.42
AD625C, 3.47
AD626, 3.23, 3.46
AD626B, 3.47
AD627, 2.7, 3.34-35, 3.46, 10.64
AD627B, 3.34, 3.47
AD645, 3.15, 5.6
AD688, 3.9
AD698, 6.5-6
AD707, 2.16, 3.4, 3.5, 3.6, 3.11, 3.16-18,
3.51,
10.3
AD743, 3.11, 3.14, 3.15, 5.22, 5.28-29
AD744, 3.15, 5.22
AD745, 3.11, 3.14, 5.22, 5.27-30, 5.28-29
AD795, 5.6-9, 5.22
AD795K, 5.11, 5.18
AD820, 3.27-28, 5.22, 8.8-9
AD822, 3.27-28, 3.38, 3.40
AD823, 5.21-25
AD824, 3.27-28
AD843, 5.22
AD845, 5.22
AD974, 8.5, 8.8
AD976, 8.8
AD977, 8.8
AD77XX family, 7.11, 7.14-15, 8.22, 8.25,
8.31-32
AD789X family, 8.8
AD1555, 8.23
AD1556, 8.23
AD1879, 8.22
AD7472, 8.5
AD7670, 8.5
AD7705, 8.23
AD7706, 8.23
AD7710, 8.23
AD7711, 8.23
AD7712, 8.23
AD7713, 8.23
AD7714, 8.23, 9.2
AD7715, 8.23, 9.2
AD7716, 8.32-34
AD7722, 10.7
AD7730, 2.14-15, 2.17, 4.12-13, 8.23, 8.25-31,
10.7
AD7731, 8.23, 10.7
AD7750, 8.34-37
AD7751, 8.36
AD7816, 7.32-34
AD7817, 7.32-34
AD7818, 7.32-34
AD7856, 8.5
AD7857, 8.5
AD7858, 8.5, 8.14-15
AD7858L, 8.14-15
AD7859, 8.5, 8.15
AD7859L, 8.15
AD7887, 8.5
AD7888, 8.5
AD7890-10, 8.8-9, 10.63, 10.65
AD7891, 8.5
AD7892, 10.7
AD8531, 3.23
AD8532, 3.23
AD8534, 3.23
AD8551, 2.16, 3.51-52
AD8552, 2.16, 3.51-52
AD8554, 2.16, 3.51-52
AD9814, 5.37
AD9816, 5.37-38
AD22103, 7.22-23
AD22151, 6.8-9
ADG7XX family, 8.12
ADG451, 8.12
ADG452, 8.12
ADG453, 8.12
ADG465, 10.65-67
ADG466, 10.65-67
I NDEX
I n d ex-20
ADG467, 10.65-67
ADG508F, 8.12
ADG509F, 8.12
ADG527F, 8.12
ADMXXX-E, 10.75-76
ADM1021, 7.35-38
ADMC300, 6.18-19
ADMC330, 6.18-19
ADMC331, 6.18-19
ADP1148, 10.28-31
ADP3310, 10.30-31
ADT05, 7.29-30
ADT14, 7.32
ADT22, 7.32
ADT23, 7.32
ADT45, 7.24-25
ADT50, 7.24-25
ADT70, 7.14-15
ADT71, 7.14
ADT701, 7.14
ADuC810, 9.8-9, 9.15-16
ADuC812, 9.8, 9.11-13, 9.15-16
ADuC816, 9.8-11, 9.15-16
ADXL05, 6.23
ADXL150, 6.23
ADXL190, 6.23
ADXL202, 6.22-23
ADXL210, 6.23
ADXL250, 6.23
AMP01A, 3.47
AMP02, 3.48
AMP02E, 3.47
AMP04E, 3.47
M
Micr oConver t er , 1.4, 1.6, 9.6-8
O
OP07, 3.12, 3.15, 3.21, 5.5
OP27, 3.12, 3.14-15, 5.29-30
OP42, 5.22
OP97, 5.5
OP113, 3.21, 3.27-28
OP177, 2.16, 3.4-6, 3.10-11, 3.16-18, 3.51,
4.9-11, 10.3
OP177A, 3.3, 3.19
OP181, 3.27-28
OP184, 3.24, 3.27-28
OP191, 3.24, 3.27-28
OP193, 3.27-28, 7.9
OP196, 3.27-28
OP213, 3.21, 3.27-28, 3.37, 4.11-12
OP250, 3.23
OP279, 3.24
OP281, 3.27-28
OP282, 3.23
OP284, 3.24, 3.27-28, 3.37
OP291, 3.24, 3.27-28, 3.37
OP293, 3.27-28
OP296, 3.27-28
OP413, 3.21, 3.27-28
OP450, 3.23
OP481, 3.27-28
OP482, 3.23
OP484, 3.24, 3.27-28
OP491, 3.24, 3.27-28
OP493, 3.27-28
OP496, 3.27-28
R
REF195, 4.11-12
T
TMP01, 7.31-32
TMP03, 7.26-29
TMP04, 7.26-29
TMP17, 7.21-22
TMP35, 7.8-9, 7.11, 7.23
TMP36, 7.23
TMP37, 7.23
TMP17F, 7.21

Analog Devices - Practical Design Techniques For Sensor Signal Conditioning

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Analog Devices - Practical Design Techniques For Sensor Signal Conditioning

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PRACTICAL DESIGN TECHNIQUES

FOR SENSOR SIGNAL CONDITIONING

(or 10G) ar e ideal for use as hydr ophone amplifier s.

THERMOCOUPLE DIFFERENTIAL EMF AT LEAD JUNCTIONS

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