IP Integration and SoC Sign-off for Power, Noise and Reliability

Presented by:

Apache Design Solutions, Inc. Low-Power Webinar Series 2011

2011 Apache Design Solutions

Apache Design Solutions

Exclusive Focus on Power
Sign-off solution for all iSuppli Top-20 semiconductor companies Multiple products expanding RTL/SoC, analog, IC package and system

Industry Recognition
EDN Innovation of the Year Awards
2003 (winner), 2005 (finalist), 2007 (winner), 2009 (finalist), 2010 (winner)

One of the fastest growing technology companies

Deloitte fast50, 2008; Deloitte fast500, 2009

2011 Apache Design Solutions

Apache Addresses Power and Noise Challenges

Manage power budget gap Ensure power delivery integrity

Power (mW)

10x 6x Power Budget

PCB, Package

2010

2015

2020

Mitigate power-induced noise

2011 Apache Design Solutions

Apaches Comprehensive Power Analysis & Optimization Solutions

Architecture Intellectual Property System-on-Chip Package System (PCB)

Power Budgeting
Ultra-low-power Methodology

Power Delivery Integrity

IP Integration, SoC Sign-off

PowerInduced Noise Immunity

Chip-Package-System Convergence

2011 Apache Design Solutions

Design Integration Trends

Integration
IP Multi-VDD Memories Power Gates I/Os Clock Gating DDR3+ Multi-Core GHz+

Low-power

High-speed

GPIO High Speed IO GPIO GPU (VDD G) CPU CORE (VDDC)

OMAP5:
~ 2GHz

Analo g IO

GPIO

SNAPDRAGON:
~ 2.5GHz

Analo g/RF

Analog

Memory/Cache (VDDM) GPIO

2011 Apache Design Solutions

Impact of Increasing Design Integration

Performance Noise Coupling Functionality

ESD Reliability EM

2011 Apache Design Solutions

Noise Coupling Scenarios

Core Noise Core I/O Core Analog

PLL
noise source guard ring
Scenario 3 Scenario 2 Scenario 1

victim

Multi-core switching Power gate turn-on/off

I/O / core SSO High-speed digital Irregular bump / package Insufficient isolation

2011 Apache Design Solutions

Noise Coupling Pathways

Power Delivery Network (PDN) transmission: shared VSS, package coupling Analog: PDN + substrate Digital: Zext noise attack victims generate noise
n+ n+ p+ p+ n+ n+

inject noise via taps, wells, bulk terminals p-well p-bulk

isolation with package Z

couple substrate noise to victim devices

substrate transmission: around, through isolation

2011 Apache Design Solutions

Impact of Design Trends on Noise Coupling

Multiple voltage islands
100+ VDD, 100+ VSS domains in one chip No re-distribution or plane based sharing as in 1V/1G Cannot over-design as in one homogenous n/w

Power gating
Disrupts continuity of PDN Transition modeling (power up, down, sleep) Over-design has multiple costs

2011 Apache Design Solutions

Impact of Technology Trends on Noise Coupling

ITRS, Trends in technology scaling

Source: Mezhiba et al. Scaling Trends of On-Chip Power Distribution Noise

Higher drive strength devices di/dt

Higher impact of inductive noise Ldi/dt

But noise margin continues to reduce

Reduced FMAX Functionality failures Over-design requirements

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2011 Apache Design Solutions

Impact of Technology Trends on Chip Reliability

Smaller wires, faster devices Increasing temperature gradient

2011 Apache Design Solutions

Lower oxide / junction breakdown voltages Wire / Via breakdown

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Impact of Design Integration on Chip Reliability

(ESD)
Multiple voltage domains Each needing protection Isolated core domains No I/O ring protection Cross-domain impact Multiple failure scenarios
GPIO GPU (VDDG) GPIO High Speed IO GPIO

CPU CORE (VDDC)

Analog IO

Analog/RF (AVDD) Analog IO

Memory/Cache (VDDM) GPIO

ESD protection schemes CANNOT be completely reused from one design to another 12

2011 Apache Design Solutions

Next Generation Design Challenges

Looking to 28/22nm Migration Highly integrated SoC designs
IP coming from different teams/vendors 3D stacked die designs

Increasing impact of power/ground noise

Package / on-die L / substrate coupling Shrinking noise margin

Impact on chip reliability

Power and signal line electro-migration ESD reliability

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2011 Apache Design Solutions

Apaches Physical Analysis Flow

TOTEM Analog / IP / Macro

IP Noise Budgeting:

SoC Level Simulation REDHAWK

System Level Analysis SENTINEL

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2011 Apache Design Solutions

RLCK CPM S-parameter

Macro Model

Voltage drop EM ESD

Apaches Physical Analysis Coverage

Technology
nxtgrd iRCx

Design Data
Layout (GDS/DEF) Package

Library Data

Constraints

IP Validation

Connectivity

ESD

Signal EM

Power

IR, EM

DvD
Functional, Test VCD, VectorLess

Low-Power
Clock, power gating LDO, back-bias

Die / Pkg Optimization

Die / Pkg Sign-off

Impact on Timing

Die Model Creation

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2011 Apache Design Solutions

Custom Design Validation Using Totem

Power Noise

Closest power pad Traced power pad

Layout View Path Tracing

Missing VIA3

Missing VIA2

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2011 Apache Design Solutions

Custom Design Validation Using Totem

Analog Power/Signal EM

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2011 Apache Design Solutions

Custom Design Validation Using Totem

CDM Discharge Modeling
Built-in extraction engine
On-die RLC, package RLCK/S-parameter Inclusion of substrate RC network

Analysis Flow
Set-up and load design Extract P/G RLC, Substrate n/w Package netlist Simulation

Proprietary modeling methodology

High-voltage modeling Clamp snap-back profile X

Spice-accurate simulation technology

Customized simulation engine Transistor-level capacitance modeling

Layout based debugging GUI

Cross probing, what-if analysis Devices failure reporting

See:

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2011 Apache Design Solutions

Custom Design Validation Using Totem

IP Model Creation for SoC
Memory/IP Designers SoC/Chip Integrators

IP data / Boundary constraints

Model Created

Full-chip data

Totem

IP Power Model
Electrical + Physical Embedded constraints IP Protection

RedHawk

IP/Memory EM/IR/DvD Sign-off IP boundary Condition Sign-off

Full-chip EM/DvD Sign-off IP boundary Condition Sign-off

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2011 Apache Design Solutions

RedHawk: Industry Standard for SoC Sign-off

Capacity Analysis Accuracy

Multi-billion transistors Hierarchical modeling Package inclusion

Functional / Scan / IR Low-power Power / Signal EM

Against silicon 28/22nm extraction Pico-second resolution

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2011 Apache Design Solutions

SoC Validation Using RedHawk

Power Noise Analysis
High drop from SSO (clock buffer, memory, I/O) Package / PCB parasitic impact MTCMOS off-state leakage, power-up/down Clock gating transitions Test-mode, ATPG, BIST, shift Simultaneous switching of large number of registers

Hot-spot

Low-power analysis

Test-mode validation

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2011 Apache Design Solutions

SoC EM Validation Using RedHawk

Full-chip power and signal EM Simultaneous multi-domain Static for average EM Dynamic for RMS and Peak Flexible query and reporting
Signal EM Power EM

Built-in rules DB query for user configurable rule-set

Support for advanced EM rules

Length / width Blech Temperature, topology, direction

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2011 Apache Design Solutions

SoC ESD Validation Using RedHawk

Pad / Clamp Layout Connectivity Wire / Via Current Density

Signal to Power(S2P) Ground to Signal(G2S) Power to Ground(P2G)

Current Density Violation Map

(a)

Current density violations

(b) Routing congestion, narrow wires

Domain Crossing Checks Signal to Ground(S2G)

D1-D4 to Power Clamp D5-D6 to Power Clamp

(c)

Device Stress due to voltage buildup

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2011 Apache Design Solutions

SoC Validation for Mixed Signal Design

Substrate Noise Coupling
Device Level

Threshold Voltage modulation

Digital Core

IN

OUT

Circuit Level
Digital Core PLL Memories
PLL/Analog block

Functionality / Performance Issues in Analog & RF Circuits Preventing Integration of Sensitive Circuits

System Level

Check/sign-off full-chip noise

Plan/analyze isolation structures

Check noise impact: jitter, spurs, etc.

CPU analog
noise source Guard-ring

PLL
victim

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2011 Apache Design Solutions

Typical Design Issues Identified

Microprocessor design
Cell row with high drop

Networking Design
Failure from high SSO

Low-Power Microprocessor
Failure from ramp-up of cores

IVdd of first power-up block

Missing vias in cell row

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2011 Apache Design Solutions

What is Chip Power Model (CPM)?

Chip on-die Power Grid RLC

Apache

Transistor current/cap/ESR Open SPICE netlist format

Multi-domain, distributed model DC to multi-GHz validity Advanced chip excitation modes Silicon correlated

Package/Board Model

System Houses

ASIC Vendors
Chip Power Model Apache Ecosystem

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2011 Apache Design Solutions

Chip-Package-System (CPS) Convergence

Chip-Aware Package/PCB Analysis
Package / PCB Design

Chip/IP Design

Chip Power Model

Prototype

Selection, Planning

Design

Package Design System Sign-off

Sign-off

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2011 Apache Design Solutions

RedHawk and Totem Integrated Platform Analysis Coverage

Dynamic Power Integrity Substrate Noise Impact Reliability EM / ESD Layout-based Analysis Model Creation

Power Grid Prototyping Impact on Timing Low-Power Dynamic Root Cause Identification Signal & Power EM

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2011 Apache Design Solutions

Summary
SoCs with several cross-domain challenges on power and reliability
Multiple IP integration Low-power design techniques

Decreasing noise and reliability margins requiring analysis based sign-off

High-speed design demands Technology scaling on EM and ESD

Need for a robust and integrated platform for IP and SoC cross validation
Totem (IP analysis and modeling platform) Redhawk (SoC analysis platform)

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2011 Apache Design Solutions