A Fold-Back Current-Limit Circuit with Load-Insensitive Quiescent Current for CMOS Low Dropout Regulator

Jianping Guo and Ka Nang Leung

Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong. E-mail: {jpguo, knleung}@ee.cuhk.edu.hk Abstract A fold-back current-limit circuit, with loadinsensitive quiescent current characteristic for CMOS low dropout regulator (LDO), is proposed in this paper. This method has been designed in 0.35 m CMOS technology and verified by Hspice simulation. The quiescent current of the LDO is 5.7 A at 100-mA load condition. It is only 2.2% more than it in no-load condition, 5.58 A. The maximum current limit is set to be 197 mA, and the short-current limit is 77 mA. Thus, the power consumption can be saved up to 61% at the short-circuit condition, which also decreases the risk of damaging the power transistor. Moreover, the thermal protection can be simplified and the LDO will be more reliable. I. INTRODUCTION obviously and cannot be fabricated in some standard CMOS technologies. In Section II, several conventional current-limit technologies are reviewed, and then the proposed method will be introduced in detail with the principle analysis and schematic description in Section III. The simulation results based on the proposed circuit are presented in Section IV. Finally, the conclusion is given in part V. II. CONVENTIONAL CURRENT-LIMIT CIRCUIT

The demand for low-voltage low dropout regulators (LDO) is increasing due to the growing demand for portable electronics. The use of LDO is mainly due to better load transient response, less noise, simpler and lower cost than the switching regulator counterparts [1]-[3]. The current-limit circuit is used in power-management ICs to save the power consumption, protect the load and make the power management IC itself work in safe and stable operation. Constant and fold-back current limit are two mostly used methods as the current limit function in the LDO design [4]. There are many published papers focus on current-limit circuit design [5]-[7], but they have some limitations. In [5], a single process and temperature dependent resistor is used to sense the current, which leads to inaccurate current-limit value under process and temperature variations. Moreover, the low dropout performance cannot be achieved, and the power loss is higher. With the parallelconnected MOSFET to sense the current in [6], the disadvantage in [5] can be overcome, but the quiescent current of the chip is proportional to the output current, which also wastes energy. A novel method proposed in [7], can solve the problem of the process and temperature variations to an integrated resistor, and the dependency of the quiescent current to the output current can be improved lightly. But a depletion-mode MOSFET is used, which increases the cost
This work was supported by the Research Grant Council of Hong Kong SAR Government under project no. CUHK413206.

There are two popular current sensing techniques to sense the output current in the CMOS LDO. One method is directly connecting a resistor series with the power transistor [5] and the current flow through the transistor can be detected by the voltage across the resistor, a simplified CMOS LDO with this current-limit structure is shown in Fig. 1. Another method is using a small sized transistor with the same gate and source connections with the power transistor [6]. Thus, the drain current of the sense transistor is proportional to the output current. Fig. 2 shows a simplified current-limit circuit with the second current sensing technique. For the first approach, it is obvious that it is not suitable to the low dropout design since the series resistor causes large voltage drop and so more energy is wasted in this structure, especially in the heavy load condition. Moreover, the resistance should be small and precision for accurate current sensing, but the integrated resistance is very sensitive with the process and temperature variations, which leads to the inaccurate current-limit value. The second method is more power efficient, but one problem is that the sensing current is proportional to the output current, and that implies that the quiescent current is much higher in the heavy load condition. Due to the huge dissipation of the power transistor in the current-limit status, especially in the short-circuit condition, the thermal management and the package of the chip should be more restricted, so that both the volume and cost will be increased. Fold-back current limit, different from the constant current limit mentioned above due to its lower current-limit threshold when VOUT is decreased to be smaller some

978-1-4244-3828-0/09/$25.00 2009 IEEE

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VIN
VCL VREF MS EA VSNS CLA RSNS VOUT RF1 VFB RF2
Fig. 1. Simplfied CMOS LDO with current-limit circuit proposed in [5].

MP

CLA: Current Limit Amplifier

RESR RLOAD COUT

GND

Fig. 3. CMOS LDO with proposed current-limit circuit.

VIN

VOUT

VSNS Vb1 RTH

Vbn

IN

VCL

Vbp
Fig. 2. Simplfied CMOS LDO with current-limit circuit proposed in [6].

IP RTL Vb2 VSNS Vb3

threshold [3], is used to decreased the power dissipation of power transistor in the heavy load condition, especially in the short-circuit condition.

VOUT

III.

PROPOSED METHOD

GND
Fig. 4. Current-limit amplifier with rail-to-rail input stage.

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic for CMOS LDO, is proposed in this paper. A CMOS LDO with this current-limit circuit is shown in Fig. 3. A sense MOSFET, MS, which has the same source, gate and bulk connection with the power transistor MP, is connected to VOUT through a sense resistor RSNS. The output current can be sensed by MS, and the drain potential of MS is nearly same as VOUT due to the very little voltage drop across RSNS, which increases the sensing accuracy effectively. The current-limit amplifier (CLA), the schematic of which is shown in Fig. 4, is an unbalanced rail-to-rail operation amplifier, and both the maximum output current-limit

threshold and short-circuit current-limit threshold can be defined easily in this structure. The size ratio of MS to MP is set to 1 : K (K is usually several thousands and is 1000 in this paper), so that the voltage across RSNS is

VRSNS =

1 I OUT RSNS . K

(1)

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The CLA can be simplified as a comparator for understanding the working principle more easily. There are two thresholds in CLA, the value of which are

VTH =
and

1 I N RTH 2

In the extremely high load situation, i.e., short circuit condition, VOUT is so small that it is over the limitation of the ICMR of PMOS input pairs, which can lead to abnormal operation. So, level shifting should be adopted to make sure both input stages can work properly as analyzed above. The resistors RSNS, RTH and RTL should be made by the same type of material and well-matched so that the process and temperature variations can be minimized and the currentlimit threshold can be accurate with the precision bias current, which can be shown from (4) and (8). In this paper, negative temperature coefficient high-resistive poly resistors are used to achieve good match and small layout area, the resistance of which is highest at worst speed (ws) corner and lowest at worst power (wp) corner. IV. SIMULATION RESULTS

(2)

VTL =

1 I P RTL , 2

(3)

respectively. When the load current is small, that means VRSNS is less than VTH, so that the VCL is pulled up to high voltage and the current-limit loop can not affect the output. Once load current increases and VRSNS is larger than VTH, a negative feedback will be included through CLA and power transistor. The output current is clamped to its maximum output current

I MAX =

K RTH IN . 2 RSNS

(4)

Due to the input common mode rage (ICMR) limitation, the PMOS input stage cannot be active at this condition when

VOUT > VIN VSGP VSD (sat ) .

(5)

Therefore, the output current is less than IMAX. If the load becomes more heavily, or in the other word, the load resistance becomes smaller, the output voltage will be decreased. When the output voltage falls into the boundaries given by

The proposed current-limit circuit has been used in a LDO with 0.35-m CMOS technology. The output voltage is 1.8 V and the input range is from 2 V to 3.3 V. All the simulation results are based on a 2.5-V input unless otherwise defined. The waveforms of VOUT and IOUT with different load resistances are shown in Fig. 5. The maximum output current and the shorted-circuit current are 197 mA and 77 mA, respectively. From the simulation result, it shows that the power dissipation of power transistor can be decreased effectively when comparing with the constant current-limit method. The power consumption of the power transistor can be saved up to 61% when the output is shorted to the ground or with very small load resistance. Fig. 6 is the curve of VOUT versus IOUT with process and temperature variations, a different and more detailed description of Fig. 5 and a typical waveform which can be seen in most paper reporting foldback current limit. It shows that VOUT and IOUT change a little at two worst-case corners: worst power 85 C high temperature (wp/85) and worst speed -20 C low temperature (ws/-20), comparing its value at typical mean in 27 C (tm/27), which is consist with that described in Section III. The quiescent current (Iq) of the proposed LDO is nearly the same at different load conditions, shown in Fig. 7. The curve of the quiescent current versus the output current of a popular commercial CMOS LDO, LP3999 [8], is plotted in this figure for comparison. The quiescent current is proportional to the output current, which leads to the quiescent current in the 100-mA load condition is nearly 100 A, which is two times of that at no-load condition at LP3999 with the traditional current-limit technique. When it turns to the proposed LDO, the quiescent current in the 100-mA load condition is 5.7 A. It is only 2.2% increase comparing 5.58 A in the no-load condition. The simulated load transient response is shown in Fig. 8. The output current changes from 1 mA to 100 mA during 1s period, and the output capacitance is 10 F and the equivalent series resistance (ESR) is 100 m. From the simulation result we can know that the LDO is stable but the phase margin is not large enough and the recovery speed is slow. The reasons are the low-frequency parasitic poles and slow slew rate caused by ultra low quiescent current, and some new approaches have been proposed to solve these problems [9].

VGSN + V DS ( sat ) < VOUT < V IN VSGP V SD ( sat ) ,

(6)

both the NMOS and PMOS input stage are active, and the output current will be decreased as well. If the load resistance still decreases, the output voltage will become smaller. Once

VOUT < VGSN + VDS (sat ) ,

(7)

only the PMOS input stage can be active in that case, so the output current will be clamped to ISHORT, and

I SHORT =

K RTL IP . 2 R SNS

(8)

The RTL is less than RTH to perform fold-back current limit (i.e. set a smaller current-limit threshold for short- circuit condition than maximum current limit).

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0.2

1.84 VOUT (V)

-1 0 1 2 3

IOUT (A)

0.15 0.1 0.05 0 -2 10 2

1.82 1.8 0.9 1 1.1 1.2 Time (s) 1.3 1.4 1.5 x 10
-3

10

10 10 Rload (ohm)

10

10

IOUT (A)
-1 0 1 2 3

1.5 VOUT (V) 1 0.5 0 -2 10

0.1 0.05 0 0.9

10

10 10 Rload (ohm)

10

10

1.1

1.2 Time (s)

1.3

1.4

1.5 x 10
-3

Fig. 5. Simulation results of VOUT/IOUT vs. RLOAD.

Fig. 8. Load transient response of the proposed LDO.

V.
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.02 0.04 0.06 0.08 0.1 0.12 IOUT (A) 0.14 0.16 0.18 0.2 tm/27 wp/85 ws/-20

CONCLUSION

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic has been designed for a LDO with 100-mA load capability in a 0.35-m CMOS technology. The propose circuit has been verified by the Hspice simulation. With this architecture, the quiescent current is nearly the same at all load conditions and the power dissipation of power transistor can be saved up to 61%. Moreover, this structure can be reproduced easily in other processes and has less sensitivity to process and temperature variations. REFERENCES
G. A. Rincon-Mora and P. E. Allen, A low-voltage, low quiescent current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan 1998. [2] K. N. Leung and P. K. T. Mok, A capacitive-free CMOS low-dropout regulator with damping-factor-control frequency compensation. IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 16911702, Oct. 2003. [3] G. Bontempo, T. Signorelli and F. Pulvirenti, Low supply voltage, low quiescent current, ULDO linear regulator, in proc. IEEE International Conference on Electronics, Circuits and Systems, pp. 409-412, 2001. [4] R. Mammano, J. Radovsky and G. Harlan, A new linear regulator features switch mode overcurrent protection, in proc. IEEE Applied Power Electronics Conference and Exposition, pp. 159-164, 1989. [5] B. Mammano, Current sensing solutions for power supply designers, Unitrode Seminars SEM1200, 1999. [6] C. Lin and Q. Y. Feng, Design of current limiting circuit in low dropout linear voltage regulator, in proc. Asia-Pacific Microwave Conference Proceedings, 2005. [7] J. A. De Lima and W. A.. Pimenta, A current limiter for LDO regulators with internal compensation for process and temperature variations, in proc. IEEE International Symposium on Circuits and Systems, pp. 2238-2241, 2008. [9] Low Noise 150 mA Voltage Regulator for RF/Analog Applications. http://www.national.com. [10] K. N. Leung, Y. S. Ng, K. Y. Yim and P. Y. Or, An Adaptive Current-Boosting Voltage Buffer for Low-Power Low Dropout Regulators, in proc. IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 485-488, 2007. [1]

VOUT (V)

Fig. 6. Simulation results of VOUT vs. IOUT at different conditions.

x 10
-5

10 Iq (A) 8 6 4

LP3999

0 x 10
-6

0.02

0.04 0.06 IOUT (A)

0.08

0.1

5.8 Iq (A) 5.7 5.6 5.5

Proposed

0.02

0.04 0.06 IOUT (A)

0.08

0.1

Fig. 7. Iq vs. IOUT in LP3999 and proposed LDO.

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