Name: Zahrein Bin Yaacob Emails: zahrein@gmail.

com Contact No: 0122096051 Nationality: Malaysian

Career Details Work Place: Intel Corporation, Malaysia site. Current: 1. Memory Circuit Designer [8T & 6T] 2. Circuit Validator using Verilog AMS for High Speed Past: 1. GPIO Circuit Design Engineer (2010-2011) 2. Circuit Validation Engineer using Ultrasim for High Speed I/O (2007-2010) 3. SMV Engineer (Post Silicon) for Pcie/DMI Gen2 (2006-2007) Education: 1. Degree: Communication & Electronics Engineering (2004) (2nd Class Uppper ~3/4.0) 2. Professional Certificate from Toppan Design Ltd (Japan) Summary I am a man that has high interest in Circuit design and Management work. My 6 years experience in circuit design, circuit validation, and post silicon validation and able to lead a team is indeed a valuable learning for me. Being leaders and able to complete a work is a great satisfaction. Through the 6 years I am exposed to the world of Circuit Design, Circuit Verification and post silicon validation. I had some bad experience through my career especially on circuit validation side where the product had been caught to be a bug after PRQ. The challenges and being tough have brought me forward to become more dynamic engineer. I can say im quite a learned person as I always took the job whatever given to me. This is proven on the task I listed below. The room of improvement to me is that I need to write more technical papers which I have not tried. I like to read Technical verification papers so that I understand the design concept and the coverage of the verification at the pre silicon level. Tasks Given:

1. Circuit Design ( Manage to design CFIO block, op-amp, SRAM for 6T and 8T) 2. Circuit validation - (validated on PLL, High Speed Tx &RX on USB3, SATA3, Pcie Gen3,
Comp circuit.

3. Post Silicon Validation ( Using DFT to test chips to test on Pcie Gen2, SDVO & LVDS )

Project Experiences 1. Circuit Design ( Manage to design CFIO block, op-amp, SRAM for 6T and 8T)
CFIO Tasks: Designing the GPIO Buffer on Low Voltage mode for chipset for 1269,1271 process). Use the presto simulation tools and do all the pre Silicon Validationas on all Hard IP Blocks. Skills obtained are XA(Functional schematics), Presto, Safran (schematic viewer) and PVX (check all the verifications that include timing, layout, schematic, aging simulation, leakage). - Made Circuit changes on 2 circuit blocks . The purpose is to generate the powergood signal internally in GPIO family to be connected to CFIO Buffers for power sequencing EOS protection. With this, there is no powergood signal required from the core and there is no power

Memory Tasks: I am the team lead to deliver the collaterals such as layout(LNF, GDS), Circuit schematics and RTL. Responsible of the quality of the collaterals by validating the Circuit and the RTL. Delivering the SRAM Memory Size for 6T and 8T type in the committed schedule and in high Generating the 8T using the memory compiler and for 6T we design the memory manually as there is the Sense Amplifier.

2. Circuit Validation Engineer using Ultrasim for High Speed I/O (2007-2010) Validation Tasks: Team lead for Circuit Validation group on the Hard IP products. Working on innovative power and/or performance optimization and dynamic power management for future generation microprocessor and chipset including energy efficient architecture, power and/or performance tradeoff analysis, voltage and clock frequency distribution, dynamic power managements, RTL level power estimation and power efficient architecture verification Responsible on validating the schematic circuits by using the RTL(stimulus input) to make sure the circuit functionality is working fine and according to the specs required. Catching the bugs at the core and the I/O ring system is the aim objective of my job. Currently validating the future edge technologies such as Pcie/DMI Gen2.0, SATA Gen 3.0 and USB Gen3.0 that will be out on the year 2012-2013

3. System Marginality Validation Engineer

System engineer for validating Intels chipset on Pcie 2.0. Job scope included verification and evaluation of processor's electrical design, functionality, feature enhancement and post silicon validation. Major accomplishments are as follows Capture hardware design failures and identify probable cause for component defect, provide recommendations to ensure products meets design and technical specs. . Develop test methodoligies to enhance effeciency in terms of execution timing and validation coverage. Improve the validation process by adopting new methodologies (i.e., data driven process, using large sample size and statistical approach). Test and design electrical hardware for motherboard components (i.e., power supply, graphics and audio cards, memory cards and other Intels on boards technologies).