Xilinx

EDN Asia - Embedded Systems & Software Seminar Bangalore, April 19, 2006 Presented by Mr.
Neeraj Varma, Country Sales Manager, Xilinx India
Xilinx Fast and Flexible Embedded Processing
EDN Asia - Embedded Systems & Software Seminar
Agenda
Why Embedded Design The Advantages of FPGA Embedded Design FPGA-Specific Embedded Design Tools and
Methodology Xilinx Embedded Processing Design Solutions How To Accelerate Performance Beyond The Core Summary
Rarely the Ideal Mix

1
Difficult to Find the Required Mix of Peripherals in

Off the Shelf (OTS) Microcontroller Solutions
Even with variants, compromises must still be made
Microcontroller #1 Microcontroller #2
UART UART FLASH FLASH UART UART
System Requirements
2@ UART TIMER I2C SPI GPIO FLASH DDR SDRAM
FLASH FLASH RAM RAM GPIO GPIO
UART UART SPI SPI Timer Timer
DDR DDR GPIO GPIO I2C I2C
CPU Core CPU Core
CPU Core CPU Core
CAN CAN SPI SPI Timer Timer
Lacks I2C & Includes RAM vs DDR SDRAM
Lacks a Second UART & Includes Unnecessary IP
Must decide between inventory impact of multiple configurations or device cost of comprehensive IP
Xilinx Fast and Flexible Embedded Processing 3 EDN Asia - Embedded Systems & Software Seminar
Changing Requirements
2
Selecting a Single Processor Core with Long

Term Solution Viability is Difficult at Best
Future proofing system requirements is difficult at best
100 MHz 2@ UART TIMER I2C SPI GPIO FLASH DDR SDRAM 100 MHz Core 100 MHz Core
Todays System Requirements
Microcontroller
FLASH FLASH DDR DDR GPIO GPIO I2C I2C UART UART UART UART SPI SPI Timer Timer
Future System Requirements

150 MHz 2@ UART TIMER I2C SPI GPIO FLASH DDR SDRAM 10/100 Ethernet
Completely meets current system requirements
Changing processor cores to accommodate new requirements consumes valuable design resources
Here Today, Gone Tomorrow

3
Without Direct Ownership of the Processing

Solution, Obsolescence is Always a Concern
A single core is used to create a family of Cs
FLASH FLASH CAN CAN
Microcontroller Variant #1 - High Volume Automotive Microcontroller Variant #2 - Moderate Volume Consumer Microcontroller Variant #3 - Lower Volume Niche
RAM FLASH RAM FLASH
CPU Core CPU Core
UART SPI UART SPI
GPIO RAM FLASH GPIO RAM FLASH GPIO RAM GPIO RAM GPIO GPIO
CPU Core CPU Core
SPI UART I2C SPI UART I2C Timer SPI UART Timer SPI UART Timer SPI Timer SPI Timer Timer
CPU Core CPU Core
The sheer number of C configurations can lead to obsolescence of lower volume configurations/variants
Chipset Solutions
4
Many Microprocessor Based Solutions Provide

Limited On-Chip Peripheral Support
Manufacturers create I/O devices to extend the functionality of the base processor core
Microprocessor Microprocessor
Microprocessor Chip-Set
MPU Interface MPU Interface
Serial Serial Parallel Parallel PWM PWM
Pre-defined interface limits performance
I/O Expansion Device
An external, pre-defined interface between a P and its support device limits overall system performance
Agenda
FPGA Embedded Design

1
FPGAs Allow for the Implementation of an Ideal
Mix of Peripherals and System Infrastructure 2 New System Requirements can be Supported without Changing the Processor Core 3 Longevity of FPGAs Approaches the Longest Available Microcontrollers in the Market 4 FPGAs are Used to Augment P Functionality Absorbing the Core is the Next Natural Step
Other Key Advantages

Traditional Embedded Platforms Platform FPGA
Fixed peripherals Fixed address maps Fixed BSP
Design dependent peripherals Each board is unique and custom Need efficient custom BSP creation
Flexibility and Functionality

Why Integrate a Processor?

FPGA evolved from glue logic into system platform Nearly all systems are composed of:
Logic + Memory + Processor
Enables optimum system partitioning between HW and SW Customers Embed it their way or Build your own MCU
Performing SW tasks in HW is Expensive Performing HW tasks in SW is Slow
Tune the optimum Hardware and Software balance

Agenda
11
Necessary Tools
A Full Complement of Tools are Required to
Design an Embedded Processor System
Processor System Generation Hardware Implementation & Software Compilation Hardware & Software Debug
HW Implementation & SW Compilation are the

two Main Flows that Must be Addressed
The Embedded Flows Should Mirror Traditional Flows
System Generation
clock interrupts reset
Tools are needed to create the system infrastructure, connect peripherals and configure the peripherals as desired
Core Core
Arbiter Arbiter
Primary Bus Primary Bus
Bridge Bridge
Secondary Bus Secondary Bus
Arbiter Arbiter
FLASH FLASH
?
SRAM SRAM
Timer Timer
UART UART
Databits = 8 Baudrate = 9600 Parity = Off
Once the system is defined, the hardware can be implemented and software compiled
13
Hardware Implementation
Source Code Synthesis Synthesis
VHDL or Verilog
System Netlist
Standard FPGA HW Development Flow
Constraints
Build & Map Build & Map
Simulation/Synthesis Build & Map
Merged & Mapped Design Memory Map for Internal Code Storage
Place & Route
Place & Route Place & Route
Configuration File
Configuration File
14
Software Compilation
C Code
Compiler Compiler
Source Code
Standard Embedded SW Development Flow
Assembly Code
C/C++ Cross Compiler Assembler Linker
Assembler Assembler
Source Code
Relocatable Object Code Mapfile and Linker Script
Machine Code
Linker Linker
Machine Code
15
HW & SW Debug
JTAG Port Debug Port clock interrupts reset Integrated Integrated Bus Analyzer Bus Analyzer
Internal & external logic analysis is used to determine where problems reside
Core Core
Arbiter Arbiter
Primary Bus Primary Bus
Bridge Bridge
Secondary Bus Secondary Bus
Arbiter Arbiter
SW debug typically consists of JTAG based runtime control of the target processor core
FLASH FLASH
SRAM SRAM
Timer Timer
UART UART
Integrated Integrated Logic Analyzer Logic Analyzer
External Connection
16
Complete Flow & Toolset

Processor System Generation Handled by XPS Hardware Implementation Leverages Traditional
FPGA Implementation Flows - No New Tools Software Compilation Leverages Traditional Software Compilation Flow - No New Tools Hardware Debug - Full Internal Instrumentation Software Debug - Complete Runtime Control Full HW/SW Interactive Debug
17 EDN Asia - Embedded Systems & Software Seminar
System Design Flow

C Code VHDL or Verilog Standard Embedded SW Development Flow Xilinx Platform Studio (XPS) Standard FPGA HW Development Flow
Code Entry Include the BSP C/C++ Cross Compiler and Compile the Software Image Linker
Board Support Package Data2MEM
HDL Entry System Netlist Instantiate the Simulation/Synthesis System Netlist and Implement Implementation the FPGA
?
Load Software Into FLASH Debugger
Compiled ELF
Compiled BIT
Download Combined Image to FPGA
Download Bitstream Into FPGA Chipscope
RTOS, Board Support Package
18
Agenda
19
Introducing Xilinx Embedded Processing Design Solutions

Processor Cores
Industry Standard PowerPC core immersed in the Virtex family Xilinx MicroBlazeTM 32-bit RISC
Selected as EDN Hot100 Products of 2005
Xilinx PicoBlazeTM 8-bit Controller
Robust selection of standard peripherals (IP) Complete Development and Debug environment for integrated HW and SW flows
Award Winning Platform StudioTM
Rich ecosystem of partner support Xilinx FPGA is a platform for Custom Processing
Xilinx Embedded Processors

one size doesnt meet all
Features
Highest Performance 32-bit General Purpose Architecture With Acceleration Only Dual PowerPC Core Architecture 700+ DMIPS 32-bit General Purpose Architecture Soft Core with Acceleration 166 DMIPS Lowest Cost 8-bit Architecture Soft Core 100 MIPS
Performance
Plus: Broad Range of Common Peripherals and IP
Flexible Embedded Use Models

1 2 3
State Machine
Microcontroller
Custom Embedded Highest Integration, Extensive Peripherals, RTOS & Bus Structures Networking & Wireless High Performance
Lowest Cost, No Peripherals, No RTOS & No Bus Structures Vast range of applications (Programmable
State Machine)
Low/High Performance
Medium Cost, Some Peripherals, Possible RTOS & Bus Structures Control & Instrumentation Moderate Performance Range of Use Models
22
PowerPC Embedded System

PowerPC 405
Data Control Register Bus - DCR

DSOCM DSOCM
ISOCM ISOCM
System System Reset Reset JTAG JTAG Block Block
BRAM User Logic User Logic
User Peripheral User Peripheral OPB IPIF OPB IPIF
Instruction
Data
PLB Arbiter
Processor Local Bus - PLB
PLB/OPB Bridge
On-Chip Peripheral Bus - OPB
OPB Arbiter
GE MAC GE MAC
Memory Memory Controller Controller
PCI 64/66 PCI 64/66
10/100 10/100 Ethernet Ethernet
GPIO GPIO
UART UART
DDR SDRAM SDRAM ZBT SSRAM

Xilinx Fast and Flexible Embedded Processing 23
Memory Memory
Virtex-II Pro Fabric

Full System Customization & High Performance
Embedded System
Instruction-Side Local Memory Bus
Dual Port Dual Port Block RAM Block RAM

MicroBlaze
Data-Side Local Memory Bus
Data LMB Data LMB
Inst LMB Inst LMB
System System Reset Reset JTAG JTAG Block Block
User User Peripheral Peripheral
FSL
User User Logic Logic
OPB OPB IPIF IPIF
On-Chip Peripheral Bus - OPB
OPB Arbiter
On-Chip On-Chip Peripheral Peripheral
Memory Memory Controller Controller
Block Block RAM RAM
10/100 10/100 Ethernet Ethernet
UART UART
GPIO GPIO
DDR SDRAM ZBT SSRAM SDRAM

FPGA Fabric
Robust Catalog of Pre-Verified Peripherals and IP

Connectivity
Parallel
PCI, PCI-X PCI, PCI-X SPI-3, SPI-4 SPI-3, SPI-4 HyperTransport HyperTransport XGMII XGMII RapidIO RapidIO Many more Many more
General Purpose
CORE Generator CORE Generator
Building Blocks Building Blocks Memory Generators Memory Generators IOB Configurations IOB Configurations Arithmetic and Shifters Arithmetic and Shifters Registers Registers Buffers Buffers Many More Many More
Serial
1 GE MAC+PHY 1 GE MAC+PHY XAUI XAUI PCI Express PCI Express Aurora Aurora Many more Many more
Peripherals Infrastructure
Processor
DSP & Math

Advanced
Reed-Solomon Turbo Codecs Virterbi Video Wireless Many More
Interrupt Controller CoreConnect Bus UARTs Arbiter ATM Utopia L2 Bridge Timer Memory controllers GPIO Soft processors SPI Software IP 10/100/1000 Many more EMAC
Math
Multipliers MAC Divider Filters CORDIC Many more
25
Platform Debug Integrated HW / SW Debug

Cross triggering of HW & SW debuggers to find and fix embedded bugs faster
Developers spend most of their project development time doing TEST & DEBUG
ChipScope Pro
Enabling better insight into the HW / SW code dynamics

Platform Studio
Industry Leading 3rd Party Ecosystem

Embedded Tools Co-design Tools
RTOS
Middleware
IDE/Debug Tools
ESL Tools
Co-Verification
27
Agenda
28
Do You Have Enough Performance?

3 GHz
300 MHz
APU or FSL
CPU
C C
FPGA FPGA
HW Accele rator
Brute Force
Intelligent
Fast Co-Processor Interfacing

Conventional approach
C
Bus Interface
FPGA, ASIC FPGA, ASIC or ASSP or ASSP
MicroBlaze
PowerPC
Xilinx Solutions
FSL
Co-Processor / Peripheral
APU
Co-Processor / Peripheral
Fast Deterministic Easy implementation
Spartan-3
Virtex-4 FX
FSL and APU enable Accelerate Performance Beyond the Core

Auxiliary Processor Unit (APU)

Accelerate Performance Beyond The Core
APU
Offloads CPU intensive operations Extends PowerPC instruction set Provides direct interface
from CPU pipeline to FPGA logic Simplifies integration of co-processor and hardware accelerators
Reduce number of bus cycles by factor of 10X Increase performance by over 20X
31
Algorithm Acceleration with APU

Using Impulse Co-Developer Application PowerPC Only
(300 MHz)
PowerPC + Acceleration Co-Processor

(300/50 MHz)
Image Filter Encryption

Image Texturing
Fractal
0.14 sec 2.3 sec 119 sec
0.012 sec 0.067 sec 6 sec
11 x 34 x 20 x
32
Agenda
33
Fast and Flexible Embedded Processing Solutions

Highest Performance FPGA Embedded Processor Solutions
Industrys Only Dual PowerPC core with Acceleration Enhanced architecture and functionality Auxiliary Processor Unit Control Interface in Virtex-4 FX
Broadest range of processor solutions

From the smallest to the fastest Flexible Integration
Scalable logic resources and Scalable Cost Points
Most complete design environment for customers flexibility

Optimized HW and SW partitioning
34
To Find Out More.

New Xilinx Embedded Magazine
First issue Mar 2005 Second Issue Sep 2005
On the web at Xilinx.com

Xilinx Processor Central site
www.xilinx.com/processor
Xilinx Embedded Development Kit, Platform

Studio Tools
xilinx.com/XPS www.xilinx.com/support/training/XPS-package.htm www.xilinx.com/xds/index.htm
Xilinx Embedded Training Courses Xilinx Design Services

Development, Eval)
Xilinx and Partner Boards (Reference,

www.xilinx.com/xlnx/xebiz/board_search.jsp
ww.xilinx.com/xlnx/xebiz/onlinestore.jsp?sGlobalNavPick=PUR CHASE
Xilinx Online Store
35

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EDN Asia - Embedded Systems & Software Seminar Bangalore, April 19, 2006 Presented by Mr.

Neeraj Varma, Country Sales Manager, Xilinx India

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

Rarely the Ideal Mix

Difficult to Find the Required Mix of Peripherals in

FLASH FLASH RAM RAM GPIO GPIO

UART UART SPI SPI Timer Timer

DDR DDR GPIO GPIO I2C I2C

CPU Core CPU Core

CPU Core CPU Core

CAN CAN SPI SPI Timer Timer

Lacks I2C & Includes RAM vs DDR SDRAM

Lacks a Second UART & Includes Unnecessary IP

Selecting a Single Processor Core with Long

Todays System Requirements

Future System Requirements

Completely meets current system requirements

Here Today, Gone Tomorrow

Without Direct Ownership of the Processing

RAM FLASH RAM FLASH

CPU Core CPU Core

UART SPI UART SPI

CPU Core CPU Core

CPU Core CPU Core

Many Microprocessor Based Solutions Provide

Serial Serial Parallel Parallel PWM PWM

Pre-defined interface limits performance

I/O Expansion Device

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

FPGA Embedded Design

FPGAs Allow for the Implementation of an Ideal

Other Key Advantages

Fixed peripherals Fixed address maps Fixed BSP

Flexibility and Functionality

Why Integrate a Processor?

Tune the optimum Hardware and Software balance

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

HW Implementation & SW Compilation are the

Primary Bus Primary Bus

Secondary Bus Secondary Bus

Databits = 8 Baudrate = 9600 Parity = Off

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

Standard FPGA HW Development Flow

Build & Map Build & Map

Simulation/Synthesis Build & Map

Place & Route

Place & Route Place & Route

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

Standard Embedded SW Development Flow

C/C++ Cross Compiler Assembler Linker

Relocatable Object Code Mapfile and Linker Script

Xilinx Fast and Flexible Embedded Processing

EDN Asia - Embedded Systems & Software Seminar

Primary Bus Primary Bus

Secondary Bus Secondary Bus