\Setting CMOS Environment for

I _

VLSI Design ;

A Thesis Presented to The Faculty of the College of Engineering and Technology Ohio University

In Partial Fulfillment of the Requirements for the Degree Master of science

BY
Chih-Ping Chung,#
4

November, 1989

ACKNOWLEDGEMENTS

I would like to especially thank Dr. Janusz A. Starzyk for his inspiration and encouragement to set up CMOS

environment for VLSI design. I also thank the members of my committee, Dr. Robert A. Curtis, Dr. Henryk J. Lozykowski and Dr. John D. Gillam, for their invaluable assistance. My deepest appreciation goes to Mr. Wu-Kai Lee and Mr. Randy Yu for their efforts and CAD support. Also, thanks to Mr. Gerald Blackburw and Miss. Elis for their patient

inspiration.

Finally, my great appreciation and acknowledgement goes to my wife Hsiao-yen Leen and my parents for their endless support, devotion and love, without which this job could not have been done.

~hih-PingChung

TABLE OF CONTENTS

CHAPTER 1. I'NTRODUCTION

...................................1

CHAPTER 2

. TECHNOIXGY UPGRADE FOR VALID WORKSTATION

FROM nMOS TO CMOS 2.1

.............................3 Introduction............................... 3

2.2 Comparison between NMOS and CMOS technologies 2.3

...............................4 CMOS Technology ............................ 8 2.3.1 Introduction......................... 8

2.3.2 Description of n-well fabrication process 2.3.3

..............................9
...............12
.............17

CMOS colormap and technology files for Valid workstations

2.3.4

CMOS layout design rules

CHAPTER 3. INSTALLING LVS ON THE SCALD SYSTEM 3.1 3.2

............21 Introduction.............................. 21 21 Layout tools section...................... 3.2.1 The command file structure ..........22
3.2.2 3.2.3 Geometric operation commands DRC/Extract control commands

........25

3.3

........32 3.2.4 Hierarchy section commands ..........33 Running COMPARE for LVS ...................34 3.3.1 Need for LVS ........................34
3.3.2 Hierarchical design for LVS

.........35

333 ..

Running COMPARE procedure

...........47

CHAPTER 4

. DESIGN EXAMPLE ................................52 4.1 New product release procedure ................52 .........57 4.2 Example of predecoder design (PD512) 57 4.2.1 Introduction........................... 4.2.2 Process definition and development .....59 4.2.3 Functional design of PD512 .............68

CHAPTER 5

. CONCUJSION....................................84
...............................................86
...............................................88
..............................................116

REFERENCES

APPENDIX-A

APPENDIX-B

CHAPTER 1. INTRODUCTION

CMOS(Comp1ementary Metal Oxide Silicon) is the fastest growing process technology in recent years. This is due to the two key features of the CMOS technology: higher circuit density combined with lower power. CMOS has the greatest impact in low power and medium speed applications such as industrial control, medical analyzers and most of the

automatic test equipment. CMOS products will continue to be a popular choice in many designs. The advanced CMOS process provides higher performance, better noise margin and lower power consumption than nMOS. Moreover, the feature size of CMOS has been scaling down continuously.l1 Ten years ago, a CMOS feature size of 5 to 7.5um was state-of-the-art

technology. By the end of 1986, lum CMOS technology was available and used increasingly to produce commercial VLSI chips,It [Masakazu 881. Therefore, it is vital to make this new technique available to students so that their

qualifications can match the needs of industry. I1Verification and validation of a design are an even more difficult challenge, [Mukherjee 861

The development

of powerful circuit design tools and software systems are the keys to the success of VLSI technology. There are many kinds of design for tools, which are presently used as and

developed

integrated-circuit chips, such

Layout

Editors (LED), Graphics Editors (GED), circuit extractors and

Layout verification System(LVS). design tools at E.C.E.

All the principle VLSI

Department are available on Valid

workstations except LVS which is a layout verification tool. It is an important design tool for VLSI design. The purpose of this thesis is to set up and test a complete CMOS VLSI environment on Valid workstations. The work on this thesis was organized around three major goals:
Goal I: Upgrade old nMOS to advanced CMOS technology

In order to upgrade Valid workstations from nMOS to CMOS, there were two steps to be done.
1) Setting up CMOS technology and color map files

2) Developing design rules checker program(DRC) for

CMOS technology rules

Goal 11: Installation of LVS in SCALD system

To run Compare 1.3L version on Valid workstations, an Extract program and special CMOS library was necessary to be set up.
Goal 111: Designing an example (PD512)

A circuit PD512 was developed as a design example from functional partitioning through circuit simulation to LVS

Chapter 2 illustrates how to do an upgrade from nMOS to CMOS for Valid workstations, and develops CMOS design rules. How to develop CMOS Extract program and to design a layout for LVS are described in Chapter 3. Chapter 4 gives a design example. Finally, further improvements and conclusions are described in Chapter 5.

CHE% !AlR

2 TECHNOIDGY UPGRADE FOR VALID .

WORKSTATION FROM nMOS TO CMOS

2.1 Introduction:

Transistors

in

nMOS

technology

with

electrons

as

majority carriers are called n-channel devices ( n M 0 ~ ) Holes are majority carriers in p-channel devices (PMOS) When PMOS and nMOS devices are fabricated on the same substrate, these devices are called CMOS devices. Since PMOS and nMOS devices are made on the same substrate, latch-up and die size are of important concern. At present, there are several approaches to prevent CMOS from latch-up by making p+ and n+ guard rings and by using EPI-substrate wafers to achieve smaller

die size for CMOS technology. Furthermore, CMOS circuits have other advantages over nMOS circuits such as lower power dissipation and higher noise margin. Therefore, CMOS has become a very important technology for VLSI. To upgrade Valid tools from nMOS to CMOS, it is

necessary to change technology and color map files. Since the CMOS fabrication process is much more complex than nMOS, CMOS circuits need more layers in these files. The 1.8um CMOS EPROM process is chosen to produce design rules. For CMOS EPROM technology 13 layers are typically needed, for very high speed products, two more layers are required such as a second metal and via contact.

2.2 Comparison between nMOS and CMOS technologies

In nMOS technology p-type high-resistivity silicon wafers are used as the substrate material. be created In CMOS

technology

special

regions must

for PMOS

transistors. These regions are called wells or tubs. For this CMOS EPROM process, an n-well is created in a p-type substrate wafer. comparison between nMOS and CMOS is

described in detail.
1 nMOS technology: .

nMOS technology uses enhancement mode transistors with a positive threshold voltage, and depletion mode transistors with a negative threshold voltage. These transistors are used as drivers, loads, and pass transistors to design functional blocks.
2. CMOS technology:

CMOS technology uses enhancement mode transistors as drivers, depletion mode transistors as pass transistors, and complementary transistors as loads. Since nMOS and CMOS use different mode transistors as loads, their transfer characteristics are also different. Fig.2.l shows a transfer characteristic for an inverter when an nMOS depletion transistor is used as a load. Fig.2.2 shows a transfer characteristic for an invertor with an nMOS enhancement transistor used as a load. Finally Fig. 2.3 shows a transfer curve with a PMOS transistor used as load.

GND

I I
I

I
I

I
I I I I I I I

Non-zero

output

I I
I

I
I

Fig. 2.1 Inverter and its transfer characteristic with nMOS depletion transistor as a load

Fig. 2.2 Inverter and its transfer characteristic with nMOS enhancement transistor as a load

GND

v ss

Fig. 2.3 Inverter and its transfer characteristic with PMOS transistor as a load

From Figs.2.1,

2.2

and

2.3,

we can summarize the

results of comparisons between nMOS and CMOS inverters as follows:

a) Noise margin:
There is non-zero output for nMOS and zero output for CMOS when input is high. Therefore, CMOS has higher noise margin than nMOS.
b) Power dissipation:

The current of an nMOS inverter flows all the time for logical 1 inputs, however, current of a CMOS inverter flows only during logic transition, therefore, CMOS has zero

static power dissipation. With the new improvements in maskmaking, it is possible to fabricate devices smaller and smaller in size. The nMOS circuits become very dense. Maximum power dissipation become the limiting factor for high density nMOS VLSI chips. In order to reduce the dc power dissipation, obtain higher

noise margin, and high density of VLSI devices, CMOS is the obvious choice.

2 3 CMOS technology: .
2.3.1

Introduction An n-well CMOS process, which is currently the most

popular process in CMOS fabrication, will be discussed in this section. CMOS technology provides both n-channel and pchannel MOS transistors on the same chip. nMOS transistors are designed in the p-type substrate, while PMOS transistors

are built in the n-well. A simple n-well CMOS fabrication sequence is shown in Fig.2.4 and a set-up procedure for

layout and design rule checking is discussed in Sections 2.3.3 and 2.3.4.

2.3.2

Description of n-well fabrication process As an illustration of the fabrication process, a CMOS

inverter example is described. The first step is to define the n-well regions. To form them, the phosphorus is

implanted into these regions at high-temperature cycle. After n-well implant, the active regions are defined for MOS source and drain regions. The formation of active

regions are accomplished through local oxidation of silicon (Locos process). In this process thick regions of silicon dioxide are grown on the silicon substrate to provide

isolation between nMOS and PMOS transistors. The thickness of the field oxide is about 5000 A. The gate oxides are grown only in the open areas of the active region. In general, the thickness of the oxide layer is about 250A. The gate oxides will affect the threshold voltage of the MOS transistors. When field and gate oxide growth made. Usually the chemical vapor deposition(CVD) process is used to deposit the polysilicon (poly) layer over the entire wafer. Poly is used, not only as a gate, but also for is finished, the polysilicon deposition will be

interconnections. We use the dry etching process to remove

Formation of n-well regions Formation of the active regions

Field and gate oxide growth Deposit the polysilicon layer

N diffusion

+
I

1
&

+
P diffusion

I
I

*
I

CVD deposition of SiO2 Contact cuts Metallization

Passivat ion Packaging

Fig. 2.4 CMOS fabrication sequence

11 the undesired poly which is outside of the gate regions and the interconnecting patterns. After the thin gate oxide is etched, we use a n+ mask (n-select mask) to define source and drain regions of nMOS transistors and implant phosphorus to obtain low-resistance source and drain regions. In the same manner, we define the p+ source and drain regions of PMOS transistors. The p+ source and drain regions of PMOS transistors are defined by a negative of the n-select mask. Boron is used as the dopant in the process step instead of phosphorus, when completing the implant of p+ and n+ source/drain. We use a CVD technique to deposit SiOZ over the entire wafer as an insulating layer. In order to expose the n+ and p+ areas and connect them to outside metal, we use a contact mask to define contact cuts in the insulating layer. The metallization mask is used to define the

interconnection pattern. Then, the evaporation process is used to deposit aluminum over the entire wafer, and the undesired metal is removed by etching. Passivation is used in the final step of the wafer fabrication, in order to protect the wafer surface from contaminants and scratches. We see from the above discussion that ten layers of masks are needed for device fabrication in a typical CMOS process. Layer data is either drawn directly or generated indirectly from logic operations in Valid CAD systems. The

details are described in 2.3.3.

2.3.3

CMOS colormap and technology files for Valid

workstations In general, colormap and technology files are needed only for layout drawing. To create a layout drawing, we need to specify all the layers. "A technology file defines various masks and symbolic layers in a cell. This file also defines the color, fill pattern, and outline pattern used to display each layer, and references a colormap file that sets each layer's color^^, (Valid layout EDITOR REFERENCE MANUAL). Colormap and technology files will be discussed next. a) Colormap file: Colormap file determines colors of all layers on the screen. The red, green and blue colors are the three basic colors. The color of combination layers is determined by the intensities of the red, green, and blue color. The intensity values ranges from
0 (off)

to 255 (maximum intensity) We can

change the color of layers by using PED(Pa1ette Editor Display). The format of the colormap file is: [red green blue color number] Color number is associated with technology file, the colors of different layers are shown below: The p active layer would be in yellow on a color graphics.termina1. The n active layer is in green The polysilicon layer (poly2) is in red

The metal layer is in blue The contact cut is cross The n-well layer is dashed line An example of CMOS color map file is presented below: [red, green, blue, color member] 178 0 250
94

183 0
0

1
2
3

200 100

Column 1 is red, column 2 is green and column 3 is blue, number 178 is intensity value of red, 94 is intensity value of green, 183 is intensity value of blue, 1 is color number corresponding to the color number of technology file. To change the color of a layer, we can call up the PED display by entering this command:
PED

Then select the E D I T command from the PED display (Fig.2.5) and select the layer to edit. There are several ways to pick layers:
1 Pick layers from the layer menu .
2 Select one or more layers from the active palette .
3. Type layer names at the keyboard

To obtain the desired color, we need to adjust the intensity values of red, green and blue. When you want to exit from

14 PED, use the QUIT command. A physical CMOS color map file is shown in Appendix A-1.
b) Technology file:

Different mask symbolic layers and the unit sizes are described in a technology file. The first line of the file is the name of the technology such as nMOS, CMOS etc. The second line is the name of the colormap file to be used with the technology. The third line contains three numbers

separated by spaces. The first number specifies the number of centimicrons such as 100 for microns and 254 for mils (lmil =25.4um)

Most companies use micron instead of mils

in current development. The second number is the grid spacing and the third number is the grid interval in this technology. Each layer in the technology file is described in the following format. layer-name outline-pattern fill-style color-number In this format layer-name is the name of the layer. The outline-pattern describes the style of the outline and is a hexadecimal number between
0

and

FFFF.

The

value

indicates no outline, and value FFFF indicates a solid line. Values between 0 and FFFF describe patterns of dots or dashes. There are four reserved words in the fill-style: empty, solid, stipple, and cross. The color-number specifies the color for the layer and is associated with color map. Technology Editor(TED) is able to change the outline-pattern we and fill-style of a layer. To use the Technology ~ditor,

can enter the following command from LED: TED Fig.2.6 shows example TED display. Seven commands are shown in TED display such as edit, buf, color, save, logop, fill, and quit. To edit the color or fill pattern for a layer, select the EDIT command from the TED menu. Color command can change color number. We can use the fill command to change fill-style, use the buf command to store the current stipple and use the logop command to perform logical operations on the current stipple by using the stipples in the buffers. In general, most users will never need to change a technology file. The system manager will change this file when the process is changed or special layer is added. However, a user may change to outline pattern or fill style for a particular layer in the technology file. The CMOS technology file shown in Appendix A-2 is for a regular 13layer EPROM process. Nactive and pactive are drawn layers. When taped out for reticles, the nactive and pactive layers should be merged to form an active layer. The p-field layer is generated from the reverse field of an oversized n-well layer while the p-plus layer is generated from an oversized pactive layer. The n-plus layer is just the reverse field layer of the p-plus layer. A hvim layer is added in the

technology file for 12V or higher while Mhvim is added for voltages between 6 and 12V for EPROM or EEPROM technology. The details of the technology file are described in the following:

Fig.2.5 PED display for a color

Fig.2.6 Example TED display

17
{

This is the typical technology file example for 1.8um CMOS

double-poly, single metal, N-well EPROM process). {The layers shown below are in the order of mask sequence, some are layout drawn layers, some are added layers for the purpose of easier layout drawing and design rule checks).
$

CMOS {specifies specific technology) CMOS.CMP{specifies color map file)

100

0.1

(100 stands for micro meter,

grid

resolution

0. lum) $

Nwell c5c5 empty 8 [layer name,outline-pattern, fill-style, color number]

$

Pfield ffff stipple 1 c) Discussion:

ffff indicates a solid line

Valid workstations use a layer name as a layer instead of using a layer number in the technology file. It is not convenient to run LVS in a layer name system. When running LVS for the top cell, we have to remove the signal name of a subcell.

2.3.4

CMOS layout design rules

The purpose of the design rules are to guarantee the precise layout according to the rules defined by the

specific process. The rules are the worst process deviation: mask misalignment, overetching, spreading of the diffusion,

18 and tolerances of other field oxides etc. More layers will need more layout that design manual rules. checking These rules are so

complicated

becomes

extremely

difficult. Besides that, the more accurate design rule check program must report false errors, which become more

difficult when the number of layers increases. The typical 13-layer CMOS 1.8um EPROM design rules and programs are described below. They can be easily modified for SRAM, DRAM or other technologies. Some basic layout design rules are explained below.
1 Minimum width: In order to prevent the line layer from .

notching or necking, the minimum width for each specific layer is defined; such as minimum width for active, polyl, poly2, or metal layers.
2 H i n h u m spacing: The line to line spacing is defined to .

avoid line shorts or bridging for polyl, poly2 and metal layers. Also, the minimum active spacing is usually

specified to prevent active to active leakage in punchthrough mode. Some larger rules are specified, especially in
1/0 or high voltage areas in EPROM or EEPROM technologies.

In these cases, the HVIM and MHVIM defined in DRC.CMD file are needed to perform special checks.
3.

Overlap:

This check

is for two overlapped

layers.

Normally it is needed to check metal contact, poly contact or active contacts. For different voltages, different

overlap rules are required.

4.

Misalignment:

Misalignment

between

masking

layers

19 determines design rules. There are two kinds of alignments.

1) direct alignment, and 2) indirect alignment. The author

would like to illustrate alignments by using 1.8um CMOS process. In this process, n-well is a major flat layer, active and p-field to n-well are direct alignments, active to p-field is an indirect alignment, polyl, poly2, N+

implant and P+ implant to active are direct alignments. They are in indirect alignments with each other. Contact to poly2, metal to contact and pad to metal are direct

alignments. Fig. 2.7 shows an alignment sequence. It is helpful to us to understand the relation between direct and indirect alignment. The direct alignment has lower

misalignment errors. The design rules of 1.8um CMOS process used by Elite Semiconductor Inc. of San Jose, California are adopted to upgrade O.U. Valid logic system from
nMOS

to

CMOS.

Organization of these rules is discussed in the Appendix

A-3.

Active

P-field

N+ implant

P+ implant

'3
Contact Metal Fig. 2.7 Mask alignment

CHAPTER 3. INSTALLING LVS ON THE SCALD SYSTEM

3.1 Introduction:

It is much more difficult to find layout errors using the naked eye. Instead, we use a computer to process this work. The SCALD star IC Layout Verification System (LVS) can perform the task of verifying IC layout designs. A COMPARE program is in of the an system IC for comparing its electrical

connectivity

layout with

corresponding

schematic representation. The SCALD and system the Graphics Editor (GED) creates creates a

schematics

system

automatically

connectivity file to describe connections of components. We also use Layout Editor (LED) to draw the IC layout. However, an LED layout drawing does not contain electrical

connectivity information, so we use an Extract program to extract connectivity from the layout data. Extract produces an electrical connectivity file in the same format as the
GED schematic connectivity file. Comparing schematics and

layout connectivity files is the primary purpose of COMPARE. ~f circuit elements do not match, we can easily correct layout or schematic errors based on the COMPARE results. Before running the COMPARE program, we need to set up command files for circuit extraction.

3.2 Layout tools section

Assuming that we have completed subcell layout, we have

22

to check if it is a correct layout or not. Both circuit extraction and DRC are performed to eliminate layout hook-up and design rule errors. Before running Extract and DRC, we must first set up two command files: drc.cmd and

extract .cmd. A perfect run of DRC and Extract program will not produce false errors.

3.2.1

The command file structure The command file is created with a UNIX text editor.

There are five sections in the command file: files, layers, hierarchy, extract, and checks. Their order is shown as below:

section
<< files>>
<< layers>>

description location of files list of layers rules for hierarchy rules for EXTRACT rules for DRC

<< hierarchy>>
<< extract>>

<< checks>>

"The files and layers sections must be present in every DRC/Extract command files; the hierarchy, extract, and

checks sections are required only when their associated operations are to be performed. For example, when performing a DRC on a cell, the extract section can be omitted. Typically, a separate command file is created for Design Rule Checks and circuit Extract. Files that do checks are

23

called DRC files, and files that do extraction are called DRC EXTRACT files, [Layout Verification DRC/EXTRACT

REFERENCE MANUAL 2-31.

1 The files section: .

The files section contains all the information about a cell. For example, where each cell is located and what

libraries are used. The files section contains two: a) The Directory and Use commands, and b) The Library command a) The directory and use commands The Directory and Use commands will specify the SCALD directory that contains the cell design data to be

processed. The legal expressions are: Use directory-name Directory-name b) The library command The master library directory can be accessed by using a lib command. The following expression can be used: Lib library-name
2 The layers section: .

There are various types of layers used in the layers section: layers. a) Input layers: Input layers are defined in a technology file. They are also called drawing layers such as n-well, pactive, input layers, intermediate layers and output

nactive, polyl, poly2, contact, metal, sae and vapox for

PD512.

b) Intermediate layers:

Intermediate layers are temporary layers, which are created from combinations of input layers. For example, when two drawing layers overlap, the overlapped area is defined as the intermediate layer used to check layout design rules. c) Output layers: Output layers can be created by using the keep command, and can be written back to the layout data files. Intermediate layers and output layers are created by the geometric operation commands. DRC and Extract command files are completed by these operators, which will be described in the next section.
3. The hierarchy section:

The Hierarchy section is to define the relation between the topcell and a subcell. It is necessary to give subcell a pin-name in order that subcells are able to connect to the topcell.
4.

The extract section: The extract section is to define transistors from the

layout and determine circuit connectivity among devices.

5.

The checks section:

The checks section checks layout for violation of the

design rules.

3.2.2

Geometric operation commands Geometric operation commands are needed in order to

create new layers from combinations of drawing layers. These new layers are used to define transistors or to do DRC checking. These commands are: and, andnot, or, xor, expand, include. The following will explain how these operators

create new layers.

1. The And Command

The AND command can create layer3 by intersection of layerl and layer2 layer3 = layerl and layer2

For example:

Drawing layer

AND operate

Result

layerl

layer2

layer3

2. The OR command

The OR command can be expressed by the following form: layer3

= layer1 or layer2

For example: Drawing layer OR command Result

layer

layer

3. The XOR command

The XOR command creats layer3 from layerl and layer2. Layer3 contains all regions of layerl and layer2, excluding their common part.

layer3 = layerl XOR layer2 For example:

Drawing layer

XOR command

Result

layerl

layer2

4. The ANDNOT command

The ANDNOT command has the following form: Layer3 regions is the layerl with overlap of layerl and layer2 removed. layer3 = layerl ANDNOT layer2

For example:

Drawing layer

ANDNOT command

Result

5. The

Include command

The Include command will copy layerl to layer3 if there are intersections between layerl and layer2,

layer3= layerl For example:

include layer2

Drawing layer

include operate

result

6. The

Expand command

The Expand command will increase or decrease layerl by a distance to produce layer2

expand

layerl distance layer2

For example:

Drawing layer

Expand operate

layer1

layer2

layer2

3.2.3

DRC/Extract

control commands

DRC/Extract control commands control program execution. These control commands are: analysis-name, donut-size, keepupdated, ignore-maskout, flat-cell-size, flat-cell-name and ignore-subcell. They are described below:
1 The wanalysis-namem command .

This command specifies DRC/Extract file to be analyzed and separates the results of DRC/Extract. For example: analysis-name "drew This command lets program execute DRC check instead of executing Extract.
2. The mdonut-sizen command

The purpose of donut-size is to let the program check the overlap of the topcell and subcell instead of rechecking the entire subcell.
A general rule for setting the donut size is:

donut size = overlap-max

+ largest-design-rule

where overlap-max is the maximum allowable cell overlap.

3. The mkeep-updatedn command

If the layout and command file have been changed since

the

last

DRC,

the

keep-updated

command

forces

the

DRC/Extract program to run the DRC/Extract program again.

4.

The wignore-maskoutm command

The ignore-maskout command causes DRC/Extract not to check or extract all layers beneath the mask layer.

5. The nflat-cell-size'

command command will flatten and all cells all

The smaller

flat-cell-size than the

specified

max-size,

flatten

hierarchies below these cells. For example: flat-cell-size

6.0

will flatten all cells below 6.0um.

6. The Nflat-cell-namen command.

This command is expressed by: flat-cell-name namett. For example flat-cell-name

ttcell-

"*"
,
Hignore-multiplen commands

will flatten all cells.

7. The nignore-subcelln

The ignore-subcell command causes DRC and EXTRACT not to check for errors or extract subcell data. The ignoremultiple command causes DRC and EXTRACT to ignore multiple signal names. Since the O.U. LED system is the 8.07 version, it does not have flat-cell-name and ignore-multiple commands.

Therefore, this system is not able to extract flat layout nor to compare the flat netlists.

3.2.4

Hierarchy section commands Hierarchy section commands are to define the relation

between the parent cell and a subcell. These commands are: define-pin, overlap-max, ignore-overlaps and get-subcell-

data commands.
1 The ndefine-pinn command .

The define-pin command causes DRC/EXTRACT to use the user-defined pin area, rather than the machine-generated pin area. Parent cell and subcells make connection through these pin-areas.
2 The noverlap-maxn command .

The overlap-max command defines the maximum allowable amount of overlap between two cells.
3.

The nignore-overlapsn command The ignore-overlaps command causes DRC/Extract to

ignore overlaps.
4.

The nget-subcell-datan command This command causes the DRC and Extract to retrieve

data from the subcellsl abstracts. Above commands will be used by DRC and Extract

programs. Appendix A-4 shows the physical DRC and Extract programs.

3.3

Running COMPARE for LVS Need for LVS The main purpose of running LVS is to determine whether

3.3.1

or not a physical layout matches the schematic. In general, there are two ways to run LVS; one is to run hierarchically, and the other is to run flatly. several parent cells and
A

physical layout includes For hierarchical

subcells.

comparisons, subcells are considered as bodies and only the

35

connectivity among bodies is checked. For flat comparison, parent cells and subcells will be flattened to transistor level, then transistors. Before running LVS, all signal names must be placed in the schematic and the layout for hierarchical and flat comparison. For hierarchical comparison, the schematic must be a ".spiceH name, and it can only use nMOS or PMOS parts from the spice library. For each nMOS or PMOS, power(VCC) and GND(VSS) signals must be attached. The symbol(.body) of every hierarchy level must have power and GND pins and the
It.

COMPARE will

check the connectivity among

logic and .spiceIf

must have VCC\I and VSS\I, and the wafer substrate signal is still a global signal, but must be attached to every part.

3.3.2

Hierarchical design for LVS

In general, hierarchical design must be used in VLSI circuits. There are several benefits for using hierarchical designs: a. savings in memory space b. Easy check for LVS errors c. Reduction in program execution time Therefore, most large chips are designed

hierarchically. For hierarchical extraction, every cell must have signal names, which will become the pin names of a body. The pins of a cell are defined by donut area and pin-area layer which is the drawing layer of LED. An

inverter is used to explain a pin name and signal name. Fig.3.1 shows the signal names of a schematic and layout of a CMOS inverter. Fig. 3.2 shows the pin names of a body of a CMOS inverter. A test circuit shown in Fig.3.3 is used to show the relationship between parent cell (test) and subcell (inverter). Fig. 3.4 shows the body of parent cell (test). In hierarchical design, pin and overlay are the two ways to define the relationship between 1) parent cell and subcell 2) subcell and subcell 3) primitive and subcell
1 Parent cell and subcell )

Parent cell and subcell can only make connections through these pin-areas. The parent cell will only read the abstract data (abstract.l.extract) and not the whole subcell layout data. The abstract data of a subcell is the layout area defined by "pin-areaw. Pin-area logical operations or pin-area layer. is created through In other words, the

parent cell can only see the pin areas of the subcell.
2) Subcell and subcell

There are overlaps between subcell and subcell. The command "OVERLAP-MAX max-numflin the extract command file is used to control any extract errors of the overlaps, and max-num should be set up to twice of the pin-area defined. For example: create_pin=boundary andnot (boundary expand -12.0) pin-area=pin-area or creategin OVERLAP-MAX 24.0 If the overlap of subcell and subcell is smaller than

Schematic

layout
INVEIlyout-bin.1 .I

pactive
P O ~ Y

mactive
..

contact cell boundary

metal

Fig.3.1 The pin names of a CMOS inverter

Schematic
VCC

OUT

VSS

layout

Fig.3.2 The schematic body and the layout extract of a CMOS inverter.

Schematic
VCC\I

TEST\lyout-bin.1 ..I

layout

Fig.3.3 The relation between parent cell and subcell

Schematic

Test

Fig. 3.4 The schematic body and layout extract of test (parent cell)

41

twenty four, the connection can be made between them. If the overlap is greater than the OVERLAP-MAX and there is no other way around, use the pin-area layer to create a bigger pin.
3) primitive and subcell

If primitives

(hard data) overlap the subcell, the

primitives have to touch the pin of the subcell. In order to run hierarchical LVS, the body name must be the same for schematics (GED) and layout, and the pin names (signal names) must be the same. The several rules for putting the signal names are as follows:
1 Put names inside the edge of the cell .

(so not to enlarge the boundary of the cell)

2 Keep .
n+ll

and signal name text together

(for easy identification)

3. Put signal names on every named net

i.e, if there are two nets that have the same name put signal name on every one of them.
4.

Put signal names as close to the cell edge as possible (so it will become the pin and at the cell edge)

5.

Put signal names on primitives (hard data): If it is within 12um of the cell edge, it does not need the pin-area.

6 Put signal names on each subcell: .

a. Must be on the pins of the subcell

b Put pin-area layer to overlap the signal .

name

c. Choose the place closest to the parent cell

edge When running the comparison on hierarchical, the layout designer has to satisfy the four rules shown in the

following figures, however, the four rules may be ignored if compare is run on a flat design.

Layout Rule 1:
Do not make device in different cells. Example : A nMOS device which has nactive in one cell and polysilicon in another cell is not allowed.

native

cell B

Not an nMOS

Layout Rule 2:
Do not make contact connection of different in different cells layers

Example : Metal and polysilicon connect through contact. Can not have polysilicon and contact in a cell, and metal in another cell.

I I-

- - p o l y s i l i c o n -----I I

cell A
metal
--7
I I I I I I I

cell B

polysilico

contact
I I I I
I

--*

I I

No connection between metal and polysilicon

Layout Rule 3:
Do not make connection of the same layer in different cells. Example : A metal net was discontinued in a cell A.

If you connect this layer on the top level, the extract program will not extract right.

Cell A

Cell B
Do not fix in cell B Fix in cell A

Layout Rule 4:
Put a proper shape of boundary layer in every cell.

Example : An error in connectivity can not be detected without proper boundary.

pin areak/I/A
I

L,--,,-,-,--

4.1
.,-----.
I

boundary

A short will not be detected without proper boundary.

3.3.3

~unningCompare procedure Fig.3.5 shows the procedure for running a comparison

program. Before running the comparison, a cell layout is extracted to generate a connectivity file (lyout cn.l.1) and a spice connectivity file (spice-cn.1.1) is generated when the schematic is written out. The COMPARE program will compare spice-cn.l.1 and lyout-cn.l.1. The two key points for running compare are summarized below:
1 Put both schematic and layout in the same cell name . -

directory For example: cell-name/lyout-bin.l.1 lyout-cn.l.1 logic-bn.l.1 logic-cn.l.1 logic-dp.l.1

2 To run compare hierarchically .

a. drc cell-name extract.cmd b. compare cell-name spice-cn.l.1 lyout-cn.l.1 It will automatically find spice-cn.l.1 and lyout-cn.l.1 and

under cell-name directory and compare them. Fig.3.6

Fig.3.7 represent the schematic and layout, respectively. Fig.3.8 is the result of the comparison.

LAYOUT EDITOR

GRAPHICS EDITOR

I
7

CELL DESCRIPTION

*
DRCI EXTRACT

CONNECTIVITY FILE

logic-cn.1.I
or
CONNECTIVITY FlLE

'

lyout-cn.1.I

Fig. 3.5 The procedure for running compare

DRAWING TITLE=RSDEC

LAS?JE!?W~ ~ c t M

00a 38 39 1 9 ~ 9

Fig 36 Schematic of a RSDEC circuit .

..

I?;.

3 7 I . a p o u ~f i f

a HSDEC c i r c u i t

SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:08:49 PST 1988). Processing rsdech/logic cn.l.1 Processing rsdech/lyout-cn.l.1 Generating Body Table

BODYTABLE

*********

Name

Number Name .................................................................... 1

1

Nuabe r

invel inve2 nand3 Num Of Bodies N u m Of S i ~ n a l s

1
3 8

inve 1 inve 2 nand3 Num Of Bodies Num Of Signals

3 8

Comparing rsdech/logic cn.l.1 rsdech/lyout cn.l.1 inve 1 inve2 nand3

vss

inve 1 inve2 nand3

un52
unS 7

unSlSinvelS3pSinp unSlSinve2S2pSinp a6s a5s a48 an

VCC

un56
unS 3 unt 5

un54 un58
unS 1

The Circuits Match.

Fig.3.8 The result of the compariion

CHAPTER 4. DESIGN EXAMPLE

4.1 New product release procedure

The ability of a semiconductor company to be a main supplier of its products, depends on release the new

products as quickly as possible. However, the products must be reliable and complete with published specifications. This section outlines a typical release procedure for a new product in semiconductor companies. The procedure describes the product development process from the design stage to the full production status. The following is the list of stages, which a product will go through from the product design to full production release status:
1. Engineering proposal
2. Design

3 Development .
4 Simulation or prototype development .
5.

Pilot production

1 Engineering proposal .

The design engineer develops an internal proposal for the product design based on the marketing definition of the product and available fabrication processes. This proposal should be reviewed by marketing and process engineering departments. The preliminary Design Review should address the following issues: a) Product development

b) Product specifications

c) Product development schedules

d) Cost objectives e) Competitive and manufacturing cost analysis

A full scale design project will be initiated upon

successful completion of the Design Review. That is,

marketing, process engineering and manufacturing engineering must agree with the product specifications and development strategies.
2. Design phase

A complete design cycle is initiated

to execute the

design. Sufficient analytical work shall be completed. This will ensure that the final design meets The the product design

objective

specification.

following product

analysis tasks should be completed prior to a preliminary design review: a) Simulation studies(i.e., design models, process models etc.)
b) Breadboard circuit test results and layout constraints

c) Discussion of the expected areas of difficulty in meeting the applicable product specifications d) Special or new (if any) manufacturing requirements
e) Unique material requirements
f) Review of all the current manufacturing factors and

levels
h) Revised development schedule

54

3 Development .

Once the design concept is reviewed and approved, full scale development of the product is authorized. Design for initial prototyping (i.e l prototype wafer) , process

specifications and test specifications, as well as test methodologies, must be identified during this phase. At this stage, the new product facilitator must select the team members from the functional groups. This team includes a marketing engineer, design engineer, product engineer,

process engineer, test engineer and assurance engineer. It is

reliability/quality the quality

important that

assurance engineer and reliability engineer become formally involved at this stage of the development to review the actions necessary to fully evaluate the reliability of the product and identify any special concerns about outgoing quality levels. Furthermore, the product development team must consider all the factors and levels of manufacturing variability to overcome the problems of variability. In order to overcome the problems of manufacturing variability, design and product engineering departments must prepare product characterization plans, which apply to the methods of experimental design. Exit from the development stage is through the critical design review, which addresses all issues regarding the development phase. At a minimum, the following shall be reviewed:

a) Product development report (i.e., define design rules,

layout and cell simulation)

55

b) Process development report (i e. , process models and process architecture)

c) Define manufacturing factors and levels affecting the

product design
d) Test parameters specifications

e) Cost projection
f) Reliability projections

g) Revised schedule (if applicable)

4.

Simulation or Prototype Development Simulation or prototyping of a new product design is

the responsibility of the design engineering group. At this stage, the design engineer should work closely with the process engineer in developing appropriate circuit models, which will be utilized in the product design. This may involve building special kit parts and subcells of the product. Furthermore, the design engineer using simulation, must include AC and DC performance evaluations of the

product. In summary, the prototype stage is completed when the following items are done:

a) The design report showing test data from the

prototypes, specifically compare the test data with both the simulation and breadboard data. Simulation results might be adequate on projects which require

complex breadboards. b) The design action report must show the areas of redesign needed prior to pilot production. The designer must document all the process model

parameters used during the

simulation. These

process model parameters must be reviewed and approved by process engineering and wafer fabrication engineering departments. c) The product quality plan giving requirements for reliability evaluations and product quality control requirements.
d) A preliminary product specification developed by a

marketing representative based on the design engineer's feasibility report. A marketing representative will be responsible for identifying a product introduction plan. e) A test development project must be able to test the product parameters. This test development will be used to characterize the product performance and eventually, it will be transferred to production testing.
5.

Pilot production The purpose of pilot production is to evaluate the

product

performance

prior

to

production

release.

The

initial production lot will be reviewed by the design engineer for compliance with the design objective should

specifications

Moreover, the

product

engineer

assume primary responsibility for the product and support from design engineering at this time. plan should be designed to
A

statistical sample the product

characterize

characteristics in a package. Exit from pilot production to full production status requires completion of the following

57

items: a) Product and process engineering analyses yields problems in any pilot production lots. This will include any design modifications requested from design engineering to support volume production.
b) Review of the product characterization report.

c) All requirements specified in the quality plan for the product and reliability report.
d) Release product development document package.
e) Final data sheet limits.

In conclusion, a new product release will take

five

steps from engineering proposal to pilot production. The next section will give an example of a new product design.

4.2

Example of predecoder design (PD512)

4 2 1 Introduction ..

PD512 is a standard industrial predecoder for memory chips. The author likes to present a chip design procedure by using this design example. This design procedure starts from specification of functional blocks, through simulation, layout, LVS, DRC to taping out the chip. The author chose 1.8um CMOS technology for this chip. Fig.4.1 shows the IC design procedure. The product can be developed by interconnecting several sub cells. Each subcell presents a functional block of the PD512 system. The intention of this example is to develop the key functional blocks for the system.

CIRCUIT DEFINITION PROCESS DEFINITION

I
I

I
A

IC
PROCESS DEVELOPMENTISIMULATION

It
DEVICE CHARACTERIZATION

+
I

FUNCTIONAL PARTITIONINGISIMULATION

I LOGIC

DESlGNlSlMULATlON

CIRCUIT SCHEMATIC CIRCUIT SIMULATION

-77LAYOUT DESIGN

LAYOUT DIGITIZATION TO GENERATE COMPUTERIZED LAYOUT DATA BASE

1. LAYOUT DESIGN RULE CHECKING 2. CONSISTENCY CHECKING BETWEEN LAYOUT AND CIRCUIT SCHEMATIC

IC
IC MASK PATTERN GENERATION

lC PROCESS

Fig.4.1 The IC design procedure

59

The PD512 has automatic power-down capability which is controlled by the chip enable signal(CEB). When CEB goes high, the device automatically powers down and remains in a low-power stand by mode. This unique feature provides

substantial system level power savings.

4.2.2

Process definition and development

1 Poly-gate CMOS process architecture .

The objective of this section is to define a simple nwell process architecture, which can be used to fabricate the functional cells described in the next section. This describes each sequence required in the fabrication process. The basic characteristics of this process are as follows: a. It is an n-well process
b. It provides two layers of connections; one poly and on

metal. c. It offers medium scale integration because it uses very simple transistor structures and the process can be used for high voltage by increasing the gate length in proportion to the depletion width. d. It requires that the N-wells and the substrate are connected to VCC and VSS respectively. Such connections are needed to prevent latch up. This standard poly-gate CMOS process can be an

excellent process for the implementation of large circuits such as PD512. The explanation for each process step is listed above the cross sectional diagrams.

CMOS EPROM PROCESS CROSS SECTION

1. INITIAL OXIDATION ( 5000A )

2. N-WELL MASKIOXIDE ETCHIN-WELL IMPLANT(ph0s)

PHOS

3. N-WELL DRIVE ( 3000A OXIDE IN WELL )

\
4.

N-WELL

OXIDE ETCH /PAD OXIDATION (350A) INITRIDE DEPOSITION (1 500A)

N-WELL

5. ACTIVE MASK1 NITRIDE ETCH NITRIDE

N-WELL

/
BORON

OADE

6. P-FIELD MASK 1 P-FIELD IMPLANT (BORON) NITRIDE

7. FIELD OXIDATION (8500A)INITRIDE & PAD OXIDE STRIP

8. SCRlFlClAL OXIDATION (150A)l OXIDE ETCH

N-WELL

I
FOX

9. CELL IMPLANT MASK1 CELL IMPLANT (BORON)

10. DEPLETION IMPLANT MASKIDEPLETION IMPLANT (AS.) AS.

N-WELL

/
POLY1

I 1 .FIRST GATE OXIDATION (350A)l POLY1 DEP &DOPE

12. POLY1 MASK1 POLY1 ETCH

13. FIRST GATE OXIDE ETCHIVT ADJ. IMPLANT (BORON)

14. SECOND GATE OXIDATION (350A)l POLY2 DEP. & DOPE 1 POLY2 OXIDATION (450A)

N-WELL

15. POLY2 MASK1 POLY2 OXIDE AND POLY2 ETCH 1 INTERPOLY OXIDE ETCH PR

16. SAE MASK1 POLY1 ETCH

17. SID OXIDATION

(150A) POLY2 POLYI

18. N+ SID IMPLANT MASKI N+ SID IMPLANT AS.

N-WELL

19. SID RE-OXIDATION(25OA)I P+ SID IMPLANT MASK IP+ SID IMPLANT (BORON)

20. BPSG DEP. (9000A) I FLOW (9256) BPSG

E m

21. CONTACT MASK / CONTACT ETCH POLY2 POLYI

22. METAL SPUTTER /METAL MASK / METAL ETCH

E q
METAL OXIDE SID POLY2

@g
POLYI

N-WELL

2 Parameter Determination and description for simulation .

Accurate specifying

circuit

simulation meaningful

is

only

possible As

by the

accurate

and

parameters.

process varies from time to time, model parameters must be measured for the typical transistors as well as the worst case. The parameters are extracted manually or

automatically. The extracted parameters shown in Appendix A-5 are written in a file for the spice program and are as described below:

Name
F1

Units V/cm

Description Mobility reduction field Measured minus drawn channel width Represents the oxide thickness Exponent for mobility reduction due to source-drain electric field

WDEL TOX MBL

m
A exponent

LAMBDA
KU

cm/v flag m ohms ohms V

Channel length modulation Velocity saturation switch Measured minus drawn channel length Drain resistance Source resistance The threshold voltage at zero substrate bias

LDEL RD RS VTO

GAMMA

V**O. 5 cm**2/v-sec meter

Surface threshold parameter Low field bulk mobility Lateral diffusion into channel from source and drain diffusion

UB LATD

FDS

Field drain to source, controls reduction of threshold due to sourcedrain electric field. default=O

WIC

Weak

inversion

equation

selection

Default=O.O (no weak inversion) MOB

CLM

Mobility equation selector.Default=O Channel length modulation equation

selector. Default=O meter Fringing field factor for gate-to source and gate-to-drain overlap capacitance calculation LDIF CF1 volts Length of lightly doped diffusion Modified Meyer control for transition from depletion to weak inversion for CGSO CGSO F/meter Gate-source overlap capacitance per meter channel width
TRD

l/deg K

Temperature resistor

coefficient

for

drain

TRS

l/deg K

Temperature resistor

coefficient

for

source

TCV

v/deg K

Threshold voltage temperature coefficient

BEX

EXPON

Temperature exponent; BEX is defined as UO temperature exponent, correction for UO (low field mobility)

LMLT

factor

Length multiplier

68

WMLT PHI

factor V

Diffusion layer shrink reduction Surface potential

4.2.3

Functional design of PD512

1 Functional partitioning .

The functional design of the PD512 product is based on the poly-gate high voltage CMOS process. The process is assumed to have a minimum device length of 3um for high voltage, 1.8um for low voltage. PD512 contains an input buffer, R-decoder, S-decoder, Clock, VPISW and XT decoder. The input buffer is TTL

compatible. It is designed to communicate between a CMOS circuit and a TTL circuit. R-decoder and S-decoder are predecoders. A clock circuit is able to generate 2OMHZ to 3OMHZ signals to supply XT decoders and VPISW. VPISW can switch VCC(5V) but to VPP(12V). pump XT decoders to are put also high

predecoders,

have

circuits

voltage(l2V) on word lines when circuits are in the program mode. A functional block diagram of the PD512 system is illustrated in Fig. 4.2. A computer simulation was performed for the key functional blocks of PD512.
2. Circuit schematic and simulation

a) Input buffer section An input buffer is used to interface a TTL level signal from the outside to the inside of a CMOS chip, it is TTL compatible. The TTL high logic level is only 2.4V and low logic level is 0.4V. However, the CMOS level is 5V for high

CEB

A4T-A9T

A1 2 T - A 1 4 T

AIHVPGMB AlHV LGDISTB

INPUT BUFFER CLOCK

i

A8,A13,A14

A7,A9,A12

A6,A5,PL4 CLK7B CL1C5 CLK7 OEBT GHV CL (SB

' I
S DECODER sots7

R DECODER

' I ' I VPlSW

I

*
r
XTDEC

ROfR7

I
XTDEC

VPI

' I

r rv

v
XTNO-XTN7 XTNO-XTN7

FIG.4.2 A FUNCTION BLOCK DIAGRAM OF THE PD512 SYSTEM

70 logic level and OV for low logic level. An ordinary CMOS inverter switches when the input voltage is about 0.5 VDD, and the TTL switching threshold should be at 1.4V for a

typical process. CMOS input buffer circuits and layout are shown respectively in Figs. 4.3 and 4.4. circuit In addition, the

simulation results and LVS results are shown in

Appendix B- 1.
b) R-decoder and S-decoder section

R-decoder and S-decoders include one Nand-3

and two

inverters. Inverter 1 is bigger for driving larger loads. Figs.4.5 and 4.6 show the schematic and layout of R-decoder

and S decoder. The LVS result is shown in Appendix B-2, there are six address lines to be fed into them, such as A 8 , A13 and A14 for R-decoder and A4, A5 and A6 for S-decoder. Their decoder schemes are shown below:

Fig.4.3 Schematic of a Input Buffer

& .

fig. 4 - 4 :,ayout o f an Input buFfor c i t 4 ~ s i t

DRAWING RS DECODER RS DECODER LAST-MODlFlED=Fri

Sep 28 13:17:31

1989

Fig. 4.5 Schematic of R- and S-decoder circuits

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"7

S-Decoder O/P SO s1 S2 S3 S4 55 S6 57

A6

A5

A4

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

c) XT decoder section (XTDEC) The main purpose of XTDEC is to select the word lines of EPROM cells. There are two modes for this circuit; one is read mode, the other is program mode. In read mode, XTDEC will put 5V on the selected word lines. In program mode XTDEC will put 16V on the selected word lines. There are eight inputs to be fed into XTEDC; VPI, CLK7, CLK7B, A9X, A12XI A7XI GDISTB and GHVB. XTN and XTNB are the outputs of XTDEC, VPI signal comes from VPISW circuit. A9X, A7X, and A12X are from address buffers. GDISTB and GHVB are from MIS and GHVBS. VPI will be 5V in read mode, and will be 12V in program mode. CLK7 and CLK7B will be active in program mode and inactive in read mode. A9X, A7X and A12 are select

signals. GDISTB and GHVB are logic signals. XTDEC circuit simulation results are summarized below: mode read

VPI

CLK7

CLK7B

GDISTB

GHVB A7 ,A9 ,A12X XTN XTNB 5V OV 5V 5V 5V 15V OV OV

5V inactive inactive active

5V 5V

program 12V active

76 This circuit pumps XTDEC circuit from 9.822V to 15.75VI and it takes just 500ns. In addition, the schematic and layout are shown in Fig.4.7 and Fig.4.8, respectively. Refer to Appendix B-3 for the complete XTDEC Spice simulation and LVS result.
d) VPI switch section(VP1SW) :

VPISW circuit is capable of switching VPI from 5V to 12V. VPI will supply 5V to XTDEC in read mode, and 12V to XTDEC in the program mode. There are 4 inputs and 1 output in VPISW; OEBT, GHV, CLK5, CLK5B and VPI. OEBT is external pin, and it is TTL low(0.4V) in the read mode and 12V in the program mode. CLK5 and CLK5B are active in the program mode and inactive in the read mode. The function of CLK5 and 5B are to pump the device 29p1s gate voltage to 12V. The spice circuit simulation results for VPISW are summarized below:

mode

OEBT

GHV
0

CLK5

CLK5B

VPI 5V 12V

read program

VIL(O.4V) 12V

inactive inactive active active

5V

Fig.4.9

and Fig.4.10

shows the VPISW schematic and

VPISW cell layout. VPISW Spice simulation and LVS results are shown in Appendix B-4. e) CLOCK section: The CLOCK circuit will produce four important output signals; CLK7, CLK7B, CLK5 and CLK5B. CLK7 and CLK7B are fed into XTDEC, and CLK5, 5B are fed into VPISW. The main

Fig.4.7

Schematic of a XTDEC circuit

Fig.4.9 Schematic of a VPISW circuit

81 purpose of the four signals is to pump circuits from 5V to 12V when circuits need a higher voltage. The CLOCK circuit also as four inputs; VPI, AlHV, AIHVPGMB and LGDISTB. VPI signal comes from VPISW circuit. AlHV is from address buffer one (Al), when A1 is supplied a high voltage, AlHV will go to 5V. Otherwise, AlHV will always be OV. The spice circuit simulation results for the CLOCK circuit are summarized below:
mode
VPI
AIHV

AIHVPGWB

LGDISTB

CLK7.7B

CLK5.5B

read program

5V 12V

OV OV

5V OV

5V 5V

active active

active active

In addition, the schematic and layout are shown in Fig.4.11 and 4.12, respectively. Refer to Appendix B-5 for the complete clock Spice simulation and LVS results.

a3
Fig.4.11

Schematic of a CLOCK circui

c x A P T m 5 CONCLUSION .

The purpose of this thesis was to install an advanced CMOS technology, layout versus schematic system (LVS), and develop a design example (PD512). The thesis objective is achieved in these three parts. A new 1.8micron n-WELL CMOS EPROM process technology is used to upgrade Valid workstation from nMOS to CMOS. In general, the process for memory chips is more complex than the process for logic chips. For logic chips, this process can be reduced several steps such as cell implant, polyl deposition, and polyl etch. This process provides two layers of connections: one is a poly2 layer, the other is a metal layer. If a designer needs one more layer for connections, the designer can use polyl. This means, the polyl deposition will be needed. Developing DRC program is very important work in VLSI design. It must be able to find the violation of a layout, because DRC violation will cause a failure design. Some DRC false errors may be produced by DRC

program. These false errors can be eliminated by modifying the DRC program. In order to make the old SCALD system COMPARE version 1.3L operating, the author had to use the spice library to set up a CMOS library. With this work, the designer will be able to verify the layout of chips. The successful chips will be determined by the correct layout. In general, the verification of the layout includes the device size and

85

connectivity checking. The version 1.3L COMPARE is only able to check the device connectivity. Further improvements for device size checking may be made in the future if the old COMPARE version is upgraded to new the version. In Chapter 4 of this thesis, the author demonstrates the phases of a semiconductor product development process by developing a 512k predecoder called PD512. The author has focused on the following product development stages.

a) New product release procedures

b) CMOS poly gate process architecture development

c) Design and simulation of the key functional blocks

REFERENCE

Neil Weste and Kamran Eshraghian, ttPrinciples CMOS of VLSI Design

Systems

Perspectivett, Addison-

Wesley, Inc., 1985. Amar Mukherjes, ttIntroductionto nMOS Systems Designtt, Prentice
&

CMOS VLSI

- Hall, 1986.
Product Life Cyclestt,

Robert H. Hayes and Steven G Wheelwright "Linking Manufacturing Harvard Process and

Business Review, January 1981.

D. Hodges and H. Jackson, ttAnalysisand Design of Digital Integrated circuitttMCGrow Hill, New York,
1983.

T.

Frederiksen,

"Intuitive IC

CMOS

Evolutionlt ,

National P. Allen

Semiconductor Technology Series, 1984. and D. Holberg, ttCMOS Analog Circuit

Designw, Holt, Rinehart and Winston Inc. New York,

1988.

J. Maver and P.B. Denyer, "Introduction to MOS LSI

Designw, Addition
1983.

Wesly,

Reading,

Massachuselts,

ItLayout EDITOR

Reference

Manualts, Valid

logic

systems, Incorporated, California, 1986. Paul Richman, "MOS Field-Effect Transistors and

Integrated Circuitstt. Masakazu Srojit "CMOS DIGITAL CIRCUIT TECHNOLOGYIt ,

87

PRENTICE HALL, INC., NJ, 1988.

11.

Dewitt G. Ong, "MODERN MOS TECHNOLOGYn, Mcgraw-Hill, Inc, 1984.

12.

Punknell. Eshraghian, "Basic VLSI Design-Systems and

circuit^^^, PRENTICE HALL, 1988.

13.

"SCALD Language Valid COMPILERw, Valid Logic Systems, INC., California, 1986. VerificationI1, Valid 1986. Logic systems INC.,

14.

"Layout

California,

APPENDIX A
A-1

CMOS c o l o r m a p f i l e

0 0 0 0 193 190 248 1 5 246 0 2 228 1 7 1 1 7 3 1 3 21 250 4 140 80 150 5 5 2 60 250 6 110 110 180 7 255 255 0 8 200 80 80 9 60 170 0 10 140 100 40 1 1 49 89 240 12 120 80 150 13 80 127 100 14 100 85 105 15 239 0 0 16 120 100 0 17 235 130 0 18 100 80 0 19 108 127 1 1 7 20 100 80 0 21 150 197 0 22 100 80 0 23 150 130 0 24 110 90 0 25 150 130 0 26 100 80 0 27 150 130 0 28 100 80 0 29 150 130 0 30 100 80 0 31 255 255 255 32 100 100 100 33 0 255 255 63 255 255 255 127 243 249 247 128 200 200 200 129 250 0 0 130 255 180 120 131 250 250 250 132 250 0 0 191 255 255 255 192 3 3 3 250 255 255 255 251 0 180 0 252 200 200 200 253 255 255 255 254 0 240 0 255 -6 -6 -106 256

A-2

CMOS technology f i l e

888
100 0 . 1 0 2 polyl 0 s o l i d 1 "wire-width" = "2" " p r e f i x "

= "PI:"

pf ffff stipple 2 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0 "wire-width" = "2" nactive "wire metal
n u i r e

0 solid 2 = " 2 " Wprefix" 0 solid 4

""

= "2" "prefix" = "M:"

pactive 0 solid 8 " w i r e - w i d t h " = "2" " p r e f i x "

= "" = "P2:"

poly2 0 s o l i d 16 "wire-width" = "0.6" "p r e f i x "

,
contact f f f f cross 32 " w i r e - w i d t h " = "2" " p r e f i x "

= ""

d e p l e t i o n f 9 f 9 empty 16 "wire-width" = "2" "prefix" r "" nwell c5c5 empty 8 " w i r e w i d t h " = "2" " p r e f i x " = " " c e l l f 0 f 0 empty 4 " w i r e w i d t h n = "2" " p r e f i x n pad
9

= ""

i f 0 0 empty 16 i f f f empty 16

sac

active f f f f .tipple 4 240 240 240 420 810 1008 c007 0 0 c007 1008 810 420 240 240 240

,
pplus f f f f s t i p p l e 8 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080
>

n p l u s f f f f s t i p p l e 16 ffffOOOOOOOffffOOOOOOO hvim f f f f s t i p p l e 2 101 202 404 808 1010 2020 4040 8080 101 202 404 808 1010 2020 4040 8080 mhvim f f f f s t i p p l e 8 ffff O O O O O O O f f f f 0 0 0 0 0 0 0 pfield f f f f stipple 1 240 240 240 420 810 1008 coo7 0 0 coo7 1008 810 420 240 240 240 errors ffff stipple 8 0 1020 2040 0 0 808 404 0 0 2020 4040 0 0 404 202 0

networks fff stipple 34 0 606 606 0 0 6060 6060 0 0 606 606 U 0 6060 ti060 0 boundary ffff eeptv 36 "cif name" = "L BND1" pin-.area ffff stipple 38 1 2 4 8 10 20 40 80 100 200 400 800 1000 2000 4000 B O O 0 "cif name" = "L B N D 2 " terminal ffff cross "cif-name" ="L TRH" 39

maskout fff s t i p p l e 33 ECCC C C C C 3333 3333 CCCC CCCC 3333 3333 CCCC CCCC 3 3 3 3 3333 C C C C C C C C 3 3 3 3 3333 cif-name" = "L MA"

A-3 CMOS design rules 1 0 Purpose: .

To define a set of design rules for 1 8 micron N-WELL . CMOS EPROM process technology. The rules are capable of handling up to 10% linear shrink.

2.0 Drawn layers:

Layer name n-WELL Active N Active P Active Cell Implant Poly I Depl Implant Poly I1 SAE

Description

GDS layer
1

Both n+ and p+ diffusion

41 2 12
5
6

n+ diffusion region
p+ diffusion region EPROM cell threshold adjustment Used as the floating gate To open up depletion transistor Control gate and peripheral gate Etch protection during self align poly etch

11 42

P+ Implant Contact Metal Pad

Open up p diffusion area

30 .

Remaining layers: Description

GDS layer

Layer name Active P-f ield N+ Implant

Merge of n active and p active Oversizing n-WELL by 3.5u/side Same data as P+ Implant

41 21 14

4 0 Mask set required and alignment sequence: .

Mask name

P.R. Field D C C
D

Align to major flat 1

1

n-WELL Active p-f ield Cell implant POLY I Depletion implant POLY I1
SAE

D C D
C

n+ implant p+ implant Contact Metal Pad

D
D C D

5 0 Generalized layout rules .

Assumption: 5.0.1 The drawn dimension equals the physical dimension on the wafer. There is dimension skew for some layers to compensate for process/etching bias. 5.0.2 Direct misalignment on stepper---------- 0 . 5 ~ Indirect misalignment on stepper-------- 0 . 7 ~ 5.0.3 All units listed below are in microns. 5.0.4 Design greater than the minimum is preferred, whenever a more conservative layout will not impact the chip size. 5.0.5 Any deviation from these design rules must be fully documented for review at the time of the composite review.

5.1 N-WELL LAYER 5.1.1 Minimum width 5.1.2 Minimum spacing

N-WELL

N-WELL

5.2 ACTIUE LAYER

5.2.1 Minimum width 5.2.2 Minimum spacing 5.2.2.1 Low voltage 5.2.2.2 High voltage 5.2.2.3 Medium high voltage 5.2.3 N+ diffusion outside well to well 5.2.4 N+ diffusion inside well to well 5.2.5 P+ diffusion outside well to well 5.2.6 P+ diffusion inside well to well

t LOW

5.2.2.1 High 5.2.2.2 Medium 5.2.2.3

I I I I

I :
I I I I

L.... ..... .\..=....I

5.3 CELL IMPLANT LAVER

5.3.1 Minimum ouerlap of POLY 2 gate 5.3.2 Minimum ouerlap of diffusion (ACTIUE) 5.3.3 Minimum spacing to unrelated diffusion

1 .O

2.0 2 .O

AGUOVE

\/
YYYYY
YYYlYYYYYYYYYYYYYYlYYYllYlY

5.381
Y

;I
Y

1I

Y Y

l e , 8 5.3.2
X Y
~YYYYYY.Y'!YYYYYYYY.LYYY!'YYY.YYYY

POLY 2

*\

IMPLANT

5.4 POLY 1 LAYER 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 Minimum gate length f o r natiue transistor Minimum spacing Minimum POLY I extension onto field Minimum spacing o f POLY I on field to unrelated diffusion Minimum spacing o f extended POLY I onto field to diffusion Minimum ouerlap o f diffusion at drain side in memory core Minimum diffusion extension from POLY I Minimum ouerlap o f channel in core Minimum POLY I width

POLY

I-r

.
C A

' x
E

.C .

.*\

UE I

5.5 DEPLETION IMPLANT LAYER

5.1.1 Minimum oveerlap o f gate in the direction o f current flow 2 .O 2.0 5.5.2 Minimum spacing to unrelated diffusion

POLY 2

5.6 POLY2 LAYER 5.6.1 M i n i m u m g a t e l e n g t h 5.6.1.1 L o w voltage and core 5.6.1.2 High u o l t a g e 5.6.2 M i n i m u m spacing 5.6.3 M i n i m u m POLY2 extension o n t o f i e l d 5.6.4 M i n i m u m spacing f r o m POLY2 on f i e l d t o unrelated diffusion 5.6.5 M i n i m u m spacing f r o m end cap t o unrelated diffusion 5.6.6 M i n i m u m overlap o f d i f f u s i o n 5.6.7 M i n i m u m POLY2 w i d t h

5.7 ETCH PROTECTION LAYER

5.7.1 Minimum spacing t o c o r e POLY I I 5.7.2 Minimum spacing t o core POLY I

Y I

POLY 2

E7C)
Y..

. L

5.8 P+ IMPLANT L A Y E R

5.8.1 Minimum overlap on P+ diffusion

1.4

5.8.2 Minimum spacing to N+ diffusion

1.4

IMPLANT

5.9 CONTACT L A Y E R 5.9.1 Minimum contact size 5.9.2 Minimum spacing 5.9.3 Minimum ouerlap of diffusion 5.9.3.1 Peripheral 5.9.3.2 Core 5.9.4 Minimum spacing from diffusion contact to gate 5.9.5 Minimum ouerlap to : 5.9.5.1 POLY I I 5.9.5.2 POLY I without POLY l l cross 5.9.5.3 POLY I with POLY I I cross 5.9.6 A l l POLY contact location field oxide only

5.1 0 METAL L A Y E R 5.1 0.1 Minimum width 5.1 0.2 Minimum spacing 5.10 3 Minimum ouerlap o f contact

METAL

&

POL

5 1 1 PAD L A Y E R . 5 1 1.1 Minimum size . 100~100 5.0 5 1 1.2 Minimum overlap to metal . 5 1 1.3 Minimum spacing . 110 5 1 1 4 Minimum spacing from pad metal to . . scribe lane 30 5 1 1.5 Minimum spacing from pad metal to . 20 unrelated metal 5.1 1.6 Minimum spacing from pad m e t a l to 15 diffusion and poly

S C R I B E LANE

METAL

DIFFUSION

A-4

The Extract and DRC program

(512K EPROM 1 1 / 8 8 ) { E x t r a c t command f i l e f o r

{

1 . 8 m i c r o n CMOS p r o c e s s )

11/14/88 YR change p 2 n g a t e n o t i n c l u d i n g p o l y l add b a d p g a t e check

<<
<<

files

>>

use epal.wrk layers

>>

pactive active n a c t f ve depletion ~ 0 1 ~ 1 p o l YZ meta 1 PP 1 u s nwel 1 contact

Pf

pad pfield { intermedtate P4 nenh penh ndep natv ngate p 1n g a t e p2ngate p9ate psubcont nwe 1 1c o n t P sd nsd badpgate substrate creategtn

LAYERS

>

<<
{

hierarchy

>>

read-cover-file 1 drf t n e gt n c r e a t e g i n = b o u n d a r y a n d n o t ( b o u n d a r y expand - 4 0 . 0 ) pfn-areampin-area or c r e a t e g l n

analysis-name "extract" keep-updated dont-reanalyze flat-cell-name "*"

{

Ignore-subcell flat-cell-stze

"dramcell" 6.0

donut-size 12.0 consoltdate edge-1 i m i t 300000 prefix prefix preftx prefix prefix

" M : " meta 1 "PZ:" ~ 0 1 ~ 2 "NA:" nsd "PA:" p s d "Pl:" ~ 0 1 ~ 1

p l n g a t e = ( p o l y l and a c t i v e ) a n d n o t n w e l l p2ngate= ( ( p o l y Z andnot p o l y l and a c t i v e ) andnot n w e l l n a c t i v e = a c t i v e andnot p p l u s n g a t e = p l o y Z and n a c t i v e n d e p = n g a t e and d e p l e t i o n nenh=ngate andnot d e p l e t i o n n s d = n a c t i v e andnot n g a t e p a c t i v e = a c t i v e and p p l u s p g a t e = p o l y 2 and p a c t i v e p e n h r n w e l l and p g a t e psd=pactive andnot pgate
(

ndep= p 2 n g a t e and d e p l e t i o n nenh= p 2 n g a t e a n d n o t ndep n a t v = p l n g a t e andnot d e p l e t i o n n s d l a c t i v e andnot ( p l n g a t e o r pZngate) p g a t e = ( a c t i v e and p o l y 2 ) and n w e l l p e n h = ( p g a t e and n w e l l ) a n d n o t p f p 4 = ( p g a t e and n w e l l ) and p f p s d = a c t i v e andnot pgate

>

~ s u b c o n t = ~ ( a c t f va n d n o t n w e l l ) a n d c o n t a c t e n w e l l c o n t = ~ n w e l land a c t i v e ) a n d c o n t a c t (touch substrate) t o u c h s u b s t r a t e psubcont touch nwell nwellcont t o u c h c o n t a c t metal p o l y l p o l y 2 psd nsd touch metal psubcont nwellcont

transistor transistor transistor transistor transistor

NMOS NMOS NMOS PMOS PMOS

NENH NDEP NATV PENH P4

nenh ndep natv penh p4

nsd nsd nsd psd psd

poly2 poly2 polyl poly2 poly2

substrate substrate substrate nwell nwell

<< <<

checks end

>>

>>

f i l e s >> u s e eprom512.wrk

<<

<< layers pact ive nact ive depletion ~ 0 1 ~ 1 p o l YZ meta 1 nwel 1 contact pad hvim mhv i m

>>

intermediate pimp11 pimp12

P O ~ Y ~ 0 1 ~ s error-layer spa ana active hvact nothvact mhvact notmhvact 1v a c t mhvnac dumact nwpp 1 us nwnp 1us PWPP 1us pwnp 1 us s b a c t 1 ve nwnsd nwpsd pwnsd pwpsd

LAYERS

gate1 gateb gate2 hvgate gate depgate nwgate pwgate ngate pgate badngate badpgatel badpgate2 ncont pcont p 1cont p2cont meta 1c o n t notpolycont notmetalcont notactcont polyconnect

<<

hierarchy

>>

def i n e g i n ignore-multiple "VCC. ignore~rnultiple" V S S " ignore-multiple "VPP" extract >> { O p e r a t i o n f o r isolation^ donut-size 2 0 . 0

<<

(checks-only) prefix "P2:" ~ 0 1 ~ 2 p r e f i x " M i " metal get-subcell-data get-subcell-data get-subcell-data get-subcell-data get-subcell-data get-subcell-data get-subcel 1-data keep-updated nactive pactive polyl poly2 metal contact nwel 1

{nsd and p s d in nwell a n d pwell a r e s e p e r a t e l y d e f l n e d 1 poly=polyl or poly2 a n a - n a c t i v e a n d n o t ( p a c t f v e e x p a n d 1.4) a p a - a c t i v e a n d ( p a c t i v e e x p a n d 1.4) n w n p l u s = a n a a n d nwell n w p p l u s - a p a a n d nwell nwgate=polyZ a n d (nwnplus or nwpplus) nwnsd=nwnplus andnot nwgate n w p s d = ( ( n w e l l and a c t i v e ) and ( p a c t i v e e x p a n d 1.4)) a n d n o t n w g a t e pwnplus=ana andnot nwnplus pwpplus=apa andnot nwpplus pwgate=poly2 and (pwnplus or pwpplus) pwnsd=pwnplus andnot pwgate pwpsd=pwpplus andnot pwgate poly=polyl or poly2 notpolycont=contact andnot poly p o l y s = p o l y l a n d ( p o l y 2 e x p a n d 1.0) t o u c h c o n t a c t metal n w n s d n w p s d touch contact metal pwnsd pwpsd
(

touch contact metal mhvact notmhvact t o u c h c o n t a c t metal h v a c t n o t h v a c t t o u c h c o n t a c t metal n o t a c t c o n t a c t i v e t o u c h c o n t a c t m e t a 1 notpol y c o n t pol y touch polys polyl edge-spacfng n w n s d n w p s d 2.8 error-layer different-node report-edge error-layer 'nwnplus t o n w p p l u s a t d i f f n o d e SPACING < 2.8. e d g p s p a c i n g p w n s d p w p s d 2.8 error-layer different-node report-edge error-layer 'pwnplus t o p w p p l u s a t d i f f n o d e s p a c i n g <2.8' edge-spacing p o l y s p o l y s 5000.8 error-layer same-node poly report-edge error-layer ' d l f f p o l y 2 t o u c h t h e s a m e p o l y l 2
(

edge-spacing h v a c t n o t h v a c t 3.8 error-layer different-node report-edge error-layer 'hvacttve t o a11 a c t l v e s p a c i n g a t d l f f n o d e edge-spacing m h v a c t n o t m h v a c t 3.8 error-layer different-node report-edge error-layer " m h v a c t i v e t o all a c t i v e s p a c i n g a t d i f f n o d e edge-spacing n o t a c t c o n t a c t i v e 2.0 error-layer dffferent-node report-edge error-layer " c o n t a c t t o a c t i v e S P A C I N G <2.0 d i f f e r e n t n o d e g

edge-spacing n o t p o l y c o n t p o l y 2 . 0 error-layer different-node " report-edge error-layer " c o n t a c t t o p o l y S P A C I N G d i f f e r e n t n o d e

<<

<

2.0"

checks

>>

analysis-name "drc" donut-size 20.0 defer-cell-edge overlap-max 150.0 edge-limit 3 0 0 0 0 0 keep-updated flat-cell-size flat-cell-name flat-cell-name flat-cell-name ignore-subcell 6.0 "ylgrg" "xtprg "rsprg" "epromarray"

( O p e r a t i o n for isolation^ a c t i v e = p a c t i v e or n a c t i v e a n a r n a c t i v e a n d n o t ( p a c t i v e expand-octagon sbactive = active fnclude poly h v a c t = h v i m and a c t i v e nothvact=active andnot hvim m h v a c t = m h v i m and a c t i v e notmhvact=active andnot mhvact lvact=active andnot hvact m h v n a c = m h v i m and n a c t i v e dumact=active andnot mhvnac g a t e l - p o l y l and p w n p l u s g a t e b = p o l y 2 and a c t i v e gatezrgateb andnot gate1 h v g a t e = g a t e 2 and h v a c t gate=gatel or gate2 d e p g a t e = ( p o l y 2 and d e p l e t i o n ) a n d a n a b a d n g a t e = n g a t e and nwell b a d p g a t e l x p g a t e a n d n o t nwell b a d p g a t e 2 z p g a t e and d e p l e t l o n n g a t e = p o l y and a n a pgate=poly and apa p i m p l l = p a c t i v e expand-octagon p i m p l 2 = p a c t l v e expand-octagon ncont=ana and contact p c o n t o a p a and c o n t a c t plcont=polyl and contact p2cont=poly2 and contact m e t a l c o n t = c o n t a c t and m e t a l polyconnect=poly andnot actlve notmetalcont=contact andnot metal notactcont=contact andnot active
0.9

1.4)

2.6

{Design Rules Start f r o m here) (1.6 nwell check) error-edge-style w i d t h nwell 3 . 0 'nwell W I D T H < 3 . 0 ' (1.a) error-edge-style s p a c i n g nwell nwell 12.6 " n w e l l t o nwell S P A C I N G

<

12.0'

C1.b)

(2.6 a c t i v e check) error-box-style (2.a) w i d t h a c t i v e 1.8 'active W I D T H < 1.8' error-edge-style e n c l o s u r e n w p p l u s nwell 3.2 " p p l u s o v e r nwell S P A C I N G

<

3.2'

C2.d)

error-edge-style spacing pwpplus nwell 4.0 'pplus outside nwell to nwell SPACING < 4.0' C2.e) error-edge-style spacing pwnplus nwell 9.5 ignore-touching "nplus outside nwell to nwell SPACING error-edge-style spacing pwnplus nwpplus 12.7 *nplus in psub to pplus in nwell SPACING < 12.7"
{

3.0 pfield no check)

{depletion check) error-box-style enclosure depgate depletion 2.0 "depletion to gate spacing < 2.0" error-edge-style spacfng depletion gate 2.0 ignore-overlaps "depletion to unrelated gate

<

2.8"

< 6.0 poly check) error-edge-style wfdth poly 1.8 "poly WIDTH < 1.8" {6.a) error-edge-style spacing polyl polyl 2.0 "polyl to polyl SPACING < 2.0" C6.b) error-edge-style spacing poly2 poly2 2.0 'poly2 to poly2 SPACING < 2.0" (6.b) error-edge-style edge-enclosure gate poly 2.5 error-layer ignore-touching ignort-outsfde report-edge error-layer "poly extension onto field WIDTH < 2.0 C6.f) error-edge-style spacing polyconnect actfve 6.2 fgnore-touchfng "poly on ffeld to active error-box-style width gate1 3.0 "polyl in gate WIDTH < 3.5" (6. ) edge-enclosure gate active 2.0 error-layer ignore-touching ignore-outslde error-edge-style report-edge error-layer "gate in active < 2.0" (6.f)
{

error-edge-style spacfng ngate pactive 2.1 "ngate to pactive SPACING

1

<

2.1"

existence badngate "BADngate in nwelln existence badpgatel 'BADpgate outslde nwell" existence badpgate2 "BADpgate in depletionn {contactact check? error-box-style width ncont 1.8 "nactive contact WIDTH < 1.8' {13.a) error-box-style width pcont 1.8 "pactive contact WIDTH < 1.8' {13.a) error-box-style . ' <13.a) width contact 1.8 "contact WIDTH < 1 8 error-edge-style . ' (13.b) spacing contact contact 1.8 "contact to contact SPACING < 1 8 error-box-style .' enclosure plcont polyl 1.0 'contact over polyl < 1 0 {13.e> error-box-style enclosure p2cont poly2 1 0 'contact over poly2 < 1 0 {13.e) . .' error-box-style . enclosure pcont apa 1 0 "contact overlaps with actual pactfve<lu ' error-box-style . enclosure ncont ana 1 0 ignore-touchfng 'contact overlaps with actual error-edge-style spactng contact gate 2 . 0 *contact to gate SPACING < 2 9 . ' {13.g> error-edge-style . ' C13.s) spacing notmetalcont metal 2.0 'contact to metal' SPACING < 2 0 {metal check) error-edge-style wldth metal 2.5 "metal WIDTH < 2.5" (l4.a) error-edge-style spacing metal metal 2.8 check-for-notch 'metal to metal SPACING error-box-style enclosure metalcont metal 0.8 "contact over metal SPACING < 0.8' < < end > >

<

28 .' Zl4.c)

C14.b)

A-5

Spice parameters for simulation

Sk A h 1 P-{'HANkEL.

FMODEL.EPH .MODEL P PMOS Fl=U.14 kDEL.=U. 2 TOX-223 ES4T= 15.E4 MBL=O.36 + LAMRL)A=3.7E-5h b = I .U3 LDEL=-0.2 RD=470 RS=470 + VY=-U.65 C;..lMM4=U. ' LIh-230 LATI)=O,1 I.'DS=0.17 WIC=l MOE)=l 27 + Ci,M=3 METO=U . 0 5 L D I F = , Z CF1-0.24 CF2=0.62 CF3=1 TR1)=2 .UE-3 + TRS=Z.OE-3 T C ' L = - 2 . i E - 3 REX=-1.3 + CJ.4=O.JE-I5 CJP=0.31E-15 EXAz0.5 EXPZ0.33 + A C M = Z PHl=0.6 SFAST ENHANCEMENT N-CHANNEL .MODEL N NMOS F1=0.12 WDEL-0.2 TOXs225 ESAT=S.4E4 MBLs0.32 VT=0.5 GAHMA=0.45 + LGAMMA=O.lI VBO=1.3 UB=710 LATDzO.1 FDSz0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RD=320 RS=320 WIC=l MOB=1 CLM=3 METO=0.05 + LDIF=2 CF1=0.12 CF2=0.52 CF3=1.36 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 + CJA=0.07E-15 CJP=0.24E-15 EXAx0.48 EXP=0.27 + PHI=0.4 ACM=2 SFAST EhH4NCEYFNT N-CHANNEL Flz0.12 WDEL=O.Z 1,OX-225E S A I = ~ . ~ E ~ MBL=0.32 VTz2.0 GAMMA=O.45 .MODEL NC NMOS + LGAMMA=U.1 I \;BO=l. ijB=710 LATD=O,I C'US=0.92 l,AHBUA=J.3E-5 3 + KU=1.21 LDELr-0.2 RD=320 HS=320 kIC=l MOB=l CLM=3 METU=0.05 + LDIF=2 CF1=0.12 CF2=0.52 CF3~1.36 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 + CJA=0.07E-15 CJP=0.24E-15 EXAz0.48 EXP=0.27 + PHI=0.4 ACM=2 SFAST ENHANCEMENT N-CHANNEL depletion FlrO.12 WDELx0.2 TUX=225 ESAl=5.4E4 MBL-0.32 VT=-3.0 G A M H A = O . ~ ~ .MODEL nD NMOS + LGAMMA=O.lI VBO=1.3 UBt7lO LATDrO.1 FDSs0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RDs320 RS=320 WIC=l MOB=1 CLM=3 METO=0.05 + LDIF=2 CFl10.12 CF210.52 CF3-1.36 + TRD=2.OE-3 TRS=Z.OE-3 BEX=-1.3 TCV-2.2E-3 + CJAt0.07E-15 CJP=O.24E-15 EXA=0.48 EXP-0.27 + ACM=2 PHI=O.4 SFAST NMOS CELL modifv epalcell 3.2 /1.4 cellmodel .MODEL ERA NMOS PHIn0.29 VT-0.9 GAJ4MA=0.8 FDS=0.51 Flr0.031 ESAT=6.5E+4 + LAMBDA=2.2E-6 KLz0.08 F3=0.54 KA11.09 MBLz0.4 MAL=0.55 + KUs1.7 LATDt0.22 CLM=3 MOB=l WIC=l LDEL=-0.25 WDELz0.7 + BETA=30.8E-6 RS=320 RD1320 LDIF=3 + TRDr2.OE-3 TRS=P.OE-3 BEXI-1.3 TCVz2.2E-3 SFAST NMOS CELL modify epalcell 3.2 /1.4 cellmodel .MODEL PRO NMOS PHl=O.OY VTz6.0 GAMMA=O.8 FDSt0.51 F1=0.031 ESAT=6.5E+4 + LAMBb4-2.2E-6 KL=O.OB F3~0.54 KAtl.09 MBLrO.4 MALz0.55 + KU=]. 7 LA'FD=O.'LZ ('LM=.i MOb=l ~ J L ' - 1 LDEL=-0.25 kbEL=O.7 + BETA=30.8E-6 RS=320 RDr320 LDIF=3 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV12.2E-3 .ENDL FMODEL.EPR

.LIB

SEPHOM FSMODEL . L 1 B FSMODEL. EPR $FAST P-CHANNEL Fl=O.lJ WDEL=0.2 TOX=225 ESAT=15.E4 MBLz0.36 .MODEL P PMOS t LAMBDA=3.7E-5 KU=1.03 LDEL=-0.2 RD=470 RS=470 + VT=-0.65 GAMMA=0.27,UB=230 LATDzO.1 FDSz0.17 VIC=l MOB=l t CLM=3 METO=O.O5 LDI'F=~ CF1=0.24 CF2~0.62 CF3=1 TRD=2.OE-3 t TRSz2.0E-3 TCV=-2.7.E-3 BEX=-1.3 + CJA=0.3E-15 CJP=0.37E-15 EXA=O.5 EXP=0.33 + PHI=0.6 ACM=2 SSLOW ENHANCEMENT N-CHANNEL .MODEI, N NMOS F l z 0 . 1 4 6 WI)k I . = - . 2 T O X = Z i 5 ESAT=.).8E4 MBL=O. 39 VTz0.9 GAMMAZO. 55 t LsGAMMA=O. 3 V R O = I . I UB=590 LATD=O. 1 FDS=O.76 LAMBDA=2.7E-5 1 t IiU=1.01 LDEL=0.2 RD=400 RS=400 WIC=l MOB=I CLM=3 WETO=O,lS + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 t TRDz2.OE-3 TRSs2.OE-3 BEX+-1.3 TCVs2.2E-3 t CJA=O.l3E-15 CJP=0.42E-15 EXA=0.42 EXP=O.21 + PHI=O.6 ACM=2

s
SSLOV ENHANCEMENT OFF-CELL .MODEL NC NMOS F1=0.146 WDEL=-.2 TOX=275 ESATr4.8E4 MBL=0.39 VT=6 GAMMA=0.55 + LGAMMA=0.13 VBO=1.1 UB=590 LATD=O.l FDSn0.76 LAWBDA=2.7E-5 + KU=1.01 LDEL=O.2 RD=400 RS=4OO WIC=l MOB=1 CLM=3 METO=0.15 + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 + TRD=2.OE-3 TRS=Z.OE-3 BEXt-1.3 TCVz2.26-3 + CJAz0.13E-15 CJPn0.42E-15 EXA=O.42 EXPt0.21 + PHI=0.8 ACM=2 SSLOW ERASBLE CELL .MODEL ERA NMOS PHI=0.29 VT=1.2 GAMMAt1.2 FDS=O.41 F1=0.037 ESAT=6.1E+4 + LAMBDA=1.8E-6 KLzO.1 F3r0.44 KA=1.33 UBL=0.46 MALt0.45 + KU=1.5 LATD-0.18 CLM=3 MOB=l WIC=l LDEL=-0.21 WDEL=0.58 + BETA=28.8E-6 RS=4OO RDg400 LDIF=3 + TRD=2.OE-3 TRS=2.OE-3 BEXI-1.3 TCV=2.2E-3 SSLOW PROGRAM CELL .MODEL PRO NMOS PHI=0.29 VT=6.0 GAMMA=l.2 FDS=O.41 Pl=0.037 ESAT=6.lE+4 + LAMBDAz1.8E-6 KL=O.l F3=0.44 KA=1.33 HBL=0.46 ML10.45 + KUz1.5 LATDtO.18 CLM=3 MOB=l W C 1 I. LDEL=-0.21 WDELr0.58 + BETA=28.8E-6 RS=400 RD=4OO LDIF=3 t TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3

SEPHOM
.LlH
SSLOk
SCMODbI . F P R

P-CHANYEL .MODEL P PMOS k1=0.18 kDEL=-0.2 TOXz275 ESAT=l 2.F4 MBI,=(J.44 + LAMBDA=J. 1E-5 K b = 1 . 01 LDEI,=O.2 RD=57O HS=570 + VT=-1.05 GAMMA=0.33 UB=190 LATDz0.1 FDSz0.13 WLC=I MOB=1 + CLM=3 METO=O.l5 LDIF.2 CFls0.48 CF2=0.38 C F 3 ~ 0 . 7 6 TRD=Z.OE-3 + TRS=2.OE-3 TC\=-2.7E-3 BEX=-1.3 + CJAz0.36E-15 CJP=0.49E-15 EXA=0.47 EXPZ0.27 t ACM=2 PHI=l SFAST ENHANCEMENT N-CHANNEL .MODEL N NMOS F 1 ~ 0 . 1 2kDELz0.2 TOX=225 ESAT=5.4E4 MBL=0.32 VTz0.5 GAMMA=0.45 + LGAMMA-0.11 VBO=1.3 UB=710 LATDzO.1 FDSz0.92 LAMBDAz3.3E-5 + KU=1.21 LDEL=-0.2 RD=320 RS=320 WIC=I MOB=l CLM=3 METO=0.05 + LDIF=2 CFlz0.12 CF2=0.52 CF3=1.36 t TRD=Z.OE-3 TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3 t CJA=0.07E-15 CJP=0.24E-15 EXA=0.48 EXPz0.27 t ACM=2 PHI.0.4 SFAST ENHANCEMENT OFF-CELL F1=0.12 WDEL=(J.2 TOX=225 ESATz5.4E4 MBLz0.32 VT=6 GAMMA=0.45 .MODEL NC NMOS + LGAMMA=O.ll VB011.3 UB=710 LATD=O.l FDSz0.92 LAMBDAz3.3E-5 t KU=1.21 LDEL=-0.2 RD=320 RSs320 WIC=l MOB=l CLM=3 METO=0.05 t LDIF=2 CF1=0.12 CF2=0.52 CF3=1.36 + TRDz2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJA=O.OIE-15 CJP=0.24E-15 EXAz0.48 EXP10.27 + ACM=2 PHIz0.4 SFAST ERASBLE CELL .MODEL ERA NMOS PHI=0.29 VT=0.9 GAMMA=0.8 FDS=0.51 F1=0.031 ESAT=6.SE+IS t LAMBDA=2.2E-6 KL=O.O8 F3i0.54 KA=1.09 MBL=0.4 MAL=0.55 t KUrl.7 LATDz0.22 CLM=3 MOB=l WIC=l LDEL=-0.25 WDEL=0.7 t BETAr30.8E-6 RS=320 LDIF=3 + TRDz2.OE-3 TRSs2.OE-3 BEXI-1.3 TCVz2.2E-3 SFAST PROGRAM CELL .MODEL PRO N M O S . PHIr0.29 VT=6,0 GAMMA-0.8 FDS-0.51 F1=0.031 ESAT=6.51+4 + LAHBDA=2.2E-6 KL=O.OB F3-0.54 KArl.09 MBLzO.4 MALs0.55 + KUtl.7 LATDs0.22 CLM-3 W B = l WIC=l LDEL=-0.25 WDELo0.7 + BETAz30.8E-6 RS=320 LDIF-3 + TRDz2.03-3 TRS=2.OE-3 BEXI-1.3 TCV=2.2E-3

t
,

.ENDL

SFHODEL. EPR

STYPI C'4L P-CHANNEL . Ll tc TMODEI, EPH MC)DE.I, P PMOS Fl=U.16 WDEL=O. 'T'0.\=25UESAl'=13.5E4 MB1,=0.4 + LAMBDAr3.4E-5 KU=l.U2 LI)EL=O. RL)=SZO RS=520 t iT=-0.85 GAMMA=0.3 UB=210 LATDzO.1 FDSZO.15 WIC=l MOB=1 + CLH-3 METO=O.I LUlFsZ CFlz0.36 CF2~0.5 C F 3 ~ 0 . 8 8TRDz2.OE-3 + TRSz2.0E-3 TC\=-2.7t'-3HEX=-1.3 + t'JA=O. .(3E-15 CJP=O..LJE-I5EXAZ0.5 EXP=O.3 + ACH=Z PHI=O.8 S+ LMLT=0.9 WMLT-0.9

ENHANCEMENT N-CHANNEL Flz0.133 WDEL=O 1'O.Y=250C:SU"5.1E.I MBL=0.355 VTz0.7 GAHNA=0.5 NMOS LGAMMA=O.l2 VBOz1.2 UB=650 LATDzO.1 FDSz0.84 LAMBDAz3E-5 KU=l.l LDEL=O RD=dtiO RS=360 WIC=1 MOB=l CLM=3 METO=O.l LDIF=2 CF1=0.24 CF2=0.4 CF3=1.12 LMLT=O .9 WMLT=O.9 TKr1=2.0E-3TRS=2.OE-3 BEX=-1.3 TCVz2.2E-3 CJA=O.lE-15 CJPz0.39E-15 EXA=O.45 EXPz0.24 ACM=2 PH1=0.6

STYPICAL ERASEABLE CELL .MODEL ERA NMOS PHI=0.32 VT=1.05 GAMMA=1.0 FDS=0.46 F1~0.034 ESAT=6.3E+4 t LAMBDA=2.0E-6 KL=0.09 F3=0.49 KA=1.21 MBLz0.43 UAL=0.5 + KU=1.6 LATD=0.2 CLM-3 MOB=1 WIC=l LDEL=-0.23 WDELr0.64 t BETA=29.8E-6 RS=360 RD=360 LDIF=3 + TCV=2.OE-3 TRD=2.OE-3 TRSz2.OE-3 BEX=-1.3

STYPICAL PROGRAMMING CELL .MODEL pro NMOS PH1=0.32 VT=6v GAMMA=l.O FDS=0.46 F1=0.034 ESAT=6.3E+4 t LAMBDA=2.0E-6 KL=0.09 F3=0.49 KA=1.21 MBL=0.43 NALz0.5 + KUz1.6 LATDz0.2 CLM=3 HOB=I,WIC=l LDEL=-0.23 WDELz0.64 + BETAz29.8E-6 RS=360 RD=360 LDIF=3 + TCVz2.OE-3 TRD-2.OE-3 TRS-2.OE-3 BEX=-1.3 STYPICAL DEP N-CHANNEL CELL F1=0.02 WDEL=-0.14 TOX=250 ESAT=2.3E4 NBLo0.26 VT=-2 G A M W A = O . ~ ~ .MODEL ND NMOS i LGAMMA=0.3 VBO=1.53 UB=560 LATDzO.1 FDSz1.37 LAMRDAz3.7E-6 + KU=l.l LDEL=O RD=360 RS=360 WIC=I MOB=l CLM=l HETO=O.l t LDIF=2 CF1=0.24 CF2=0.4 CF3s1.12 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCVs2.2E-3 t CJA=O.lE-15 CJP=0.33E-15 EXAr0.45 EXP=0.24 t ACM=2 PHI=0.36 ENDL TNODEL.EPR

P-CH4NNE1, SMOUt L. EPH .MODLI. P PMOS Fl = O . 18 !dI,EL=-0.2 7OX=275 E,dr\7'=12. E4 MBLzO. 44 t LAMBUA=J.IE-5 k U = 1 .01 LDEL=0.2 HD=570 RS=570 t VT=-1.05 GAMMA=0.33 UB=lYU LA'I'D=O.I FDS=U.13 WIC=1 MOB=1 t CLM=3 MFTO=0.15 LDIF=Z CFl=O.IH C F 2 ~ 0 . 3 8C F 3 ~ 0 . 7 6 TRD=Z.OE-3 t TRSz2.OE-3 TCV=-2.7E-3 BEX=-1.3 t CJA=0.36E-15 cJP=0.49~-15ExA~0.47 EXPz0.27 t ACH=2 PHI=0.8
SSl,Ok

.L i H

SSLOW ENHANCEMENT N-CHANNEL .MODEL N NMOS F1=0.146 WDEL=-.2 TOX=275 ESAT=4.8E4 MBL=0.39 VT=0.9 GAMMA=0.55 t LGAMM4=0.13 VBO=l.l UH=590 LATDzO.1 FDSz0.76 LAMBDAz2.7E-5 t KU=1.01 LDEL=O.2 RD=400 RS=400 UIC=l MOB=l CLM=3 HETO=0.15 + LDIF=2 CF1=0.36 CF2=0.23 CF3=0.88 + TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJAz0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=0.21 t ACM=2 PHI =O.6 SS1,OU ENHANCEHENT N-CHANNEL FOR OFF CELL .MODEL ND NMOS F1~0.146 WDEL=-.2 TOXz275 ESAT=4.8E4 MB1,=0.39 VT=-2.0 t GAMMA=O. 55 t LGAl(nA=0.13 VBO=1.1 UB=590 L A T D = O . ~ FDS=0.76 LAMBDA=2.7E-5 + KU=1.01 LDEL=0.2 RD=400 RS=400 WIC=1 MOB=l CLM=3 METO=0.15 t LDIF=2 CFl=O.Q6 CF2~0.23 CF3~0.88 t TRD=2.OE-3 TRS=2.OE-3 BEX=-1.3 TCV=2.2E-3 t CJA=0.13E-15 CJP=0.42E-15 EXA=0.42 EXP=O.21 + ACM=2 PHI=O.6 SSLOW ERA CELL .MODEL ERA NMOS PBI=0.35 VT=1.2 GAHMA=1.2 FDS=0.41 Fl=0.037 ESAT=6.lE+4 LAMBDAz1.8E-6 KLzO.1 F3=0.44 KA=1.33 HBLsO.46 MAL10.45 KU=1.5 LATDrO.18 CLMz3 UOBrl WlC=l LDEL=-0.21 WDEL10.58 BETAs28.8E-6 RS=4OO RD=4OO LDIF=3 TCVs2.2E-3 BEX=-1.3 TRD=P.OE-3 TRSz2.OE-3

+
+ +
SSLOW PRO CELL .MODEL PRO NMOS

+ + + +

PHI'=o.~~ VT=6.0 GAMMAsl.2 FDS=0.41 Flr0.037 ESAT=6.1E+4

LAMBDA=l.EE-6 KLtO.1 F3r0.44 KA=1.33 MBLtO.46 WLx0.45 KU11.5 LATDz0.18 CLH=3 UOB=l WIC=l LDEL=-0.21 WDELs0.58 BETA=28.8E-6 RS=4OO RD=4OO LDIFr3 TCV12.2E-3 BEXI-1.3 TRDt2.OE-3 TRSs2.OE-3

.ENDL

SMODEL. EPR

APPENDIX B

B-1 The circuit simulation results and LVS results of a

input buffer circuit
****** ****** rabuf ****** ******
h s p t c e 8807a c o p y r i g h t 1988 m e t a - s o f t w a r e , l n c . input l i s t i n g 2:11:14 27-Jan89 *****slte:elite

u n 1 x

*****

. o p t i o n p o s t aspec . w i d t h outm80 .model c j n d cja.0.1 cjp.0.33 e x r = 8 . 4 5 exp=#.24 vcc 9 0 5 % ceb 7 $ a n t 10 S anb 8 % an 6 v 7 7 1 1 p u ( 5 0 Sns 2 n s 2 n s 8 0 n s 9 0 n s ) v l 0 1 0 1 1 p u ( 0 . 8 2.4 l 0 n s 2 n s 2 n s 2 0 n s 4 0 n s ) vsub 5 0 0 v s s 11 0 0 . t r a n I n s 80ns . t e m p 25 . p l o t t r a n v ( 7 ) ~ ( 1 0 )v ( 8 ) v ( 6 ) ml 1 0 11 11 5 nenh wr58.8 1-4 m2 3 2 1 1 5 n e n h ~ ~ 3 l. e0 . 8 1 m3 4 3 1 1 5 n e n h wa15 1 ~ 1 . 8 m4 6 4 1 1 5 n e n h w.75 1=1.8 m5 9 2 3 9 p e n h w = l 0 1-1.8 m 6 8 3 1 1 5 n e n h w.75 1.1.8 m 7 9 3 4 9 p e n h w=20 1 - 1 . 8 m8 9 4 6 9 p e n h w a l l 0 1 - 1 . 8 m9 9 3 8 9 p e n h w = 1 4 0 1 ~ 1 . 8 m l 0 2 1 0 1 1 5 n e n h w = 1 0 0 113 m l l 2 7 1 1 5 n e n h w-10 1-1.8 m12 1 2 1 0 2 9 p e n h w.25 113 m13 9 7 12 9 p e n h w=30 113 .end

pht-d.6

SCALDsystem COMPARE Ver 9.2 SUN3-P1 (Tue Mar 15 01:08:49 Processing rabuf.lyout Processing rabuf.sptce Generattng Body Table rabuf.lyout BODYTABL E
--------------------------------------------------------------------------,

PST 1988).

Name

Number Name Number -------------------------------------------------------------------------

Num Of Bod tes Num Of Sfgnals

13 11

Num Of Bodtes Num. Of S igna 1 s

Comparing rabuf.lyout rabuf.sptce ant wafersubstrate pmos#25.00/3.00#penh pmos#30.00/3.00+penh pmos#140.00/1.80+penh pmos#140.00/1.80~penh pmos#l0.00/1.80~penh pmos#20.00/1.80bpenh nmos#58.80/4.00#nenh nrnos#75.00/1.80i?nenh nmos#75.00/1.80i?nenh nmos#l0.00/1.80#nenh nmos#l00.'00/3.00#nenh nmos#l5.00/1.80#nenh nmos#30.00/1.80#nenh unS3 unS4 unS9 unSl un95 unSll unS2 unS6 unS7
Tha Circuttm M a t c h .

ant wafersubstrate pmos#25.00/3.00#penh pmos*30.00/3.00#penh pmos#140.00/1.80#penh pmos#140.00/1.80#penh pmos#l0.00/1.80#penh pmos#20.00/1.80#penh nmos#58.80/4.00#nenh nmos#75.00/1.80#nenh nmos#75.00/1.80#nenh nmos#l0.00/1.80#nenh nmos#l00.00/3.00#nenh nmos#l5.00/1.80#nenh nmos#30.00/1.80#nenh un%lSinveSSpSout<0> unSlSinveSSpSout<0>
(rabufnor2.4p)t~nSlSp.nh
VCC

unSlSlnveS5pSinp<0> cob VS s an . anb

B-2 The LVS result of R-decoder and S-decoder

SCALDsystem COMPARE Ver 9.2 SUN3-PI (Tue Mar 15 01:08:49 Processing rsdec.spice Processing rsdec.lyout Generating Body Table rsdec.spice BODYTABLE

PST 1988).

*********

Name

Number Name .........................................................................

Num

Num Of eodfes Num Of Signals

1 0
11

Num Of Bodies Num Of Signals

Comparing rsdec.spfce rsdec.lyout a 6s a5s

a4s.
VCC

wafersubstrate sn

-matching---> -matching---> -matching---> -matching---> -matching---> -matching--->

a6s a5s a4s

VCC

wafersubstrate sn vss pmos#l0.00/1.80Bpenh pmos#l0.00/1.80#penh pmos#l0.00/1.80#penh nmos#34.90/1.80#nenh nmos#34.90/1.80#nenh nmos#34.90/1.801nenh pmos#30.00/1.80#penh nmos#15.00L1.80+nenh pmos#80.00/1.80#penh nmos#125.00/1.80#nenh
unS5

unS4 un$6 unS7

Tho C f r c u i t s Watch.

8 - 3 T h e s p i c e s i m u l a t i o n and LVS r e s u l t o f a XTDEC

circuit
,

Cop~r.iCltr 1 ir,.
nirl

* * x i * *

4 - S o t t i ; a r ~ .I I I C . ' = * * * s

t * : r L~ ~ e

+i+++

******
.bJdT

xtjeC

lnatlt I 1 s t l n g **a*** .opt l o n n o q t R S D ~ C

vcc
Y

q i c~al o n e x p i r e s t

YUUH

h 0\lt=8() (i 5

X
$

LIJ1

1U

x t n 11 S l t n b 16 S c l k i 14
S c l k 7 b 17 s a?)\ (1 S al2xlZ

S aix 7 S Q d i s t b 1H

S ghvb 1 5 v10 10 0 12 v8 8 0 5 v12 1 2 0 5 v7 7 0 5 vl8 18 0 5 - 1 5 15 0 0 v l 4 1 4 0 v u ( 0 7 . 5 l O n s 4011s l o o n s 2 0 n s 17011s) \ 1 7 17 O PU( 7 . 5 0 lOns l 0 O n s 4Ons 2017s 1 7 0 n s ) vsub 3 0 0 v s s 13 0 0 . t r a n 5 n s 5OOns . t e m p 25 .plot t r a n v t l l ) vi17) ~ ( 2 6 1 1 x 7 ~ 1 1 1 1 1 1 7 ) ~ ) ~ . p r i n t tran v 1 2 6 l v ( 2 7 1 v 1 2 ) ~ ( 1 1 ) m1 26 2 0 1 3 3 n e n h w=12 1 = 3 . 5 mZ 1 0 2 6 2 0 10 p e n h w = 5 . 8 1 = 3 . 5 m d 1 0 20 2 6 l u p e n h w=6 1 = 3 . 5 m4 21 1 6 1 3 3 n e n h w = 1 5 L = 2 . 5 m5 1 1 1 1 2 1 3 n e n h w=15 1 ~ 2 . 5 16 22 9 1 1 3 n d e p w = 1 0 4 . 1 0 3 1 = 3 . 0 6 2 m i . 15 22 3 n d e p w = 1 2 0 1 - 3 . 5 i m H 1 0 26 27 3 n e n h w=6 1=20 8 9 6 Y 2 0 3 n a t v w=30 1 = 3 m i 0 2 7 27 2 3 n a t v w = 5 4 . 1 9 1 1 = 4 . 7 2 1 a l l 2 2 1 1 3 n a t v w=54.194 1 = 4 . 7 2 1 m12 1 7 2 1 7 3 n a t v w = 2 3 . 2 1 = 4 3 . 3 0 6 0 1 3 14 27 1 4 3 n a t v w = 2 3 . 2 1 = 4 3 . 3 0 6 m14 5 6 1 3 3 n e n h w = 1 0 2 . 3 1 1 1 = 1 . 8 0 5 m l 5 1 6 4 1.3 3 n e n h w = 1 0 0 . 5 1 = 1 . 8 m16 9 6 5 9 p e n h w = 2 5 9 . 8 1 = 1 . 8 a 1 7 9 4 1 6 9 penh w=130.2 1 = 1 . 8 a 1 8 6 4 1 3 3 n e n h w=40 1 = 1 . 8 m19 9 4 6 Y p e n h w=30 1 = 1 . 8 m20 2 3 1 8 1 3 3 n e n h w=40 1 = 1 . 8 m21 2 4 7 1 3 3 n e n h w = 2 5 . 1 l = l . 8 m22 4 1 9 2 3 3 n e n h v = 4 0 1 = 1 .8 m Z Y 2 5 1 2 2 4 3 npnh 1.=25.1 1-1 .x m24 1 9 8 2 5 3 n e n h v = Z 5 . l 1-1 . H a 2 5 9 1 8 4 Y p e n h w-40 l = l . 8 m26 9 1 9 4 Y p e n h w = 4 0 1-1 . H mZ7 9 7 1 9 9 p e n h w = 1 0 1 = 1 . 8 m2H 9 1 2 1 9 9 p e n h w=10 1 ~ 1 . 8 m29 9 8 1 3 9 p e n h w = 1 0 1 - 1 . 8 .end O P E N I N G P L O T F I L E ONUNIT=

****** ******
xtdec

h s p i c e 88Uia 9:Jti: 6 31-aug89 coppriqht 1 9 8 8 meta-software,inc. *****slte:elite

transient analysis tnom=
2 5 . 0 0 0 temp=

*****

****** ******

25.000

time
(abcdef
)

v ( 0 : 11 0.
t

5.0000
t

10.0000

15.0000

20.0000
t t

9.822 9.822 9.822

9.777 9.894
10.087 10.296 10.517 10.766 11.02ti 11.288 11 , 2 6 0 11.154 11.032 10.912

10.7ti6
10.641

10.528

10.415 1O.:i04 10.193 -+-2----+------+p-----+----------c+----c+------+------t------+10.U84 +'L + e t da cl t t 9 7 2 t e+ t d a ct t 9.971 2 t e t + d a c+ t 9.368 2 t e t + t i a ct t 9.967 2 + e t * d a c+ 9.966 2 te t + d a c+ t t 1C1.247 t 2 e t + d +a c+

t t -e------t------+------2------a-d---c+-------+------+-----e t t 2 a d c+ + t e t t 2 a d c+ + t t e + t 2t at d c+ + + t e t t 2 t a d c+ t t t te + 2 t a dc+ + + t t e t 2 t t t +a 2t t t et 2 t +a cd t + t t t2e t t a ctd + t t t 2 e t t a ctd t + -+------+-----Z+------e------+--a-c+-d----+------+-----t t 2 t e + a ctd t t t t 2 + e t a ctd t + t + Z t e t a cd t + + +Z t e t a cd + + t 2 t + a dct t t et t 2+ t e t t a ti c+ t t + + 2 t t +a d C+ t e t t 2 t t e + tad ct t t t Z t t e t +Z c+ t t
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****** ****** xtdec ******

h s P i c e 8807a 9:46: 6 31-auq89 copvrieht 1 9 8 8 meta-software,inc. *****site:elite

transient analysis voltaqe
0 :2 6 12.0000 12.0000 12.0000 12.0006 12.0004 12.0005 12.0005 12.0005 12.0004 12.0005 12,0004 11.9996 11.9997 11.9997 11.9997 11.9993 11.9994 11.9994 11.9989 11.9888 11.9775 11.9760 11.9770 11.9825 11.9832 11 .9854 11.9871 11.9897 11.9911 11 .9925 11.9936 11.9946 11.9954 11.9961 1 1 ,9968 12.0192 12.0151 12.(~6il 12.0617 1 2 . UOhO 12 . 0 0 0 0 12.004 1 11.9947 12 . OOkil
I
U 4 I I

u n i x
25.000

*+***

******

tnom= loltaue

25.000

temp= vol tape

' i

0:2 10.2040 10.2040 10.2040 10.1182 10.3474 10.6259 10.8967 11.1686 11.4399 1 1 . 7 1 14 1 1 . '9825 11.9132 11.7591 11.5825 11.4009 11.0994 10.7691 10.4180 10.0629 9.7043 9.3488 8.9990 8.6578 8.6384 8.6283 8.6247 8.6215 9.5240 10.4267 11.3267 I Z ' . 22UJ 13.1132 14 . O O O f i 14.8877 15.7735 15.7726 15.7729 15.4296 I5.0Uh.l 14.7390 14.3914 14.0444 1 .i tr913 1.4. 4560

'

I(iI

0:ll 9.8218 Y.HZ18 9.8218 9.7770 9.8939 10.U872 1U.2956 10.5167 10.7655 11.0258 11.2884 11.2599 11.1545 11.0920 10.9125 10.7660 10.6415 10.5281 10,4154 LO. 3037 10.1929 10.0837 9.5771 9.9710 9.9679 9. 9667 9.9657 1U. 2475 1 0 . 5401 10.9.i21 1 1.5893 12. .>22% IJ . 1 9 2 5 I-i.1~.521 I 4. YO9 2 14.9722 I 4. ynnn 14.71Xi 14.JT8~ 14 . . I 1 1 h 14. 1 i t l ( 1 1 4 . u5nJ l.t.9434 I .i . M 7 .$ ii 1 , , 4,47,,

*****

i o b concl

SCALDsystem COMPARE Ver 9 . 2 Processfng xtd.spice P r o c e s s i n g cmpexp.dat G e n e r a t f n g Body T a b l e

xtd. spice BODYTABL E

SUNS-PI

( T u e Mar 15 01:08:49

PST 1 9 8 8 ) .

*********

Name

Number Name ............................................................................

Number

Num Of B o d i e s Num O f S l g n a l s Comparing x t d . s p l c e clk7 clk7b VP f xtnb xtn ghvb g d is t b a9x a 12x a7x vCC wafersubstrate cmpexp.dat

29 26

Num O f B o d i e s Num O f S i g n a l s

clk7 clk7b VPf xtnb xtn ghvb gd t s t b a9x a12x a7x

VCC

wafersubstrata

The C i r c u i t s M a t c h .

B-4 The spice s i m u l a t i o n and LVS result of a VPISW

circuit
Thu Aun 31 21:41:19 PDT 1989
vp1sws

****** ******

copvriqht 1988 meta-software,lnc.

*****slte:el~te

.option nopaqe aspec post dcon=l d v = 1 0 0 0

.width o u t = 8 0 vcc 16 0 5 vsub 6 0 0 vss 19 0 0 .tran lOns llOOns .plot tran v121 ) v( 1 7 ) ~ ( 2 0 v(221 vll81 ) .temp 25 v 2 0 20 19 pu ( 0 5 Ions 2ns 2ns lOns 2511s) v22 22 19 pu ( 5 0 lOns 2ns 2ns lOns 2 5 n s ) v17 17 19 pu ( 5 0 lOOOns 2ns 2ns loons 1 1 0 0 n s ) v21 21 19 dc 12v ml 15 16 10 6 ndep w = 5 1 = 2 5 r 2 11 16 9 6 ndep u = 5 1 = 2 5 m3 21 25 25 6 nenh w = 3 0 0 1 = 3 a 4 22 27 22 6 nenh w = 4 7 1=8.5 a 5 24 16 18 6 ndep w = 3 0 0 1 = 3 a 6 2 0 2 2 0 6 nenh w = 4 7 1=8.5 r 7 16 26 24 6 ndep w = 3 0 0 1=.3..5 m8 2 0 3 2 0 6 nenh w = 4 7 L-8.5 a 9 19 9 19 6 ndep w = 4 0 1=10 m10 21 14 2 6 nenh w = 1 8 1 = 4 mll 19 1 0 1 9 6 ndep w = 4 0 1-10 a 1 2 25 4 4 6 nenh w = 1 0 0 1 - 1 . 8 m13 12 1 b 4 6 nenh w=5O l = J ml4 21 4 18 6 nenh w = l U 0 0 1 = 3 mi5 27 27 3 6 natv w = 4 5 1 = 4 m16 3 3 4 6 natv w = 4 5 1 = 4 el7 2 2 27 6 natv w = 4 5 1-4 m 1 8 11 17 19 6 nenh w = 4 1-4 1 1 9 12 7 19 6 nenh w = 4 0 1=1.8 a 2 0 16 17 1 1 16 penh w = 5 1 = 4 121 13 8 19 6 nenh w = 5 1 = 5 0122 14 7 19 6 nenh w = 8 1=1.8 a23 16 7 12 16 penh w = 4 0 1 = 1 . 8 a 2 4 16 8 13 16 penh w = 5 1 = 5 a25 15 9 19 6 nenh w = 5 1 = 5 a 2 6 16 7 14 16 penh w = 8 1=1.8 m27 8 10 19 6 nenh w = 5 L-5 m28 16 9 15 16 penh w = 5 1 = 5 a29 16 10 8 16 penh w = 5 1 = 5 m30 26 13 19 h nenh w = Z O 1=1.8 a31 26 17 19 b nenh w = 2 0 l=l.H m.42 23 13 26 1 6 penh w=4U l = 1 . 8 m33 16 17 2 3 lh penh w = 4 0 111.H m.34 5 1.4 19 6 n ~ n hw = l O l=1 . X m . i 5 7 1 7 n h npntl w=l I 1 I = 1 X m J h 1 6 1.3 7 1 1 . w n h w=.iO l = l . n m.47 I h I i i I h p r n t ~w = . 4 0 I = I . X

.~ n r l

******

******

transient

analvsis

legend :

time (abcde

v(0:21) 0.
t

5.0000
t

10.0000
t

15.0000
t
t

20.0000
t
t

0. 10.0000n 20.0000n 30.0000n 40.0000n 50.0000n 60.0000n 70.0000n 80.0000n Y O . 0000n 100.0000n 110.00001-1 120.0000n 130.0000n 140.0000n 150.0000n 160.0000n 170.0000n 180.0000n 190.0000n 200.0000n 210.0000n 220.0000n 230.0000n 240.0000n 250.0000n 260.0000n 270.0000n 280.0000n 290.0000n 300.0000n 310.0000n 320.0000n 330.0000n 340.0000n 350.0000n 360. 0000n 3 70.000Un .48U. 0 0 0 0 n J'40.0000n 400.0000n 410.UU00n 420.0000n 4 3 0 . UUOUn 44U.OOUOn 1 5 0 . U00Un 4 6 0 . U000n 4 7 0 . OOUOn J X O . CIOOUn
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12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.0UO 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12,000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.OOU 12.000 12.000 12.000 12.000 12.000 12.000 12.000 12.0U0 12.0iJ0 12.000 12.000 12.000 12.000 12.Uo0 12.UU0
12. OOU

-c------+-e----2------+----------a+-----at------t------t-----c + e 2 t t at

+
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12.000 12.000 1 Z . 000

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*****
vp1 sws

l o b concluded

****** ******

l o b statistics strmmarv

SCALDsystem

C O M P A R E Ver 9.2 S U N S - P 1 ( T u e Mar 15 01:08:49 PST 1988).

Process i n g v p isw.s p fce Process i n g

v p i sw. 1 y o u t

Genersting Body Table

vp l c w .

lyout

...........................................................................
hame

Number Name Number ---------------------------------------------------------------------------.

N u m O f Bodiec N u m Of S lgnals

37 26

N u m Of Bod its N u m O f Signals

Comparing vplsw.splce vp1sw.lyout oebt VP f wafer substrate

vss

nmos+45.50/4.00#natv nmos#lB05.H0/3.00+nenh nmos#300.0B/3.B8#nenh

-matching---> oebt -matching---> vpf -matchfng---> wafersubstrate -matching---> vss -matching---> nmos#45.00/4.88+natv -matching---> nmos#l00H.B0/3.H8#nenh -i3atchlng---> nmos#300.H8/3.0H~nenh

Tho C l r c u l t s Match.

B - 5 The s p i c e s i m u l a t i o n and LVS result of a CLOCK

circuit
l't111 A I I ~ : ( I 2 2 : : j X : 1 8 P[)T 1 9 x 9 c < ~ ~ ~ v l . i 1 9l 8 8t m r t i l - s o t t c i i r . ~ , r l r . . * * * * * + I ! g ~ ~ <- I I<
tar*** **a***
I on a s p r c ~ ~ o s td,c o n : l r l \ = l O ( l 0 22 O 5 v 2 . i 2:1 0 I " v 21, 2 ( i ( 1 O v v.3 I .1 (1 l>Ll1 s e i u 5 l O u c l l l s 2 1 1 s 211s i v 3 u :3u 0 5\, $ \ P I 2.4 $ ~ l h v ti Z $ alhvpqmb 31

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fi c l k 7 t > 2 Y % c l k 5 25 $ c l k 5 h 28 vsub 5 U O v s s 24 U 0

5ns 1 O O O n s u l c v 1 3 t i l = 5 v v l 1 3 ) = U v ( 9 ) = 5 v v l l t i ) = O \ I I $ l = 5 v v l lX.)=Or- v l 1 l ) = 5 v 1 4 1 = 0 + v l X I = 5 v v ( 7 ) = O v l 2 5 ) = 1 v ( 2 ) = 5 \ . v ( 3 ) = 0 v ( 1 2 ) = 5 v ( l O l = 5 v v l 1 9 I=O v ( 2 0 ) = 5 + v l 2 1 l = O v ( 1 5 l = O v1 1 4 l = 5 v l 3 7 ) = 5 v ( . i H ) = 5 .plot 1r.a11 \ I 2 7 1 \ * I 2 9 1 ~ ( 2 5 1 l Z X ) v l . i i I \.I.<HI \.(:{I v t t,nll' 25 n ~ l .I7 1 9 1 0 ;17 p e n 1 1 w = 5 1 = 3 . . 5 i n 2 Z J 3 8 :it; I: r r a t v w = t i 1 = 4 mJ 37 2 2 2 2 5 n a t v w=15 1-3.5 nl l 1 2 2 2 111 5 r l n t \ w = . l O l =:1 1115 1 1 I x 2 I :> r l t ? l l l l w = 5 1 = 5 1111, 2 6 Z 2.4 5 I ~ e l \ l hw r 4 O 1 - 1 . H m i 1'2 . 2 1 5 l l r n l t w = l O l = I . H i lllX ') 4 2.) .-> ~ I ~ I*I= II 0 I = 1 X I m9 li 2 4 . r 1 r t 1 1 1 w = 6 l = l . P i 1 n 1 0 2 2 1 8 1 1 2 2 u e r r l r w - l l r I=:, m i l 25 T 2.4 5 r r e r l l ~ v = . S U I = l . 8 11112 2 2 2 :H 2 2 ))t>r111 h = j I l I = I .P. r n l .{ 7 X 2 I 5 ~ ~ r r w =l1 i5 1 = 1 .8 ~ n 1 l 4 2 2 : I 2 2 2 rent1 u=25 1 z I . H i m 1 5 2 2 4 '4 2 2 ~ w r ~ w )= 1 0 1 = 1 .8 t 111lli H 1 2 1 . 11#.1il1 W - 2 0 ( = I . X i m l i 2 2 li 1 3 2 2 p e t l l ~w = t i l = l . t ( m l 8 I b 9 2 4 5 n ~ r ~ =h 1 = 5 w 3 m l 9 2 2 7 2 5 2 2 pent1 w = 5 0 I = I . H n l 2 O 4 9 2 - 1 5 nptlh id='lU I = I .X m 2 I 1 i l t j 2 4 5 11e11tl w = 5 1 = 5 m 2 2 2 2 X 7 2 2 prnh w = 1 5 1 - 1 .8 m2:{ 1 H 1 7 2.1 5 1rf.11t1 w=!> 115 1n2sI 2 2 '1 H 2 2 1wr111 w = X O I = 1 . H m 2 3 2 2 Y lti 2 2 p e n h w = 1 0 1 = 5 m Z 0 2 2 9 .I 2 2 r ~ e r r h w = Z O 111 . H m 2 i 2 2 Ifi 1 7 2 2 penh w = l U 1 - 5 i n 2 8 2 2 1 7 I H 2 2 r w n h w = l O 11% rnZY 1 9 I I J 2 I .-b ~ l ~ r l v ,= I l l I = . j . . I l
.ic

.t r a n
.

TI,'{IIJ l l '

'1

\~ .

= ~J 6 l

I = ' I . :, ~

m.41 21 2 t l 2 4 5 ~ P I Iw~- 2 5 L = . 4 . 5 , m32 29 14 24 5 nenh w = Y 6 l = d . > m33 27 15 2 4 5 nenh w - 3 6 lz.4.5 1x134 9 13 24 5 nenh w = 5 1 - I . & mJ5 9 11 24 5 nenh w = 5 1 = 5 m36 .I4 13 9 22 pcnh w = 2 0 1 = 5 m J 7 22 11 34 22 penh w=ZO 1 = 5 mJ8 3 26 24 5 nenh w = 1 0 L=1.8 m39 3 8 24 5 nenh w = 1 0 1 = 1 . 8 m40 3 5 26 3 22 penh w = 2 0 1=1.8 a41 2 2 8 35 22 penh v-20 121.8 m42 37 1 0 19 37 penh w = 6 1 ~ 3 . 5 m43 37 19 20 37 penh w = 2 5 1=3.5 8 4 4 37 2 0 21 37 penh w=25 1=3.5 m45 37 14 29 37 penh *=I20 1=3.5 a 4 6 37 15 27 37 penh *=I20 1=3.5 a 4 7 14 15 24 5 nenh w = 2 5 1=3.5 m 4 8 14 21 2 4 5 nenh us25 1=3.5 m49 15 1 4 24 5 nenh w = 2 5 1=3.5 a 5 0 15 2 0 24 5 nenh w = 2 5 1=3.5 a51 36 30 24 5 nenh w = l O 1=1.8 n 5 2 6 31 36 5 nenh r = 1 0 1=1.8 a 5 3 22 3 0 6 22 penh u = 1 0 1=1.8 a 5 4 22 31 6 22 penh w = 1 0 1=1.8 m55 32 15 1 4 37 penh w = 2 5 1=3.5 m56 37 21 32 37 penh w = 2 5 1=3.5 m57 33 14 15 37 penh w = 2 5 1=3.5 m 5 8 37 2 0 33 37 penh w = 2 5 1=3.5 Sm59 38 38 38 5 nenh w = 1 0 1 = 4 mml 3 8 38 100 5 nenh u = 1 0 1=4 mm2 100 100 101 nenh w = 5 1 = 4 am3 101 101 22 nenh w = 5 1 = 4
S

1060 23 m61 23 1062 24 m63 24 m64 24 a 6 5 24 m66 24 .macro a1 1 2 m2 2 2 m3 vpi a4 3 3 m5 7 3

.end8

23 3 8 5 nenh w = 1 0 1 - 7 38 37 5 nenh u=305.6 i=2.5 16 24 5 ndep u = 2 3 . Z 1=18..{2 1 7 24 5 ndev ut23.2 I=lfJ.J2 1 8 24 5 ndep w = 2 3 . 2 1=18.32 9 24 5 ndep w=23.2 1=18.32 11 24 5 ndep -23.2 l=lH.JZ load 1 7 v p i 1 24 natv ~ ~ 2 3 .1=6.925 2 3 24 natv w=5.8 1=3.5 vpi 2 2 4 nenh w=5.9 1=15 24 24 natv w=5.8 1=3.5 7 2 4 natv w-5.8 1-3.5

xl 27 2 9 vpi load m = 8 cl 2 7 24 lpf rl 2 7 100 lk x Z 100 29 vpi load a = 6 4 1-2 1 0 0 101 lk c 2 101 2 4 lpf x3 101 2 9 vpi load m = 8 end copyriqht 1988 mets-softuare.inc. *****site:elite

****** clk ****** ******

n:

trans ient anal v s i s

tnom=

25.000 temp=

25

leqend:
vfo:27)

vl0:27 1

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t

+
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+
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1 0 .0000

+ +
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-+------+------4--c---+------2------+---t------t------+------*

4.122

+
+
+
t

1.411 4.771 5.617

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t t t

549.425~1 + + 2 a + f + + + 170.43581 + + 3 + 3 f + + + 133.514m + + 3 t 3 f + + + lZ8.895m + + 3 + 3 f + + + 128.419=-+------+------3------+----- d z - f - - - - + - - - - - - + - - - - - - + - - - - - - + + + + 2 c f 118.776~1 + t 3 + f + + a2e 2 + 4.641 + + + + f + c a e 2b + 5.741 + + f + + ae c 3 + 7.141 + + f+ t +2 c 7.857 3 + t + f + c + 2 3 + 8.195 + + f + c + ae 3 + 8.359 + + f + + 2 c 3 + 8.437 + + f + + 2 c 8.481 3 + + t 7.737 - + - - - - - - + - - - - - - 3 - - - - - - + - - - - - - d - - - - - - w - - - f + - - - - - - + - - - - - - t a+2 f + d 7.277 + 2 + + + + + d2 f 364.970m + + 2A + + + + 3 f 157.949~1 3 + + + + + + 3 f 129.476s + 3 + + + + + 3 f 3 + 126.594~1 + + + + + 3 f 126.766. + 3 + + + + 3 f + 127.035m + 3 + + + + 102.231m + + 3 + 2 c f 3.980 + + 2 t a 3 f + + + 5 , 4 4 5 -+------+------2b-----+------ cae----+f-----+------+------+ c se+ f + + 3 + 6.958 + + c +2 f+ + 3 + 7.762 + + c + 2 f + 8.152 + + 3 + c + 2 f + 8.336 + 3 + + 8.428 c + 2 f + + + 3 + c + 2 f + 8.476 + + 3 + d +2 f+ + 8.018 + + 3 + +3 f + 7.903 t d + + 2 f+ + + 5 9 4 . 3 9 3 ~+ + Z a + d 2 172,063~-+------+------3--------+------3-f----+------+------+------+, + + + 3 f 137.208m + + 3 + + + + 3 f 128.443. + 3 + + + + + 3 f 127.64Ym + + 3 + + + + 3 f 3. + 1 2 7 . 9 0 0 ~+ + + + + Z c f 1 1 1 . 3 3 0 ~+ + 3 + 3.075 + + 2 + a ebc f + + + 5.272 + + 2 b + cae +f + + c ae+ f + + 6.778 + + 3 + 7.670 + + 3 + c ae f+ + 8.112 -+------+------3------+------c--------+-2----f------+------+ f + + 2 3 + c 8.316 + + 1 + + 2 3 + c 8.416 + + f + c + 2 3 + 8.471 + + f + + 2 3 + d 8.198 + t f+ + d bea 7.720 + 2 + + + + +f 2 a + d 2 I .309 + + 106.557m + + 2a + 3 f + + + , l d l Y'/c;m + A 1

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128.102m t t 3 t 3 f + t + t t 1 2 0 . 3 4 7 ~t t 3 t ebcf t t t + 1.754 t 2 c f t t t t 2 a t +f 5.309 t t t t t 2 t b cae n e t f + t t 6.502 t c t 3 t 7.521 t c 2 f t t t t J + + + t 2 ft 8.046 t 3 t c t t 2 8.287 t .i + c t t' + . t t ' t + ' L f 8.404 t c t 3 t 8.462 - + - - - - - - + - - - - - - J - - - - - - + - - - - - - c - - - - - - + - - 2 - - - f - - - - - - t - - - - - - t 8.273 + t 3 t d t 2 f t + 7.377 + t 2 t db ea f + t t 2.811 t t 2 +a d bet f t t t + t t 3 f t t 207.382~ t t 'La t t t 3 f t t 142.311m t 3 t t t t 3 f t t 129.969. l 3 t t t t t t 3 f 1 2 8 . 7 8 5 ~t 3 t + t t t t 3 f 1 2 8 . 8 6 2 ~t J t + t t t t 2c f 119.217. t t 3 791.538D-+------t------22R----t---222CCf----+------+------+------+5.279 t t 2 t bcae tf + t t c a e t f + t t 6.327 + t 3 t 7.448 t t 3 + c 2 f t + t 8.004 + t 3 + c tae f+ t t 8.265 t t 3 + c t 2 f t t 8.394 t t 3 t c t 2 f t t 8.455 t t 3 + c t 2 f t t 8.415 + t 3 t d t ea f t t 7.401 t t 2b t d ea f + + t 4.834 - + - - - - - - t - - - - - - 2 - - - - - - + - - - - - - - - - b s + - - - - b e t - - - - f - t - - - - - - t - - - - - - t 247.059. t t 2a t 3 f t t t + 151.018~ t t 3 t J f + t t t 13U.072m t t 3 t 3 f + t t t 1 2 8 . 8 5 3 ~t t 3 t 3 f + t t t 129.517r t t 3 t 3 f l t t t 128.333r t + 3 t 3 f t t t t 241.120m + t 2a t 2 c f + t t t 5.057 t t 2 t 3 e f + t t 6.065 t t 3 t c a e t f + t t 7.330 - + - - - - - - + - - - - - - 3 - - - - - - + - - - - - - - - c - - - - - - ~ - - - - f - + - - - - - - + - - - - - - + t2 ft t t 7.943 t 3 t C t t 2 f t t 3 + c 8.236 t t f t t t c t ae 8.379 t t 3 t 2 f + t 3 t c 8.447 t t t 2 f t t 8.486 + 2d t c t ft t t 2 t d 7.590 t t 3 a 2 ft t t 2 t d 6.346 t t 298.321. t + 2a + d2 F t t t t 155.706m t + 3 t 3 f t t + t )30.790m-+------+------3------+------3-f----+------+------+------+l t t t 3 f 3 t 1 2 9 . 3 5 1 ~l t t t t t 3 f 3 t 129.786. t t + t t + d2 f 3 t 129.948m t t l t t t 2 c f 3 t llY.6RBm t t t t f t 2 t a2e 4.ri13 t t t t t f + 2b t c a e 5.708 + + f t t + t c ar 3 7.141 + t Yt t t t2 3 + r 7.854 .t t t 4 + t 2 3 t r U.lk4 t t 8.35f, - + - - - - - - t - - - - - - ~ - - - - - - + - - - - - - , . - - - - - - + - a e - - f - - - - - - + - - - - - - + -

SCALDsystem C O M P A R E Ver 9.2 SUN3-P1 ( T u e Mar 15 01:88:49 Processing clk-s.1yout Processing clk-s.spice Generatfng Body Table clk-s.lyout BODYTABL E Name

PST 1988).

Number Name ............................................................................

Number

Num O f Bodies Num O f Signals Comparing clk-s.lyout clk7 clk7b VP

V CC

54 31
clk-s.spice

Num O f Bod i e s Num O f Signals

clk7 c 1 k7b VP f
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pgmb wafer substrate VSS lgdfstb pmos#Z5.00/3.SB#p4 pmos#25.00/3.50#p4 pmost25.00/3.58#p4 pmos#25.00/3.50#p4 pmos#120.00/3.50+p4 pmos#120.00/3.50#p4 pmos#6.00/3.50#p4 pmos#5.00/3.50+p4 pmos#25.00/1.80#penh pmos#20.00/1.80#penh pmos#20.00/5.00#penh pmos#20.00/5.00#penh

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