E&CE 223 VHDL Project Description

Winter 2004

1. Objectives
Designing a 16-bit carry-skip adder. Modeling and simulation of combinational logic using VHDL. Using VHDL CAD tools (Webpack). Using structural design techniques.

2. Introduction
We will start by explaining the operation of one-bit full adder which will be the basis for constructing the carry-skip adder.

2.1. One-bit full adder

A one-bit full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs ai , bi , and ci , and two outputs si and ci+1 as illustrated in Figure 1.
Bi
Ai

Full Adder

Ci

Ci+1

Si

Figure 1. One-bit Full Adder.

The gate implementation of 1-bit full adder is shown in Figure 2.

Figure 2. One-bit Full Adder (Gate level).

Expressions for the one-bit full adder outputs are as follows: Pi = Ai Bi Gi = Ai Bi s i = Pi Gi ci +1 = Gi + Pi ci

2.2. 4-bit carry-propagate (ripple) adder

A carry propagate adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed using one-bit full adders (see section 2.1) connected in serial, with the carry output from each full adder connected to the carry input of the next full adder in the chain. Figure 3 shows the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder. It can be noted from Figure 3 that the input starts from the right side since the first cell traditionally represents the least significant bit (LSB). Bits a0 and b0 are the LSB bits of the numbers to be added. The Summation output is represented by (s0... s3).

Figure 3. 4-bit Carry-propagate Adder.

3. Carry-skip addition
Carry-skip addition is used to accelerate carry propagation in long chain adders. Based on the values of the propagate bits of one group of bit (Pi Pi+1 Pj), the final carry can be predicted. Figure 3 shows the schematic diagram for a 16-bit carry-skip adder. Each 4-bit block is a 4-bit carry propagate adder (refer to Section 2.2).

Figure 3. Carry-skip adder.

The carry-skip condition is such that:

If (Pi Pi+1 Pj) = 1 then Group_Carry_out = Group_Carry_in Else Group_Carry_out = Cj End if

Where Cj is the carry generated internally within the group. That can be expressed as:

Group_Carry_outj = Ci+k + (Pi Pi+1 Pj+k-1).Group_Carry_inj Where k is the group size (number of bits for which the carry is skipped), i, and j are the start and end bits of the group. For example, the carry predicted for the first group of 4bits in the carry skip adder is expressed as: c4 = c3 + ( P0 P P2 P3 ) c0 1

4. Hint
Use the GENERATE statement to generate the necessary blocks and to establish the required connections. The syntax is as follows:
generate_label : generation_scheme GENERATE [ { block_declarative_item } BEGIN ] { concurrent_statement } END GENERATE [ generate_label ] ;

Then, to generate multiple instances of a block, a for generate can be used.

Label: for i in discrete_range generate {concurrent statement} end generate [label];

4. Project Requirements
In this project you are required to design, model, and simulate a carry skip adder. The target technology is FPGAs. We are going to use the Xilinx FPGA chip used in the Lab as the target device (Spartan 2E, part: xc2s300e, package: PQ208, speed: -6). Below are the project required steps: 1. Write VHDL behavioral models for OR, AND, and XOR gates. 2. Model a structural description of a 1-bit full adder using the OR, AND, and XOR gates as components. Pi, si, and ci+1 should used as outputs. 3. Model a 4-bit carry-propagate adder in a separate file using VHDL structural description. The 4-bit adder will use 1-bit full adders as components. 4. Model a 4-bit carry skip cell. 5. Model a 16-bit adder in a separate file using the VHDL structural description. The 16-bit adder will use the 4-bit carry-propagate adders and the 4-bit carry-skip adders as components. 6. The 16-bit adder has two inputs of type std_logic_vector representing the two numbers to be added. A 1-bit input carry of type std_logic representing the carry in is also required. The adder produces one output signal of type
_

std_logic_vector representing the sum word and a 1-bit output signal

representing the Carry-out from the 16-bit adder. 7. Write a testbench to verify the operation of the 16-bit adder. The testbench should try different number values. Simulate the behavior of the adder using the testbench you developed.

5. Project Report
Your lab report should include the following. 1. ALL VHDL files used in the project implementation including your own testbench file. Missing files will result in a corresponding penalty. 2. Number of FPGA slices used by your design. 3. Maximum CLOCK frequency after compilation from the place and route report. 4. Project analysis + simulation waveforms for some (not all) test vectors.

6. Marking Scheme
The marking scheme is: Implementation (ALL VHDL files can be compiled and simulated) Area (number of slices) Speed (maximum clock frequency) (60%) (10%) (10%)

Report (2 pages: problem description +analysis +area and speed numbers) (20%)

7. Submission Procedure
Deadline is April 2nd, 2004, at midnight. Use the WebObjects web site for electronic submission: (https://ecewo.uwaterloo.ca). Create an account for your GROUP in the course book of ECE223. Compress all files (including the report in PDF format) in a single .zip file. Upload the file to you account.