Introduction to Circuit Layout

with Virtuoso and Calibre

Integrated Circuit Application and Design Lab. Chung Yuan Christian University Prepared by C. Y. Chiou

Schedule
Environment Setup
Lab.1 Ruler

Contact Layers
Lab.2 VIA12_Cell Layout

MOS Layout
Lab 3 NMOS Layout

Environment Setup
Step 1
mkdir Layout cd Layout cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/cds.lib . cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/display.drf . cp /process/TSMC/018um/PDK-13D/T018MMSP001K1/PDK13D/techfile . layout &

Step 2.1
File >> New >> Library

Environment Setup
Step 2.2 Step 2.3

Step 2.4

Environment Setup
Step 3.1

Step 3.2

Environment Setup
Step 3.3 1. 2.

3.

Environment Setup
Step 4.1

Library Name: Cell Name: Tool:

Exercise Rule Virtuoso

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Environment Setup
Step 4.2

(1) Minor Spacing: Major Spacing:

0.01 5

X Snap Spacing: 0.005 Y Snap Spacing: 0.005 Library (2) Click Save To Click OK
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Lab.1
Lab 1 Ruler

k: Shift + k: Shift + z: Ctrl + z:

Ruler Clear Rulers Zoom out Zoom in

Case 1: (Zoom in) Distance = ? Case 2: (Zoom out) Distance = ?

Answer : 0.01

Answer : 5
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Contact Layers

VDD

Outline 1. Gate, Source, Drain 2. Substrate 3. Contact Layers 4. MCO Layout 5. Calibre DRC of MCO 6. MCP Layout and DRC

VIN2

VOUT

VIN1

GND

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Contact Layers
Gate, Source, Drain

Input/output signal is always feed in/out from Metal Line.

VDD VIN2

VOUT

VIN1

GND

Gate: Drain: Source:

POLY Contacted to Oxide Contacted to Oxide Contacted to

Metal 1 Metal 1 Metal 1

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Contact Layers
Substrate (1)

One chip can only have only one P-Substrate, but it can have multiple N-Well. Minimize chip area: Use only 1 N-Well.

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Contact Layers
Substrate (2)

Substrate of NMOS: (1) In P-Substrate (2) Diffusion + P-IMP Substrate of PMOS: (1) In N-Well (2) Diffusion + N-Well
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Contact Layers
Substrate (3)

Reduce Rs to avoid latch-up. That is, eliminate the distance from MOS to the nearest substrate contact.
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Contact Layers
Contact Layers
VDD VIN2

VOUT

VIN1

GND

MCO MCP VIA12_Cell

Metal1 + Contact + Oxide (Diffusion) Metal1 + Contact + Poly Metal2 + VIA12 + Metal1
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Contact Layers
MCO Layout
Step 1

Library Name: Exercise Cell Name: Tool: MCO Virtuoso

Step 2

Create >> Rectangle (or click r )

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Contact Layers
MCO Layout
Step 3

Click CONT in LSW.

Step 4

Draw a rectangle. ( Dont care the size! )

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Contact Layers
MCO Layout Step 5 1. Click the rectangle. 2. Press q. 3. Key in the parameters. 4. OK Design Rule CO.W.1 = 0.22u Step 6 Check the length with ruler.

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Contact Layers
MCO Layout Step 7 1. Click the rectangle. 2. Create 3. Layer Generation

Step 8.1 1. CONT 2. GROW BY 3. 0.1 4. DIFF 5. OK Design Rule CO.E.1 = 0.1u Hot Key: f (Fit)
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Contact Layers
MCO Layout Step 8.2 Check the distance with ruler.

Step 9.1 1. Click the rectangle. 2. Create 3. Layer Generation 4. CONT (Grow by) 0.005 = Metal1 Design Rule M1.E.1 = 0.005u M1.E.2 = 0.06u

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Contact Layers
MCO Layout

(Step 9.2) 1. Click the rectangle made of Metal1. 2. Press q. 3. Top = 0.225 + (0.06-0.005) = 0.28 4. Bottom = -0.005 - (0.06-0.005) = -0.06 5. OK

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Contact Layers
MCO Layout

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Contact Layers
Calibre DRC of MCO Step 1 Calibre >> Run DRC

Step 2

Step 3

Calibre-DRC Rules File: /process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc Calibre-DRC Run Directory: .

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Contact Layers
Calibre DRC of MCO

Step 4

Flat

Step 5

Run DRC

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Contact Layers
Calibre DRC of MCO (Step 6)

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Contact Layers
MCP Layout and DRC Step 1

Step 2 Press and hold the right key of the mouse.

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Contact Layers
MCP Layout and DRC Step 3 Step 4 Remove of DIFF in MCP

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Contact Layers
MCP Layout and DRC Step 5

1. Click the rectangle made of CONT. 2. Create 3. Layer Generation Design Rule CO.E.2 = 0.1u 4. CONT (Grow by) 0.1 POLY1 5. Calibre >> Run DRC

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Contact Layers
MCP Layout and DRC

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Lab.2
Lab.2 VIA12_Cell Layout and Verification Related Design Rules

Mx.E.1 = 0.01um Mx.E.2 = 0.06um VIAx.E.1 = 0.01um VIAx.E.2 = 0.06um

VIA.W.1 = 0.26um
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Lab.2
Lab.2 VIA12_Cell Layout and Verification

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MOS Layout

Layers: DIFF, CONT, POLY1, Metal 1, VIA12, Metal 2 DIFF CONT POLY1 1 VIA12 Rules: Space (Clearance), Overlap, Extension
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MOS Layout
/process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc

NM OD PO PP NP CO M1 VIA1 M2 VIA2 M3 VIA3 M4

N-Well Thin Oxide Poly-Silicon P+ Implantation N+ Implantation Contact Window from M1 to OD 1st Metal Via1 hole between M2 and M1 2nd Metal Via2 hole between M3 and M2 3rd Metal Via3 hole between M4 and M3 4th Metal
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MOS Layout
/process/TSMC/018um/PDK-13D/T018MMDR001C1/calibre_modified.drc

W: Minimum Width S: Space ( Distance between the same layer) C: Clearance (Distance between different layer) O: Overlap E: Extension

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MOS Layout
1. Width: Diff 2. Length: Poly 3. D: Clearance 4. X : Contact Number of Contact = ? >> Spacing Rule 5. Implant

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MOS Layout
Space: Example of MCO
Space of Two MCOs Related Rule: CO.S.1 = 0.25 Original Space = 0.2 0.25-0.2 = 0.05 Increase the distance by 0.05.
Height of 1st MCO = 0.42 Height of 2nd MCO = 0.42+0.05=0.47

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MOS Layout
Space: Example of VIA12_Cell

Space of Two VIA12_Cells Related Rule: VIA1.S.1 = 0.26 Original Space = 0.12 0.26-0.12 = 0.14 Increase the distance by 0.14.
Height of 1st VIA12_Cell = 0.38 Height of 2nd VIA12_Cell = 0.38+0.14=0.52
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MOS Layout
Distance between MCO and POLY = 0.06

CO.C.1 = 0.16

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MOS Layout
P-Implant

PP.E.1 = 0.18

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MOS Layout
Overlap

PO.O.1 = 0.22

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MOS Layout

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MOS Layout
Clearance

OD.C.4= 0.43

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MOS Layout
Common-Used Bind-Key
f Ctrl + z Ctrl + f m, F3 c, F3 i d k s Shift + k Esc Shift + f View total layout diagram Shift + z Zoom In/Out Hierarchy/Flat View Move and call its detailed options Copy and call its detailed options Instance invoking Delete Ruler (marker) Stretch Remove all marker in the diagram Cancel the invoked command
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MOS Layout
PMOS Layout Flow
Step 1 File >> New >> Cellview Library Name: Exercise Cell Name: PMOS_Mp1 Tool: Virtuoso W=3.32u, L=0.18u Step 2 (1) r (2) DIFF (3) Draw a Rectangle (4) Select the Rectangle (5) q Step 4 (1) r (2) POLY1 (3) Draw a Rectangle (4) Select the Rectangle (POLY1) (5) q

Step 3 Left: 0 Right: 0+0.42*2+0.06*2+0.18= 1.14 Bottom: 0 Top: 3.32 Step 5 Left: 0+0.42+0.06= 0.48 Right: 0.48+0.18= 0.66 Bottom: 0-0.22= (-0.22) Top: 3.32+0.22= 3.54

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MOS Layout
PMOS Layout Flow
Step 1~5 Step 6 3.32-0.42=2.9 2.9/0.47=6.1702 Number of MCO = 6+1 = 7 Height of MCO = 0.42 + 0.47*6 = 3.24 3.32-3.24 = 0.08(even) 0.08/2 = 0.04

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MOS Layout
PMOS Layout Flow
Step 7 (1) i >> MCO (2) Rows = 7, Delta Y = 0.47 Column = 2, Delta X = 0.42+0.18+0.06*2 = 0.72 (3) Put MCO into the PMOS (4) Shift + f

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PMOS Layout Flow

Step 8 (1) Select the Rectangle of DIFF (2) Create >> Layer Generation (3) DIFF (Grow by) 0.18 = PIMP (4) Apply (5) DIFF (Grow by) 0.43 = NWELL (6) OK (7) Stretch PIMP to fit PP.C.5 (8) Calibre >> Run DRC

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Lab.3
NMOS Layout
Design Rule NP.E.1 = 0.18um NP.C.5 = 0.35um

Library Name: Exercise Cell Name: NMOS_Mn1 Tool: Virtuoso W=1u, L=0.18u

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