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Points Addressed in this Lecture

General model of finite state machines FSM design procedure

Lecture 12: Finite State Machines


Professor Peter Cheung
Department of EEE, Imperial College London

E1.2 Digital Electronics I

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E1.2 Digital Electronics I

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Design of Synchronous Binary Counter


From the last lecture we have seen:
synchronous counters use a register to hold the outputs the inputs of synchronous counters are derived as logical combinations of outputs We will now design the counter as a FSM

Step 2: Construct Karnaugh maps for each input from the state transition table and the flip-flop transition table
State Transition Table

Procedure Step 1: Start with the transition table of the flip-flop to be used
E.g. D-type
Output Transition Required 0 to 0 0 to 1 1 to 0 1 to 1 Input D 0 1 0 1

Current State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Next State Q2+ Q1+ Q0+ 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0

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E1.2 Digital Electronics I

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D2
Q2\Q1Q0 0 1 00 0 1 01 0 1 11 1 0 10 0 1

Step 3: Extract Boolean expressions from the Karnaugh maps

Q2\Q1Q0 0 1

00 0 1

01 0 1

11 1 0

10 0 1

D2 = Q2. Q1 + Q2. Q1. Q0 + Q2. Q1. Q0

D1

Q2\Q1Q0 0 1

00 0 0

01 1 1

11 0 0

10 1 1

Q2\Q1Q0 0 1

00 0 0

01 1 1

11 0 0

10 1 1

D1 = Q1. Q0 + Q1. Q0 = Q1 Q0

D0

Q2\Q1Q0 0 1

00 1 1

01 0 0

11 0 0

10 1 1

Q2\Q1Q0 0 1
Nov 2007

00 1 1

01 0 0

11 0 0

10 1 1
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D0 = Q0
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E1.2 Digital Electronics I

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E1.2 Digital Electronics I

Design of Arbitrary Code Counters


Step 4: Implement using combinational logic
Q0 Q1

1 =1 CLOCK 1 1 D0 & & & & D1 D2

It may be necessary to design counters which count sequences other than a binary count Examples:
C1 1D Q0 Q1 Q2

Counters which never reach their maximum value


e.g. a zero-to-nine counter (needs 4 bits)

Q2 Q1 Q2 Q1 Q0 Q2 Q1 Q0

Counters which follow a specific code sequence


e.g. 7 segment display sequence counter

The design procedure presented for binary counters can be extended to arbitrary code counters

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Example
A 3-bit counter to count the decimal sequence 0, 2, 5, 6. Counting sequence: Decimal Q2 Q1
0 2 5 6 0 0 1 1 0 1 0 1

State Transition Table

Current State Q2 0 0 Q1 0 1 0 1 Q0 0 0 1 0 0 1 1 0

Next State Q2+ Q1+ Q0+ 1 0 1 0 0 1 0 0

Q0 0 0 1 0

1 1

Undefined States
In this example, some of the possible 8 states are undefined What happens if the circuit gets into one of the undefined states?
e.g. at power-on

State Diagram:
000 010 101 110

We will consider two approaches here:


1. 2. Ignore this possibility treat the undefined states using "don't care" Take account of this possibility map the undefined states explicitly to the "zero" state

In both cases we follow the design procedure already presented

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Undefined states as "don't care" Circuit Diagram


D2

Q2\Q1Q0 0 1
Q2\Q1Q0 0 1
Q2\Q1Q0 0 1

00 0 X
00 1 X
00 0 X

01 X 1
01 X 1
01 X 0

11 X X
11 X X
11 X X

10 1 0
10 0 0
10 1 0

CLOCK Q0 Q1 Q2 D0 D1 D2

C1 1D Q0 Q1 Q2

D1

D0

C u rre n t S ta te Q2 0 0 1 1
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N e x t S ta te Q 2+ 0 1 1 0 Q 1+ 1 0 1 0 Q 0+ 0 1 0 0
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Q1 0 1 0 1

Q0 0 0 1 0

D2 = Q0 + Q2. Q1. Q0 D1 = Q1 D0 = Q2. Q1


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E1.2 Digital Electronics I

Undefined states map to "zero"


Modified State Transition Table
Current State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
111 011 100

Modified State Diagram

Q2+ 0 0 1 0 0 1 0 0

Next State Q1+ Q0+ 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

D2

Q2\Q1Q0 0 1 Q2\Q1Q0 0 1

00 0 0 00 1 0

01 0 1 01 0 1

11 0 0 11 0 0

10 1 0 10 0 0

D2 = Q2. Q1. Q0 + Q2. Q1. Q0 D1 = Q2. Q1. Q0 + Q2. Q1. Q0

D1

D0

Q2\Q1Q0 0 1

00 0 0

01 0 0

11 0 0

10 1 0

D0 = Q2. Q1. Q0

001

000

010

101

110

The term Q 2. Q1. Q 0 can be re-used to simplify the circuitry This implementation is a bit more complicated but will always work (unlike the "don't care" implementation)

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Implementing FSM with ROM


000 010 101 110

Implementing FSM with ROM


Address A2:0 A2 A1 A0 D2 Data D2:0 D1 D0

0 0 1
CLOCK Q0 Q1 Q2 D0 C1 1D Q0 Q1 Q2

0 1 0 1

0 0 1 0

0 1 1 0

1 0 1 0

0 1 0 0
CLOCK C1 D0 1D

All other locations contain 000

ROM

D1 D2

Q0 Q1 Q2

Q0 Q1 Q2

ROM

D1 D2

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