Properties of RISC Processors: A RISC microprocessor such as the PowerPC emphasizes simplicity and efficiency.

RISC designs start with a necessary and sufficient instruction set. The purpose of using RISC architecture is to maximize speed by reducing clock cycles per instruction. Almost all computations can be obtained from a few simple operations. The goal of RISC architecture is to maximize the effective speed of a design by performing infrequent operations in software and frequent operations in hardware thus obtaining an improved performance. The following list summarizes the typical features of a RISC microprocessor. 1. Simple Instructions: All instructions are simple instructions so that each can execute in single cycle. This property simplifies processor design. Note that a cycle is defined as the time required to fetch two operands from registers, perform an operation, and store the result in a register. 2. Hardwired control unit: The RISC microprocessor is designed using hardwired control unit with little or no micro programmed CU. Note that variable-length instruction formats generally require micro programmed design. All RISC instructions have fixed formats, so no need of micro programmed design is necessary. This improves the overall execution efficiency can be as good as a micro programmed CISC machine. 3. Register-to-Register Operations: A typical CISC instruction set supports register-to-register operations as well as register to memory and memory to memory operations. RISC processors allow only special load and store operations to access memory. The rest of the operations are on register-to-register basis. This feature simplifies instruction set design and allows execution of instructions at one instruction per cycle. This operand restriction simplifies the control unit. 4. Simple Addressing Modes: Simple addressing modes allow fast address computation of operands. Because RISC processors employ register-to-register instructions, most instructions use register-based addressing. Only the load and store instructions need a memory-addressing mode. RISC designs provide very few addressing modes that is less than or equal to 4. 5. Large Register Set: RISC processors use register-to-register operations in order to implement most of the operations based on register to register. This will permit the intermediate results to be stored in the registers and hence reduce the number of load /store memory accesses and speed up the runtime. Another advantage with a large register set is the procedure calls and returns are minimized. The number of register set in a RISC is a minimum of 32 and a maximum of 100. 6. Fixed-Length, Simple Instruction Format: RISC designs use fixed-length instructions. Variable-length instructions can cause implementation and execution inefficiencies. For example, we may not know if there is another word that needs to be fetched until we decode the first word. Along with fixed-length instruction size, RISC designs also use a simple instruction format. The boundaries of various fields in an instruction such as opcode and source operands are fixed. This allows for efficient decoding and scheduling of instructions. 7. Less number of instructions: RISC processors have less then 128 number of instructions which is very small compared with CISC processors. 8. Parallel Processing: A RISC microprocessor processes several instructions simultaneously and thus includes pipelining. Super scalars, super pipelining methods are adapted that offers more than one instruction are executed in a single cycle.

9. General support to HLL: Most of the CISC processors support HLL characteristics such as handling local variables, constants and procedure calls by time consuming and hence reduce the complexity. 10. Delayed Branch: In most RISC processors, a new technique called Delayed Branch is followed. If a branch instruction comes, the Branch Predictor unit predicts the condition and depends on the condition, it prefetches the instruction. If the prediction becomes wrong, a large time delay occurred due to flushing the pipeline and loading new set of instructions in the pipeline. To reduce this time delay, processor reorders the instructions and executes them. For example,

11. Score boarding: When continuous instructions that have the same destination (write after write) are executed in pipeline incorrect result occurs. This is the same in case of read after write. To avoid this, a special register called score board register whose size is equal to the number of registers available in that processor. For example, if 32 register available in a system, then the score board register is 32 bit wide each bit is assigned with one register. If a register is a destination register then the corresponding bit in the score board register is set. Hence the subsequent instructions in the pipeline will be prevented from the fault operations. 12. Dual cache: Most of the RISC processors have dual cache Instruction cache and dual cache that hold code and data separately. Hence the memory access can be done with a less time.