REVISED PHYSICAL ALPHA-POWER LAW MODEL
FOR ULTRATHIN OXIDE MOSFETS
Nazmul Arefin, Fauzia Ahmed, Md. Rashedur Rahman and Quazi Deen Mohd Khosru
Department of Electrical & Electronic Engineering
Bangladesh University of Engineering & Technology
Dhaka-1000, Bangladesh
E-mail: nazmularefin@gmail.com
ABSTRACT
A thorough study of the physical alpha-power law
MOSFET model reveals that the model has been
developed for relatively thick oxide MOSFETs
ignoring the effect of interface states. Although the
effect of interface states is negligible for thicker
oxide MOSFETs, it starts affecting the drive current
as the device size is scaled down to ultrathin regime.
In this work, we propose a revised physical alpha-
power law model for ultrathin oxide MOSFETs
incorporating the effect of interface states. A
comparative study between the existing and the
proposed model revealed a remarkable significance
of interface states on the characteristics of ultrathin
oxide MOSFETs.
1. INTRODUCTION
The physical alpha-power law MOSFET model [1]
was constituted of previously proposed alpha-power
law MOSFET model [2] and the low power
transregional MOSFET model [3]. The alpha-power
law MOSFET model [2] was the most widely used
compact drain current model due to simple
mathematical form and high degree of accuracy. But
the model did not describe the subthreshold region
and therefore on/off drain current tradeoffs could not
be analysed. In this respect, the low power
transregional MOSFET model has described all the
three regions of operation. The drain current
equations have been provided insight into the
physical basis of MOSFET behaviour. But this model
showed a disadvantage due to complex drain current
equations. Coupling the alpha-power law MOSFET
model and the low power transregional MOSFET
model the physics based alpha-power law MOSFET
model [1] was proposed that included the
advancement in study in subthreshold region of
operation and even it included the effects of high
field mobility degradation. But this model [1] was
not facilitated with the existence of the interface
trapped charges that might change the value of the
MOS capacitance significantly altering the drain
current values in the different operating regions. In
this respect we have suggested the advancement of
physical alpha-power law MOSFET model by
including the above mentioned capacitances and thus
have obtained a good deviation from the previous
model and it presents a very accurate physics based
alpha-power law MOSFET model.
2. EXISTING MODEL
The derivation of the physical alpha-power law
MOSFET model [1] begins by equating the
saturation drain current of the alpha-power law
MOSFET model [2], equation (1) and the low power
transregional model [3], equation (2)
α
 V − VT 
I D 0  GS  = I DSAT (1)
 VDD − VT 
[
I DSAT ≈ (W L )C ox µ eff V DSSAT VGS − VT − (η 2 )V DS SAT ]
(2)
where ID0 is a modified drive current that includes an
effective mobility dependence on VGS, (W/L) is the
channel width-to-length ratio, Cox is the gate oxide
capacitance per unit area and µeff is the effective
mobility including vertical [4] and lateral [5] high
field degradation effects given as
µ0
µ eff = (3)
[1 + θ (VGS − VT )][1 + VDS (EC L )]
SAT
The equations for different operating regions include
Cox as the total capacitance for the calculation
purpose. Further these equations have included Cox
as a constant component for the whole of the
operating region. The equations are as follows:
η
I DSUB = (W L )µ 0 C ox [1 − exp(− βVDS )]
β2
 exp[(β η )(VGS − VT − η β )] (4) defects at the interface, which gives rise to charge
“traps”; these can exchange mobile carriers with the
I DTRI = (W L )µ eff C oxVDS [VGS − VT − (η 2 )VDS ] (5) semiconductor, acting as donors or acceptors [7].
The interface trapped charges are very negligible in
α
 V − VT  effect in case of strong inversion but if we consider
I DSAT = I D 0  GS  (6) the case of very thin gate oxides then we find the
 VDD − VT  trapped charges playing a vital role in case of
determining MOS capacitance. The band diagram
3. PROPOSED MODEL for a MOS structure at positive voltage is as follows:
Our study about the physical alpha-power law
MOSFET model includes a modification about the
MOS capacitance. In the subthreshold region, the
effects of depletion capacitance and capacitance due
to interface trapped charges are not included. As a
consequence revised model is presented with the
employment of interface trapped charge capacitance
(Cit) and depletion capacitance (Cd). The revised
model includes the arrangement of capacitances in
the following manner [6]:
Fig 2: Band diagram of a MOS structure
From the above figure, we see the existence of
interface trapped charges in the oxide region of
MOSFET. Usually in case of significantly thick gate
oxides these charges are not of any significance in
calculating the MOS capacitance. But as we see,
Fig 1: Arrangement of capacitances when the oxide thickness is very thin then these
charges existing near to the edge of the oxide surface
Now it comes to a point of determining the different
strongly take part during the application of electric
components of the total capacitance (CMOS). Oxide
field [8]. So we see that negligence about the
capacitance is varied from the flatband capacitance
existence of these charges is not quite always right to
(CFB) to the intrinsic value of the oxide capacitance
determine a better current response from a MOSFET
(εi/tox). The flatband capacitance is a series operation. An energy distribution of the interface
combination of Debye capacitance (Cdebye) and trapped electron density, obtained at 293K at 1 KHz
insulator capacitance (Ci) [6]. It is assumed for frequency, is shown below:
convenience that the oxide capacitance (Cox) varies
linearly. In our proposal we determine the gate to 11
substrate voltage (VGS) from surface potential (φs) by 10
the following equation [7]:
Distribution (cm eV )
-1
Interface Charge

VGS = VFB + φ s + γ φ s + φt exp((φ s − 2φ F ) φt )

-2

o
T = 20 C

(7)
Depletion capacitance (Cd) is determined by
calculating depletion width (Wm) that is directly
10
proportional to the square root of the surface 10
0.10 0.15 0.20 0.25 0.30 0.35
potential (φs) [6]. It follows that:
Energy (eV)
1
 2ε φ  2ε
Wm =  s s  ;C d = s (8) Fig 3: Energy band distribution of interface trapped
 qN a  Wm electron density (Intrinsic level is the zero reference
The interface trapped charge distribution was level)
calculated from the study through charge pumping
method [8]. To mention that an interface trapped From the previous distribution, we obtained value of
charge (also called fast interface state) exists at the
the interface trapped charge capacitance (Cit) equal
oxide-semiconductor interface. It is caused by
to 65.771 nF. For our purpose of operation we that calculated by the physical alpha-power law
assumed it to be a quite constant value and used model.
it in all the necessary regions of operation.
-2
10
4. RESULTS AND DISCUSSION 3.5 nm alpha model
-5
10 3.5 nm proposed model
We have engaged two specimens for our study: a) 3.5

Drain Current (A)

2.2 nm alpha model
nm oxide n-MOSFET and b) 2.2 nm oxide n- 10
-8 2.2 nm proposed model

MOSFET. Although they show difference in

-11
response with the variation of parameters, for our 10
convenience of study, we have used the same value -14
VDS = 50 mV
10
of interface trapped charge capacitance for both the
o
T = 20 C

samples. 10
-17

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Drain to Source Voltage (V)
MOS Capacitance (F/cm )
2

-8
8.5x10 Vds = 50 mV
o
T = 20 C
Fig 5: IDS vs. VGS plot at 20o C and VDS = 50 mV
-8
8.0x10
-8
7.5x10
-3
-8
7.0x10 10
MOS Capacitance (3.5nm)
Drain Current (A)
-8
6.5x10 MOS Capacitance (2.2nm) VGS = 0.8 V
o
T = 20 C
-4
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 10
Gate Voltage (V)
3.5 nm alpha model
-5 3.5 nm proposed model
o 10
Fig 4: MOS Capacitance, CMOS vs. VGS at 20 C 2.2 nm alpha model
2.2 nm proposed model
The above figure deals with the subthreshold MOS
capacitance (CMOS) for both the specimens. It appears 0.0 0.5 1.0 1.5 2.0
that from the very beginning of the subthreshold Drain to Source Voltage (V)
region the 2.2 nm sample maintains a lead in the
values of CMOS than the other sample. This statement Fig 6: IDS vs. VDS plot at 20o C and VGS = 0.8 V
can be verified with the discussion related with the
value of insulator capacitance in case of the
specimens and that values are higher for the 2.2 nm
sample due to less thick gate oxide. Both curves lead -2
10
to a less steep manner to the end of the subthreshold
region of operation. This gives the idea of the
Drain Current (A)

VGS = 1 V
decrease of the impact of the depletion capacitance T = 20 C
o

that increases according to the application of the gate 10

-3

bias, VGS.
3.5 nm alpha model
3.5 nm proposed model
Studying the IDS vs. VGS curves, we find a good -4 2.2 nm alpha model
impact of the newly engaged trapped charges and 10 2.2 nm proposed model
depletion capacitance. For both the specimens, the 0.0 0.5 1.0 1.5 2.0
proposed model shows (Fig: 5) lower values at the
Drain to Source Voltage (V)
initial points of the subthreshold region. In the initial
region, alpha model shows a quite constant rise in the
Fig 7: IDS vs. VDS plot at 20o C and VGS = 1 V
values of drain current, where the proposed model
shows a slightly curved rise in the drain current
Now we focus on the dependence of drain current on
values. This may be taken as an effect of the
drain to source voltage with a fixed gate bias voltage.
appearance of the newly arranged capacitances that
The IDS vs. VDS plot for VGS = 0.8 volt (Fig: 6) shows
are varied with the applied gate bias. We find that for
that the drain current reaches to the saturation region
both the samples, the value of subthreshold slope
at a very steep rate while it appears to be quite
calculated from the proposed model is higher than
delayed for application of higher gate bias (Fig: 7, 8
and 9).
 oxide devices. Moreover, study of subthreshold slope
shows lower values for tunnelling oxide thickness
(~2 nm) than that of the existing physical alpha-
VGS = 1.5 V
power law MOSFET model. This phenomenon can
be considered as a practical impact of the
Drain Current (A)

-2 o
10 T = 20 C
incorporation of interface trapped charges in the
subthreshold regime.
-3 3.5 nm alpha model
10
3.5 nm proposed model REFERENCES
2.2 nm alpha model
2.2 nm proposed model
[1] Keith A. Bowman, Blanca L. Austin, John C. Able and
-4 James D. Meindl, “A Physical Alpha-Power Law
10
MOSFET Model,” IEEE Journal of Solid-State
0.0 0.5 1.0 1.5 2.0
Circuits, vol. 34, no. 10, pp: 1410-1414, October 1999.
Drain to Source Voltage (V)
[2] T. Sakurai and A. R. Newton, “Alpha-Power Law
MOSFET Model and Its Application to CMOS Inverter
Fig 8: IDS vs. VDS plot at 20o C and VGS = 1.5 V Dealy and Other Formula,” IEEE Journal of Solid-State
Circuits, vol. 25, pp: 584-594, April 1990.
[3] B. Austin, K. Bowman, X. Tamg and J. D. Meindl, “A
-1
10 Low Power Transregional MOSFET Model for
Complete Power Dealy AAnalysis of CMOS Gigascale
VGS = 2 V th
Drain Current (A)

Integration (GSI),” in Proc. 11 Annu. IEEE Int. ASIC

o
T = 20 C
-2
10
3.5 nm alpha model
3.5 nm proposed model
-3
2.2 nm alpha model
10
2.2 nm proposed model
0.0 0.5 1.0 1.5
Drain to Source Voltage (V)
Fig 9: IDS vs. VDS plot at 20o C and VGS = 2 V
Figure 8 and 9 shows the IDS vs. VDS curves for
VGS = 1.5 and 2 volts respectively. Here both the
specimens attain the saturation point at
comparatively delayed points than figure 6 and 7.
Now, in case of the drain leakage currents, the
specimens even produce a comparatively low value
of leakage currents, which were predicted earlier [9].
The current levels are lower for the proposed model
in all the figures as we can clearly define it to be an
effect of the engagement of a parallel combination of
(comparatively low valued) depletion capacitance
(Cd) and interface trapped charge capacitance (Cit) in
series with the oxide capacitance (Cox). As a result
we find a total MOS capacitance, CMOS, of a
comparatively low value that ultimately creates the
noticeable difference in drain current between the
two models.
Conf. pp: 125-129, September 1998.
[4] S. L. Gaverick and C. G. Sodini, “A simple model for
scaled MOS transistors that includes fielddependent
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including velocity saturation,” IEEE Journal of
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[6] Ben. G. Streetman and Sanjay Banarjee, “Solid-State
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[7] Yannis Tsividis, “The MOS Transistors,” WCB-
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[8] Guido Goreseneken, Herman E. Maes, Nicolas
Beltran and Roger F. De Keersmaecker, “A Reliable
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oxides,” IEEE Transactions on Electron Devices,
vol. 47, Issue 8, August 2000.

5. CONCLUSION
A revised physical alpha-power law MOSFET model
for ultrathin oxide MOSFETs has been proposed.
Incorporation of previously neglected effects of
interface states has revealed that the existing alpha
model overestimated the drive current for ultrathin