Mupee 4

CONVERTING ASSEMBLY LANGUAGE
INSTRUCTION TO MACHINE CODE

• The machine code specifies things like
- what operation is to be performed,
- what operand or operands are to be used,
- whether the operation is performed on byte or word data,
- whether the operation involves operands that are located in registers
or a register and a storage location in memory, and
- if one of the operands is in memory, how its address is to be
generated
• Some instructions can be encoded with just 1 byte, others in 2 bytes, and
many require more. The maximum number of bytes an instruction might
take is 6
Single byte instructions generally specify a simpler operation with a
register or a flag bit.
• Most multi-byte instructions use the general instruction format
BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
LOW HIGH LOW HIGH

DISP/ DISP/ DATA DATA
Opcode D W MOD REG R/M DATA DATA
REGISTER OPERAND / REGISTERS TO USE IN EA CALCULATION
REGISTER OPERAND/ EXTENSION OF OPCODE
REGISTER MODE / MEMORY MODE WITH DIPLACEMENT LENGTH
WORD / BYTE OPERATION
DIRECTION IS TO REGISTER / DIRECTION IS FROM REGISTER
OPERATION ( INSTRUCTION ) CODE
CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 1

CODE and INSTRUCTION SET OF 8086 dnk kumar
1. OPCODE field ( 6 bits ) specifies the operation such as add, subtract,
move.
2. REGISTER DIRECTION bit ( D bit ) specifies whether the register
operand that is specified in byte 2 is the source or destination operand .
A logic 1 at this bit position indicates that the register operand is a
destination operand, a logic 0 indicates that it is a source operand.
3. DATA SIZE bit ( w bit ) 0  8 bits, 1  16 bits
4. MODE ( MOD ) field ( 2 bits ) Mod field together with R/M field
specifies the second operands. Mod indicates whether the operand is in a
register or memory. Notice that in the case of a second operand that is
in a register, the MOD field is always 11.
5. REGISTER/MEMORY ( R/M ) field ( 3 bits ) R/M field along with W bit
from byte 1 selects the register
6. REG ( Register field ) ( 3 bits ) field is used to identify the register for
the first operand. This is the operand that was defined as the source or
destination by the D bit in byte 1.
REG W=0 W=1
000 AL AX
REGISTER 001 CL CX
FIELD
010 DL DX
ENCODING
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Code Explanation
0 Memory Mode, no displacement follows MODE

1 Memory Mode, 8 bit displacement follows FIELD
10 Memory Mode, 16 bit displacement follows ENCODING
11 Register mode ( no displacement )
Except when R/M = 110, then 16 bit displacement follows
MOD = 11 EA CALCULATION
R/M W=0 W=1 R/M MOD = 00 MOD = 01 MOD = 10
000 AL AX 000 [BX]+[SI] [BX]+[SI]+D8 [BX]+[SI]+D16

001 CL CX 010 [BX]+[DI] [BX]+[DI]+D8 [BX]+[DI]+D16
010 DL DX 010 [BP]+[SI] [BP]+[SI]+D8 [BP]+[SI]+D16
011 BL BX 011 [BP]+[DI] [BP]+[DI]+D8 [BP]+[DI]+D16
100 AH SP 100 [SI] [SI]+D8 [SI]+D16
101 CH BP 101 [DI] [DI]+D8 [DI]+D16
110 DH SI 110 DIRECT ADDRESS [BP]+D8 [BP]+D16
111 BH DI 111 [BX] [BX]+D8 [BX]+D16
R/M FIELD ENCODING
Example:
The instruction MOV BL, AL
Stands for “move the byte contents from source register AL to destination
register BL using the general format, show how to encode the instruction in
machine code. Assume that the 6 bit Opcode for the move operation is
100010
Solution: In byte 1 the first 6 bits specify the move operation and must be
100010
Opcode = 100010
The next bit, which is D, indicates whether the register that is specified by
the REG part of byte 2 is a source or destination operand. Let us say that we

will encode AL in the REG field of byte2, therefore , D is set equal to 0, for
source operand
D=0
The last bit (W) in byte 1 must specify a byte operation. For this reason, it
is also set to 0
W=0
This leads to BYTE 1 = 10001000B = 88H
In byte2, the source operand, which is specified by the REG field, is AL.
The corresponding code is
REG = 000
Since the second operand is also a register, the MOD field is mode 11
The R/M field specifies that the destination register is BL and the code is
011
MOD = 11 R/M = 011
Therefore
BYTE 2 = 11000011B = C3H
The entire hexadecimal code for the instruction is
MOV BL, AL = 88C3h

INTERNAL FORMAT OF INSTRUCTIONS
1. Cwd Convert word t double word

Opcode
Cbw Convert byte to word
2. inc/dec/neg/mul/div register
Opcode mod r/m
mov/add/sub register, register
3. inc/dec/neg/mul/div memory
mov/add/sub memory, register Opcode mod r/m address
mov/add/sub register, memory
4. mov/add/sub register, byte constant Opcode mod r/m constant
5. mov/add/sub register, word constant Opcode mod r/m constant
6. mov/add/sub memory, byte constant
Opcode mod r/m address constant
7. mov/add/sub memory word constant
Opcode mod r/m address constant

Example :
The instruction ADD AX, [SI]
Stands for “ add the 16 bit contents of the memory indirectly specified by
SI to the contents of AX “. Encode the instruction in machine code. The
Opcode for this add operation is 000000b
Solution: To specify a 16 bit add operation with a register as the

destination, the first byte of machine code will be
BYTE 1 = 00000011b = 03 h
The REG field bits in byte 2 are 000 to select AX as the destination
register. The other operand is in memory and its address is specified by the
contents of SI with no displacement. For indirect addressing using SI with
no displacement. MOD equals 00 and R/M equals 100
MOD = 00
R/M = 100
This gives BYTE 2 = 00000100b = 04 h
Thus the machine code for the instruction is
ADD AX,[SI] = 0304h
Example :
What is the machine code for the instruction, XOR CL, [1234h].
This instruction stand for exclusive-OR the byte of data at memory address
1234h with the byte contents of CL. The Opcode for EX-OR is 001100b
Solution: Using the XOR Opcode 001100b, 1 for destination operand, and 0
for byte data. We get
BYTE 1 = 00110010b = 32h

The REG field has to specify CL, which makes it equal to 001 . In this case a
direct address has been specified for operand 2 . This requires MOD = 00
and R/M = 110.
Thus
BYTE 2 = 00001110b = 0Eh
To specify the address 1234h we must use bytes 3 and 4. The least
significant byte of the address is encoded first, followed by the most
significant byte.
This gives,
BYTE 3 = 34h
BYTE 4 = 12h
The entire machine code form of the instruction is

XOR CL, [1234h] = 320E3412h
Example:
The instruction ADD [BX][DI]+DISP, AX
Means “ add the word contents of AX to the contents of the memory
location specified by based-indexed addressing mode”. The opcode for the
add operation is 000000b and assume that DISP equals 1234h
Solution. The add Opcode, which is 000000b , a 0 for source operand, and a
1 for word data, gives
BYTE 1 = 00000001b = 01h
The REG field in byte 2 is 000 to specify AX as the source register, since
there is a displacement and it needs 16 bits for encoding, the MOD field
obtained is 10. The R/M field, which is set to 001 for an effective address
generated from DI and BX.
This gives the second byte as
BYTE 2 – 10000001b = 81 h

The displacement 1234h is encoded in the next 2 bytes, with the least
significant byte first. Therefore the machine code that results is
ADD [BX][DI]+DISP, AX = 01813412h
The general format cannot be used to encode all the instructions that can be
executed by 8086. Minor modifications must be made to this general format
to encode a few instructions. In some instructions, one or more single-bit
fields are needed. These 1-bit fields and their functions are shown below.
Field Value Function
S 0 No sign extension
1 Sign extend 8-bit immediate data to 16 bit if W =1
V 0 Shift/Rotate count is one

1 Shift/Rotate count is specified in CL register
Z 0 Repeat/Loop while zero flag is clear

1 Repeat/Loop while zero flag is set
For instance the general format of the repeat (REP) instruction is
REP = 111001z
Here bit z is made 1 or 0 depending on whether the repeat operation is to be

done when the zero flag is set or when it is reset. Similarly, the other two
bits, S & V, are used to encode sign extensions for arithmetic instructions
and to specify the source of the count for shift or rotate instruction
respectively.
Register SR
ES 00
CS 01
SS 10
DS 11

Instructions that involve a segment register need a 2 bit field to encode
which register to be affected. This field is called SR field.
Example:
The instruction
Mov WORD PTR [BP][DI]+1234h, 0ABCDh
Stands for “ move the immediate data word ABCDh into the memory location
specified by based-indexed addressing mode”.
Express the instruction in machine code.
Solution:
Since this instruction does not involve one of the registers as an operand, it
does not follow the general format we have been using. The format of byte 1
is an immediate data-to-memory move is
1100011W
In our case, we are moving word size data:
Therefore W = 1
BYTE1 = 11000111b = C7h
BYTE2 = (MOD)000(R/M)
For a memory operand using a 16 bit displacement, MOD = 10, and for based
indexed addressing using BP and DI with a 16 bit displacement R/M = 011
BYTE2 = 10000011b = 83h
Byte 3 and 4 encode the displacement with its low byte first. Thus, for a
displacement 1234h,
BYTE3 = 34h and
BYTE4 = 12h
Last bytes 5 & 6 encode the immediate data, also with LSByte first,
For data word ABCDh, we get
BYTE5 = CDh
BYTE6 = Abh
Therefore
Mov WORD PTR [BP][DI]+1234h,DS
= C7833412CDABh

Example:
The instruction
Mov [BP][DI]+1234h, DS
Stands for “ move the contents of the data segment register to the memory
location specified by based-indexed addressing mode”. Express the
instruction in machine code.
Solution:
The instruction is encoded as

10001100(MOD)0(SR)(R/M)(DISP)
MOD & R/M are same as in previous example. That is MOD = 10 and
R/M = 011
Moreover, the value of DISP is given as 1234h.
Finally we find that to specify DS the SR field is
SR = 11
Therefore the code is
10001100100110110011010000010010b = 8C9B3412h

DEBUG
Command Syntax
Register R [register name]

Examine or modify the contents of an internal register
Quit Q
End use of the DEBUG Program
Dump D [address]
Dump the contents of memory to the display
Enter E [address][list]
Examine or modify the contents of the memory
Fill F [starting address][ending address][list]

Fill a block of memory with the data in the list
Move M [starting address][ending address][destination address]

Move a block of data from a source location in memory to a
destination location.
Compare C [starting address][ending address][destination address]

Compare two blocks of data in memory and display the location that
contains different data
Search S [starting address][ending address][list]

Search through a block of data in memory and display all locations
that match the data in list
Unassemble U [starting address][ending address]

Unassemble the machine code into its equivalent assembler instructins
Write W [starting address][drive][starting sector][Number of sectors]

Save the contents of memory in a file on a diskette

Load L [starting address][Drive][starting sector][number of sectors]
Load memory with the contents of a file on a diskette.
Assemble A [starting address]

Assemble the instruction into machine code and store in memory
Trace T [address][number]
Trace the execution of the specified number of instructions.
Go G [starting address][breakpoint address]

Execute the instructions down through the breakpoint address
Notations used for displaying the status flags
Flag Meaning Set Reset
OF overflow OV NV
DF direction DN UP
IF interrupt EI DI
SF sign NG PL
AF auxiliary carry AC NA
ZF zero ZR NZ
PF parity PE PO
CF carry CY NC
Example:
Issue commands to the debugger on the PC that will cause the value in BX to
be modified to FF00h and the verify that this new value exists in BX.
C:> DEBUG
-R BX
BX 0000
:FF00
-R BX
BX : FF00
:

a. –R
b. –D
c. –D 1076:0100
d. –D DS:100
e. –D 100
f. –D DS:200 201
g. –D CS: 0 F
h. –D ES: 0 F
i. –D SS: FFEE FFFD
j. –E DS:100 FF FF FF FF FF
-D DS:100 104
1076:0100 FF FF FF FF FF
-
k. –E DS:200 “ASCII”
-D DS:200 204
1076:0200 61 73 63 69 69
-
l. –F 100 11F 22
-D 100 11F
m. –F 120 13F 33
-F 140 15F 44
-D 120 15F
n. –F 100 11F 11
-M 100 11F 160
-D 100 17F
o. –C 100 10F 120
p. –S 100 17F 33
q. –E CS:100 88 C3
-D CS:100 101
1076:0100 88 C3
-U CS:00 101
1076 : 0100 88C3 MOV BL,AL
r. –E CS:200 03 04
-D CS:200 201
1076:0200 03 04
-U CS:200 201
1076 : 0200 0304 ADD AX,[SI]

s. –A CS:100
1076:0100 ADD [BX+SI+1234],AX
1076:0104
-D CS:100 103
1076:0100 01 80 34 12
-Q
t. T
INSTRUCTION POINTED BY CURRENT CS;IP WILL BE EXECUTED
u. T=CS:100
INSTRUCTION AT CS:100 WILL BE EXECUTED
v. –E CS:100 03 04
-U 100 101
1076:0100 03 04 ADD AX,[SI]
-R AX
AX 0000
: 1111
-R SI
: 1234
-E DS:1234 22 22
-R
AX=1111 BX=0000 CS=0000 DX=0000 SP=FFEE BP=0000 SI=1234 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 IP=0100 NV UP EI PL NZ NA PO NC
1076:0100 03 04 ADD AX,[SI] DS=1234=2222
-D DS:1234 1235
1076:1230 22 22
-T=CS:100
AX=3333 BX=0000 CX=0000 DX=0000 SP=FFEE BP=0000 SI=1234 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 IP=0102 NV UP EI PL NZ NA PE NG
1076:0102 93 XCHG BX,AX

INSTRUCTION SET OF 8086
• The instruction set of a microprocessor defines the basic operations that
a programmer can make the device perform
• This powerful instruction set contains 117 basic instructions. The wide
range of operands and addressing modes permitted for use with these
instructions further expand the instruction set into many more
instructions executable at the machine code level.
• For instance the basic MOV instruction expands into 32 different
machine level instructions [24 memory addressing 8 register addressing]
• Data transfer instructions – arithmetic instructions, logic instructions,
shift instructions, and rotate instructions
MOV Instruction
Mnemonic Meaning Format Operation Flags affected
MOV Move Mov D,S [S]  [D] None
Destination Source
Memory Accumulator
Accumulator Memory
Register Register
Register Memory
Memory Register
Register Immediate
Memory Immediate
Seg-Reg Reg 16
Seg-Reg Mem 16
Reg 16 Seg-Reg
Memory Seg-Reg

Example:
Mov DX, CS
[CS]  [DX]
In all memory reference Mov instruction, the machine code for the
instruction includes an offset address relative to the contents of the data
segment register
Mov [sum],AX
Let DS contain 0200h
SUM correspond to 1212h
Physical address
PA = 02000 + 1212 = 03212h
Therefore [AL]  [memory location 03212h]

[AH] [memory location 03213h]
Example:
What is the effect of executing the instruction
Mov CX, [SOURCE-MEM]
Where SOURCE-MEM is the memory location offset 20h relative to the
data segment starting at address 1A000h ?
Solution:
[[DS]0 + 20h]  [CL]
[[DS]0 + 20h + 1h ]  [CH]
OR
CL is loaded with contents held at memory address
1A000h + 20h = 1A020h
CH is loaded with 1A000h + 20h + 1h = 1A021h

C:> DEBUG
-R
- -------------
- -------------
-A
1076:0100 MOV CX, [20]
1076:0104
-R DS
DS 1076
:1A00
-E 20 55 AA
-T
AX=0000 BX=0000 CX=AA55 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
DS=1A00 ES=1076 SS=1076 ES=1076 IP=0104 NV UP EI PL NZ NA PO NC
1076:0104 DEC SI
-Q
In this example the value pointed by SOURCE-MEM is initialized by AA55h
XCHG instruction
XCHG AX,DX
[AX original]  [DX]
[DX original]  [AX]
[AX]  [DX]
XCHG Exchange XCHG D,S [D] [S] None
Destination Source
Accumulator Reg 16
Memory Register
Register Register

Example:
XCHG [SUM],BX
[ [DS]0 + SUM ] BX
If [DS] = 1200h
SUM = 1234h
PA = 12000h + 1234h = 13234h
If this location contains FF & 00

And if [BL]  AAh
[BH]  11h
Executing the instruction, the following 16 bit swap is performed
[13234h] [BL]
[13235h] [BH]
Therefore [BX] = 00FFh

[SUM] = 11AAh
C:> debug
-R
- ----------
- ----------
-A 1100:101
1100:0101 XCHG [1234],BX
1100:0105
-R BX
BX 0000
: 11AA
-R DS
DS 1076
:1200
-R CS
CS 1076
:1100
-R IP
IP 0100

:101
-R
AX=0000 BX=11AA CS=0000 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
1100:0101 871E3412 XCHG BX,[1234] DS:1234=0000
-E 1234 FF 00
-U 101 104
1100:0101 871E3412 XCHG BX,[1234]
-T
AX=0000 BX=00FF CS=0000 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
1100:0105 0000 ADD [BX+SI],AL DS:00FF=00
-D 1234 1235
1200:1230 AA11
-Q
The translate - XLAT instruction
XLAT Translate XLAT [ [AL]+[BX]+[DS]0][AL] None
Simplifies implementation of the lookup table operation .

The values in both AL and BX must be initialized
Execution of XLAT replaces the contents of AL by the contents of the

accessed lookup table location.
The physical address of this element in the table is derived as
PA = [DS]0 + [BX] + [AL]
Let us assume that [DS] = 0300h

[BX] = 0100h
[AL] = 0Dh
0Dh represent the ASCII CR [ carriage return ]

PA = [DS]0 + [BS] + [AL]
= 03000h + 0100h + 0Dh = 0310Dh
[0310DH]  [AL]
Assuming that this memory location contains 52h ( EBCDIC carriage return)
This is replaced in AL
[AL] = 52h
LED  LOAD REGISTER WITH EFFECTIVE ADDRESS

LDS  LOAD REGISTER AND DATA SEGMENT REGISTER
LES  LOAD REGISTER AND EXTRA SEGMENT REGISTER
Mnemonic format operation flags affected
LEA LEA Reg16, EA [ EA ]  [ REG16 ] None
LDS LDS Reg16, Mem32 [Mem32][REG16]

[Mem32][DS] None
LES LEA Reg16, Mem32 [Mem32][Reg16]

[Mem32+2][ES] None
Example:
LEA SI, [INPUT]
It loads the SI register with an offset address value. The value of this
offset is represented by the value of INPUT. INPUT is encoded following
the instruction Opcode in the code segment memory.
LDS SI, [200]

PA = 12000h + 0200h = 12200h

Address Memory content instruction
1300
0100
11100 C5 LDS SI, [200]
11101 36
1100 11102 00
1200 11103 20
11104 XX NEXT INTRN.
12000 XX
12001 XX
0020
12200 20
12201 00
12202 00
xxxx 12203 13
13000 XX NEW DATA

13001 XX SEGMENT

C:> DEBUG
-R IP
IP 0100
:
-R CS
CS 1076
: 1100
-R DS
DS 1076
: 1200
-R SI
SI 0000
:
-A CS:100
1100:0100 LDS SI, [200]
1100:0104
-E 200 20 00 00 13
-T
1100:0104 1200 ADC AL, [BX+SI] DS:0020=00
-Q

ARITHMETIC INSTRUCTION
The status that results from the execution of an arithmetic instruction is

recorded in the flags.
Arithmetic instructions are addition, subtraction, multiplication and division.
On unsigned or signed binary bytes or words unpacked or packed decimal

byte ASCII numbers.
Flags  CF, AF, SF, ZF, PF AND OF
ADDITION
ADD Add byte or word

ADC Add byte or word with carry
INC Increment byte or word by 1
AAA ASCII adjust for addition
DAA Decimal adjust for addition
SUBTRACTION
SUB Subtract byte or word

SBB Subtract byte or word with borrow
DEC Decrement byte or word by 1
NEG Negate byte or word
AAS ASCII adjust for subtraction
DAS Decimal adjust for subtraction
MULTIPLICATION
MUL Multiply byte or word unsigned

IMUL Integer multiply byte or word
AAM ASCII adjust for multiply

DIVISION
DIV Divide byte or word unsigned

IDIV Integer divide byte or word
AAD ASCII adjust for division
CBW Convert byte to word
CWD Convert word to double word
ADDITION
ADD Addition ADD D,S [S]+[D][D] OF SF ZF AF PF CF
ADC Add with ADC,D,S [S]+[D]+[CF][D] OF SF ZF AF PF CF

Carry Carry  [CF]
INC Increment INC D [D] + 1  [D] OF SF ZF

AF PF
by 1
AAA ASCII adj AAA ----- AF CF

For addition OF SF ZF PF undefined
DAA Decimal adj DAA ----- SF ZF AF PF CF

For addition OF undefined
Example:
Assume that the AX and BX register contain 1100h and 0ABCh, respectively.
What are the results of executing the instruction
ADD AX,BX
Solution:
[BX] + [AX] = 0ABCh + 1100h = 1BBCh

[AX] = 1BBCh
C:> DEBUG
-A 1100:0100
1100:0100 ADD AX,BX
1100:0102
-R AX
AX 0000
: 1100
-R BX
BX 0000
: 0ABC
-U 1100 : 0100 0101
1100:0100 01D8 ADD AX,BX
-T=1100:0100
AX=1BCC BX=0ABC CX=0000 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
1100:0102 0002 ADD [BP+SI],AL
-Q
Example:
The original contents of AX, BL, memory location SUM, and carry flag [CF]
are 1234h, Abh, 00CDh and 0h respectively. Describe the results of
executing the following sequence of instructions.
ADD AX, [SUM]

ADC BL, 05h
INC [SUM]
Solution:
[AX]  [AX] + [SUM] = 1234h + 00CDh = 1301h
The carry flag remains reset.
The second instruction adds to the lower byte of the base register [BL], the
immediate operand 5h and carry flag, which is 0h.
This gives
[BL]  [BL]+ immediate operand +[CF] = Abh + 5h + 0h = B0h

Since no carry is generated CF stays reset.
The last instruction increments the content of memory location SUM by 1
[SUM]  [SUM] + 1h = 00CDh + 1h = 00Ceh
Instruction [AX] [BL] [SUM] [CF]
Initial state 1234 AB 00CD 0

ADD ax,sum 1301 AB 00CD 0
ADC bl,05h 1301 B0 00CD 0
INC sum 1301 B0 00CD 0
Example:
What is the result of executing the following instruction sequence?
ADD AL, BL
AAA
Assume that AL contains 32h which is the ASCII code for number 2, BL
contains 34h which is the ASCII code for number 4, and AH has been
cleared.
Solution:
[AL]  [AL] + [BL] = 32h + 34h = 66h
Next the result is adjusted to give its equivalent decimal number. This is
done by execution of the AAA instruction. The equivalent of adding 2 and 4
is decimal 6 with no carry.
Therefore the result of after the AAA instruction
[AL] = 06h [AH] = 00h

SUBTRACTION
SUB Subtraction SUB D, S [D] – [S]  [D] OF SF ZF AF PF CF

Borrow  [CF]
SBB Subtraction SBB D, S [D]-[S]-[CF][D] OF SF ZF AF PF CF

with borrow
DEC Decrement by1 DEC D [D] – 1  [D] OF SF ZF AF PF
NEG Negate NEG D 0 -[D]  [D] OF SF ZF AF PF CF

1  [CF]
DAS Decimal adj DAS SF ZF AF PF CF

For subtraction OF undefined
AAS ASCII adj AAS AF CF

For subtraction OF SF ZF PF undefined
Destination Source Destination Destination
Register Register Reg 16 Register

Register Memory Reg 8 Memory
Memory Register Memory
Accumulator Immediate
Register Immediate for DEC for NEG
Memory Immediate
For SUB AND SBB
Example:

Assuming that the contents of register BX and CX are 1234h and 0123h
respectively and the carry flag is 0. What will be the result of executing the
following instruction?
SBB BX,CX
Solution:
[BX] – [CX] – [CF]  [BX]

we get
[BX] = 1234h – 0123h – 0h = 1111h
C:> DEBUG
-R
1076:0100 4D DEC BP
-R BX
BX 0000
:1234
-R CX
CS 0000
:1234
-R CX
:0123
-R F
NV UP EI PL NZ NA PO NC –
-A
1076:0100 SBB BX,CX
1076:0102
-R
AX=0000 BX=1234 CS=0123 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
1076:0100 19CB SBB BX,CX
-U 100 101
1076:0100 19CB SBB BX,CX
-T
DS=1076 ES=1076 SS=1076 CS=1076 IP=0102 NV UP EI PL NZ NA PE NC
1076:0102 0003 ADD [BP+DI],AL

-Q
Example:
Assuming that register BX contains 003Ah. What is the result of executing
the following instruction?
NEG BX
Solution:
Executing the NEG instruction causes the 2’s complement Subtraction, that
follows 0000h – [BX] = 0000h + 2’s complement of 003Ah
= 0000h + FFC6h
= FFC6h
This value is placed in BX
[BX] = FFC6h
C:> DEBUG
-R BX
BX 0000
:3A
-A
1076:0100 NEG BX
1076:0102
-R BX
BX 003A
:
-U 100 101
1076:0100 F7DB NEG BX
-T
AX=0000 BX=FFC6 CX=0000 DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 IP=0102 NV UP EI NG NZ AC PE CY
1076:0102 0003 ADD [BP+DI]. AL
-Q

MULTIPLICATION AND DIVISION INSTRUCTION
MUL Multiply MUL S [AL].[S8][AX] OF CF

(Unsigned) [AX].[S16][DX],[AX] SF ZF AF PF Undefined
DIV Division DIV S 1. Q[[AX]/[S8]][AL] OF SF ZF AF PF CF

(Unsigned) R[[AX]/[S8]][AH] Undefined
2. Q[[DX,AX]/[S16]][AX]
R[[DX,AX]/[S16]][DX]
If Q is FFh in case 1 or FFFFh in case 2 then type 0 interrupt occurs
IMUL Integer IMUL S [AL].[S8]  [AX] OF CF

Multiply [AX].[S16][DX],[AX] SF ZF AF PF Undefined
(Unsigned)
IDIV Integer IDIV S 1. Q[[AX] / [S8]]  [AX] OF SF ZF AF PF CF

Divide R[[AX] / [S8]]  [AH] Undefined
(Unsigned) 2. Q[[DX,AX]/[S6]][AX]
R[[DX,AX]/[S16]][DX]
If Q is positive and exceeds 7FFFh, or if Q is negative and becomes
less than 8001h then type 0 interrupt occurs
AAM Adjust AL AAM Q[[AL]/10] [AH] SF ZF PF

For multiplication R[[AL]/10] [AL] OF AF CF Undefined
AAD Adjust Ax AAD [AH].10 +[AL]  [AL] SF ZF PF

For division 00  [AH] OF AF CF Undefined
CBW Convert CBW [MSB OF AL]  [ ALL BITS OF AH] None

Byte to word

CWD Convert CWD [MSB OF AX]  [ ALL BITS OF DX] None
Word to double word
Source : Reg8 Reg16 Mem8 Mem16

Example:
If the contents of AL equals –1 and the contents of CL are –2, what will be
the result produced in AX by executing the following instruction?
MUL CL and IMUL CL
Solution:
The first instruction multiplies the content of AL and CL as unsigned
numbers
-1 = 11111111b = FFh
-2 = 11111110b = Feh
Then executing MUL
[AX] = 11111111b x 11111110b = 1111110100000010b = FD02h
The second instruction multiply the same two numbers as signed numbers
[Ax] = -1h x –2h = 2 h
C:> DEBIUG
-R AX
AX 0000
:FF
-R CX
CS 0000
:FE
-A
1076:0100 MUL CL
1076:0102
-R AX
AX 00FF
:
-R CX
CS 00FE
:
-U 100 101
1076:0100 F6E1 MUL CL

-T
AX=FD02 BX=0000 CX=00FE DX=0000 SP=FFEE BP=0000 SI=0000 DI=0000
DS=1076 ES=1076 SS=1076 CS=1076 IP=0102 OV UP EI NG NZ NA PO CY
1076:0102 0003 ADD [BP+DI],AL
-Q
Example;
What is the result of executing the following sequence of instruction ?
MOV AL, 0A1h
CBW
CWD
Solution:
The first instruction leads AL with A1h . This gives
[AL] = A1h = 10100001b
Executing the second instruction extends the MSB of AL which is 1, into all
bits of AH.
The result is
[AH] = 11111111b = FFh
therefore [AX] = FFA1h
This completes conversion of the byte in AL to a word in AX
The last instruction loads each bit of DX with the MSB of AX.
This bit is also one
[DX] = FFFFh


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CONVERTING ASSEMBLY LANGUAGE

INSTRUCTION TO MACHINE CODE

• Most multi-byte instructions use the general instruction format

BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6

LOW HIGH LOW HIGH

REGISTER OPERAND / REGISTERS TO USE IN EA CALCULATION

REGISTER OPERAND/ EXTENSION OF OPCODE

REGISTER MODE / MEMORY MODE WITH DIPLACEMENT LENGTH

WORD / BYTE OPERATION

DIRECTION IS TO REGISTER / DIRECTION IS FROM REGISTER

OPERATION ( INSTRUCTION ) CODE

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 1

REG W=0 W=1

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 2

0 Memory Mode, no displacement follows MODE

000 AL AX 000 [BX]+[SI] [BX]+[SI]+D8 [BX]+[SI]+D16

R/M FIELD ENCODING

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 3

The entire hexadecimal code for the instruction is

MOV BL, AL = 88C3h

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 4

1. Cwd Convert word t double word

4. mov/add/sub register, byte constant Opcode mod r/m constant

5. mov/add/sub register, word constant Opcode mod r/m constant

6. mov/add/sub memory, byte constant

Opcode mod r/m address constant

7. mov/add/sub memory word constant

Opcode mod r/m address constant

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 5

Solution: To specify a 16 bit add operation with a register as the

This gives BYTE 2 = 00000100b = 04 h

Thus the machine code for the instruction is

ADD AX,[SI] = 0304h

BYTE 1 = 00110010b = 32h

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 6

BYTE 2 = 00001110b = 0Eh

The entire machine code form of the instruction is

BYTE 1 = 00000001b = 01h

This gives the second byte as

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 7

ADD [BX][DI]+DISP, AX = 01813412h

Field Value Function

V 0 Shift/Rotate count is one

Z 0 Repeat/Loop while zero flag is clear

For instance the general format of the repeat (REP) instruction is

Here bit z is made 1 or 0 depending on whether the repeat operation is to be

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 8

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 9

The instruction is encoded as

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 10

Register R [register name]

Fill F [starting address][ending address][list]

Move M [starting address][ending address][destination address]

Compare C [starting address][ending address][destination address]

Search S [starting address][ending address][list]

Unassemble U [starting address][ending address]

Write W [starting address][drive][starting sector][Number of sectors]

CONVERTING ASSEMBLY LANGUAGE INSTRUCTION TO MACHINE 11

Assemble A [starting address]

Go G [starting address][breakpoint address]

Notations used for displaying the status flags

Flag Meaning Set Reset