8051 special function registers (SFRs)

Symbol ACC* B* PSW* SP DPTR DPL DPH P0* P1* P2* P3* IP* IE* TMOD TCON* TH0 TL0 TH1 TL1 SCON* SBUF PCON

Name Accumulator B register Program Status Word Stack Pointer Data Pointer 2 bytes Data Pointer low byte Data Pointer high byte Port 0 Port 1 Port 2 Port 3 Interrupt Priority Control Interrupt Enable Control Timer/Counter Mode Control Timer/Counter Control Timer/Counter 0 high byte Timer/Counter 0 low byte Timer/Counter 1 high byte Timer/Counter 1 low byte Serial Control Serial Data Buffer Power Control

Address 0E0H 0F0H 0D0H 81H

Contents after reset 00000000 00000000 00000000 00000111

82H 83H 80H 90H 0A0H 0B0H 0B8H 0A8H 89H 88H 8CH 8AH 8DH 8BH 98H 99H 87H

00000000 00000000 11111111 11111111 11111111 11111111 XXX00000 0XX00000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Indeterminate 0XXXXXXX

(* = bit addressable)

functional descriptions

PSW: Program Status Word (bit addressable)

(msb) |CY|AC|F0|RS1|RS0|OV|-|P| (lsb) Symbol CY AC F0 RS1 RS0 OV P Position PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 Name & Significance Carry flag. Auxiliary Carry flag. Flag 0 available to the user for general purpose. Register Bank select bit 1. (see note) Register Bank select bit 0. (see note) Overflow flag. User definable flag. Parity flag. Set/cleared by hardware to each instruction cycle to indicate an odd/even number of "one" bits in the Accumulator.

NOTE: RS1 0 0 1 1 RS0 0 1 0 1 REGISTER BANK 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH

PCON: Power Control Register (not bit addressable)

(msb) |SMOD|-|-|-|GF1|GF0|PD|IDL| (lsb)

Symbol SMOD

Position PCON.7

Name & Significance Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. Not implemented Not implemented

PCON.6 PCON.5

GF1 GF0 PD

PCON.4 PCON.3 PCON.2 PCON.1

Not implemented General-purpose flag bit. General-purpose flag bit. Power Down bit. Setting this bit activates the Power Down operation in the 8051BH. (Available only in CHMOS). Idle Mode bit. Setting this bit activates Idle Mode operation in the 8051BH. (Available only in CHMOS).

IDL

PCON.0

IE: Interrupt Enable Register (bit addressable)

If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled. (msb) |EA|-|ET2|ES|ET1|EX1|ET0|EX0| (lsb)

Symbol EA

Position IE.7

Name & Significance Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Not implemented. Enable/disable Timer 2 overflow or capture interrupt. (8052 only). Enable/disable serial port interrupt. Enable/disable Timer 1 overflow interrupt. Enable/disable external interrupt 1. Enable/disable Timer 0 overflow interrupt. Enable/disable external interrupt 0.

ET2 ES ET1 EX1 ET0 EX0

IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

INTERRUPT SOURCE IE0 TF0

VECTOR ADDRESS 0003H 000BH

IE1 TF1 RI & TI TF2 & EXF2 (8052 only)

0013H 001BH 0023H 002BH

IP: Interrupt Priority Register (bit addressable)

If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the corresponding interrupt has a higher priority. (msb) |-|-|PT2|PS|PT1|PX1|PT0|PX0| (lsb) Symbol PT2 PS PT1 PX1 PT0 PX0 Position IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 Name & Significance Not implemented. Not implemented. Defines the Timer 2 interrupt priority level (8052 only). Defines the serial port interrupt priority level. Defines Timer 1 interrupt priority level. Defines External interrupt 1 priority level. Defines Timer 0 interrupt priority level. Defines External interrupt 0 priority level.

TCON: Timer/Counter Control Register (bit addressable)

(msb) |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0|

Symbol TF1

Position TCON.7

Name & Significance Timer 1 overflow flag. Set by hardware when Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 On/Off.

TR1

TCON.6

TF0

TCON.5

Timer 0 overflow flag. Set by hardware when Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 On/Off. External Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected. Cleared by hardware when interrupt is processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. External Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected. Cleared by hardware when interrupt is processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

TR0 IE1

TCON.4 TCON.3

IT0

TCON.2

IE0

TCON.1

IT0

TCON.0

TMOD: Timer/Counter Mode Control Register (not bit addressable)

(msb) timer1> |GATE|C/T|M1|M0| timer0> |GATE|C/T|M1|M0| (lsb) Symbol GATE Name & Significance When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software control). Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for counter operation (input from Tx input pin). Mode selector bit. (see note) Mode selector bit. (see note)

C/T

M1 M0 NOTE: M1 0 0

M0 0 1

OPERATING MODE 0, 13-bit Timer (MCS-48 compatible). 1, 16-bit Timer/counter.

1 1

0 1

2, 8-bit Auto-Reload timer/counter. 3, (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit timer and controlled by Timer 1 control bits. 3, (Timer 1) Timer/counter 1 stopped.

SCON: Serial Port Control Register (bit addressable)

(msb) |SM0|SM1|SM2|REN|TB8|RB8|TI|RI| (lsb)

Symbol SM0 SM1 SM2

Position SCON.7 SCON.6 SCON.5

Name & Significance Serial Port mode select. (see note 1) Serial Port mode select. (see note 1) Enables the multiprocessor communications features in modes 2 & 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. (see note 2) Set/cleared by software to enable/disable reception. The 9th bit that will be transmitted in modes 2 & 3. Set/cleared by software. In modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in

REN TB8

SCON.4 SCON.3

RB8

SCON.2

TI

SCON.1

mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. RI SCON.0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software.

NOTE 1: SM0 0 0 1 SM1 0 1 0 MODE 0 1 2 DESCRIPTION Shift Register 8-bit UART 9-bit UART BAUD RATE Fosc./12 Variable Fosc./64 OR Fosc./32 Variable

9-bit UART

NOTE 2: SERIAL PORT SET-UP Mode 0 1 2 3 0 1 2 SCON 10H 50H 90H D0H NA 70H B0H SM2 Variation Single Processor environment (SM2 = 0) Single Processor environment (SM2 = 0) Single Processor environment (SM2 = 0) Single Processor environment (SM2 = 0) Multiprocessor environment (SM2 = 1) Multiprocessor environment (SM2 = 1) Multiprocessor environment (SM2 = 1)

F0H

Multiprocessor environment (SM2 = 1)

Alternate Functions of Port 3 (bit addressable)

(msb) |RD|WR|T1|T0|INT1|INT0|TXD|RXD| (lsb)

Symbol RD WR T1 T0 INT1 INT0 TXD RXD

Position P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

Name & Significance External Data Memory read strobe. External Data Memory write strobe. Timer/counter 1 external input. Timer/counter 0 external input. External interrupt 1. External interrupt 0. Serial output port. Serial input port.