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VHDL Tutorial
ECE 223
Fall 2005
By:Shahed Shahir
Email: sshahir@engmail.uwaterloo.ca
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Outline
VHDL Quick Look
Entity
Architecture
Component
HalfAdder
FullAdd
Generate if Statement
Selected Signal Assignment
Generics
How to develop VHDL code using Xilinx Project
Navigator
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VHDL Quick Look
1. Entity
2. Architecture
All the available signal types and functions can be imported by adding :
Library ieee;
Use ieee.stdlogic1164.all,
In C:
#include <stdio.h>
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Entity
entity < entity_identifier>is
Port(
<signal identifier> : <mode> <type>;
<signal identifier> : <mode> <type>;

<signal identifier> : <mode> <type>);

end < entity_identifier >;
Example:
entity QuarterAdder is
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end QuarterAdder ;
buffer
Inout
Out
In
mode
character
String
Integer
Boolean
Std_logic
type
Z (High impedance)
H (Weak High)
1 (High) 1
L (Week Low)
0 (Low) 0
- (Dont Care)
X(Unknown)
U(Uninitialized)
W(Week Unknown)
STD_logic Boolean
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Architecture
architecture <architecture_name> of <entity_identifier> is
[ architecture_declarative_part]
begin
<architecture_statement> ;
<architecture_statement> ;

<architecture_statement> ;
end <architecture_name>;
Example:
architecture main of QuarterAdder is
begin
o_s <= i_a xor i_b;
end main;
Concurrent statements
Int main (void)
{
Printf(Hello World);
}
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Component
Component < entity_identifier>
Port(
<signal identifier> : <mode> <type>;
<signal identifier> : <mode> <type>;

<signal identifier> : <mode> <type>);

end Component;
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VHDL Code For HalfAdder
entity HalfAdder is
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic;
o_c : out std_logic);
end HalfAdder ;
architecture main of HalfAdder is
component QuarterAdder
port(
i_a : in std_logic;
i_b : in std_logic;
o_s : out std_logic);
end component;
begin
o_c <= i_a and i_b;
A1: QuarterAdder port map( i_a, i_b, o_s);
end main;
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FullAdd
Library iieee;
Use ieee.stdlogic1164.all
Entity FullAdd is
port (
i_a, i_b,i_c : in std_logic;
o_s,o_c : out std_logic);
End FullAdd;
Architecture main of FullAdd is
Beging
o_s<=i_c xor i_a xor i_b;
o_c<=(i_c and ( i_a or i_b)) or (i_a and i_b);
End main;
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Generate-If Statement
Library ieee;
Use ieee.stdlogic1164all;
Entity adder is
Port (
ia, ib :in stdlogicvector(15 downto 0);
os: out stdlogicvector(15 downto 0);
o_c: out std_logic);
End adder;
Architecture main of adder is
Component fulladd
Port(
i_a, i_b, i_c : in std_logic;
o_s,o_c : out std_logic);
End component;
Component halfadd
Port(
i_a,i_b :in std_logic;
o_s,o_c : out std_logic);
End component;
Signal carry: stdlogicvector(14 downto 0):=000000000000000;
Signal a, b, s : stdlogicvector(15 downto 0):=0000000000000000;
Signal initialization
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Generate-If Statement (cont)
Begin
For i in 15 downto 0 generate
G1:iI i0 generate
HalIadd0 : halfadd --Label
Port map(a(0), b(0), s(0), carry(0));
End generate;
G2 : iI i15 generate
Fulladd15 : fulladd
Port map(a(15), b(15), carry(14) ,s(15), oc);
End generate;
G3 : iI i/0 and i/15 generate
Fulladdi : fulladd
Port map(a(i), b(i), carry(i-1),s(i), carry(i));
End generate;
End generate;
a<=i_a;
o_s<=s;
End main;
Generate with if
Concurrent statements
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Selected Signal Assignment
With <expression> select
<target> <= <waveform> when <choice>;
< waveform > when <choice>;
< waveform > when others;
Example:
Library ieee;
Use ieee.stdlogic1164.all;
Entity muxone is
Port(i0, i1, i2,i3: in stdlogic;
ic: in stdlogicvector( 1 downto 0);
o_q:out std_logic);
End muxone;
Architecture main of muxone is
Begin
With i_c select
oq i0 when 00;
i1 when 01;
i2 when 10;
i3 when others;
End main;
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Generics
ENTITY reg1 IS
generic( width : positive: 1); default value of 1
port(clk,r: IN std_logic;
d:IN stdlogicvector( 0 to width - 1 );
q:OUT stdlogicvector( 0 to width - 1));
end reg1;
ARCHITECTURE inIer oI reg1 IS
...
iI( r '1') then q (others => 0);

End infer
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY useit2 IS
port(clk,r: IN std_logic;
d1:IN std_logic_vector(3 downto 0);
q1:OUT std_logic_vector(3 downto 0));
end useit2;
ARCHITECTURE useit2 of useit2 IS
component reg1
generic(width:positive;
reset_value : positive);
port(
clk,r: IN std_logic;
d:IN std_logic_vector(width-1 downto 0);
q:OUT std_logic_vector(width-1 downto 0)
);
end component;
begin
a1:reg1 generic map (reset_value => 1 , width =>4) port map
(clk,r,d1,q1);
end useit2;
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How To Develop VHDL Code
Using Xilinx Project Navigator
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This brief tutorial will help you on how to start a VHDL
project on Xilinx Project Navigator 6.3i step by step.
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new project
Select a Name for the project
Select Schematic as the project type
Click Next
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Select the device properties
Click Next
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Click on New Source
Select a name for your VHDL code
Choose VHDL module
Click Next and click next
Click finish
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Click next
Click next
Click finish
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Any question or Comment?