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A 250M Hz clock for SOC systems

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. . Chen Jii BoanLiu , . , . i 'liistitiite of Microelectronics Tsingliua University , Beijing P.R.C . BeijingP.R.C , ., . . .~ Tcl: +86-'10;62795 100 'Tel: +86-10-6274685-33 . . E ;~n d h;iliu,ii~~ i ~i i i ~,. ~!s i i!i i l~i i i~i . ~ ~ I~i i . !~ i i~ .'~ i i l i , Eii~aIl: ~ i . ~ . ~. ~ i ~ ~ ~ ~ ! ~ ! j ~ ! ~ . ~ .
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Ah.qd-This pqIeq introduces a methoi to' implement a phase-locket1 lool) (PLL) based on ring oscillator. In order to reject the ,jitters, a .voltage r e p l a r is applied tu reduce the ~io\~er-supply noise, which is the mnst cnmmnn and dominant, souwe of, ,jitter. The simulation result s h o w that the voltage m regulator c achieve a power-supply rejection ratio
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(PSRR) greater than SOdB while VCO Oiierating at frequencies about ,1 G H i And it is in layout. The. system will be integrated in a'O.25-um 2-poly 5-metiil digital CMOS technolo=. . .,. ,
Inder Ternis-Clock regulator.
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generator, . . . . ,. .
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PLL,
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voltage
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Regulator . . vr+g2=2.2V Vregl=2. iv


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I . INTRODUCYION

In SOC systems. both analog and digital systems exist Digilal parls niay cause llie Yoltage supply variations. TI& iiiay affcct tlic a h l o g parts' perfonnance, including PLL. To rcgolate the supply of 1 : PLL is 1 c an effective inclliod lo niiiiimizc tlic jittcr. Previous . . work has slio\vii that the PLL acliieves a PSRR greaier !hnn 40 dB while operating at frcqocncies execding 4 GHz. The high lcycl of noise rcieclion cxcceds that of earlier dcsigns by &iig il conibini~tion both passive of and active filteiiiig of the PLL's analog supply

voltage. The' PLL systeili has been iutegrated 'in a (I. 15- I-I 111 single-poly 5-nictal digital CMOS teclinolopy. The iiicasured perfoniiancc indicates the peak cycle-to-cycle jitter is 23 ps at 700 MHz aiid a 2.8-GHz VCO freqiienc!- with a 500-mV stcp 011 the rcgulator's 3.3-V siipply)lJ. Doe to different technology. there are sonic differcnces in design considerations.

11. PLL DESIGN


I n a 0.25-11111 2poly 5iiielal digital CMOS technology.

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0-7803-7889-X/03/$17.0002003 IEEE.

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the digital supply is 2.5V, and the U supply is 3.3V. A 0 block diagram of thc clock is shown in Fig.1. All digital parts. including those in PLL. are powered using a 2.5V supply. The regulator is powered using a dedicated 3.3V supply that is shared at the boaid level by a portion of the SOC's IiO circuit blocks. The regulator filters this supply and produces a constant nominally noise-free supply of approximately 2.2V and 2.7V. These supplies are used to power the PLL's noisesensitive charge pump and voltage contnlled oscillator (VCO)[I]. A . VCODesign

work in the saturated region. Second. due to the effects of ss comcr and ff comcr. it is not fcasiblc to sct thc minimum length for each transistor in the oscillator. In ss comer, set the width of the transistor as small as possible and the highest frequency is got. Third. in condition ff. keep the length of those transistors in the oscillator and make the width wider, the lowest frequency in the ff condition is got. Fourth, regulate the dimensions of M, and M , in order to milliinize,tl;e variation in .M2 .. 8.:. .

P;' when oscillator working.


B.. Shifter Design
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The VCO, slloivn in Fig.2. consists of a tluee-stage single-ended ring oscillator that is controlled using a cumlit-numr topology[l]. For inverts: in order to maximize the noise margins and obtain symniehical characteristics. it is necessary to make the PMOS section ( k, I k,, ) times wider than the NMOS section. The inverters can be modeled as first-order RC nehvorks. In switches, the PMOS and NMOS transistors can be assumed to be in die saturation and linear regions. respectively[2]. In linear regions.

In order to detect and check a period of the oscillator. the threshold of the inverter in the shifter must be set carefully. In ss comer. when frequency reaches IGHZ the peak inay reach 1.8% wlule in ff condition, in the same frequency. the peak is only 1.3V. so the proper tlucsliold of the inverter should be 0.9V More infomation about other parts' design, Please refer to
[I].

R", =

/lemW (VG8- VTH) L


c-WL

(1)

111. VOLTAGE REGULATOR DESIGN


A block diagram of the voltage regulator is shown in Fig. 3 . A reference. generated by a bandgap generator. is used to adjust the PLL's voltage by being amplified by an operatiod amplifier. There are two amplifiers in the design. One is to regulate a 2.2V voltage for the charge pump. the shifter and the pre-slufter, and the other is to regulate a 2.7V voltage for the VCO. Mcsl and Mcs2 am transistors to provide big current for those parts, respectiwly. Ictrl and Ictrl2 are used to discharge the superfluous current so that tbe voltage of PLL is held properly. not'too high. In order to stabilize the supply voltage. Cdl and Cd2 are used[l].
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(2)

So the propagation delay is proportional to L 2 , so did the period of the oscillator. Nest are the steps to determine the dimensions of each transistor. First, after scanning parameter and the width and length of the transistors in the oscillator. different frequencies are got at different p< . w a n d L . in typical comer. This will

.M, and help to deteniune the dimemions of M , ~vluch consmct a siinple amplifier. They should
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A . Voltage Regulator Design


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First. in different comers and under different voltages. all parts.of the PLL are siioulated in order to get conditions on that PLL could work properly. Second. consider the amplifier and the regulator transistor. which c o n s e c t an amplifier system. They and the two feedback ksistok. fonn a negative feedback system. Cdl and Cd2 q e used to provide current when PLL needs big current wlule :not reducing'the voltage of PLL. Third. due t o ' a voltage feedback system.

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Fig.2 Voltage-controlled oscillator

To achieve a gain error less than 1%.

> 10000. In

tile Same tilne. for

yn = o,,(t)
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the output

response can be expressed as


R l -t b;,,,,(t)=n(l+-)(I-exp-)o(t)

Fbiutli. from above, Cdl=CdZ=jjOpf: the dc gain of the first amplifier is set to SO&: its unih-gain is set to IOOMHZ.

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GND

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Fig.3 Voltage regulator block diagram

B. Op amp design

headroom, The schematic shown in Fig.4. consists of two stages, and gain boosting is employed[l][.l]. b.3

Fig. 4 Master op amp


Each op amp is implemented using the folded-cascode order to pro\'ide the lagest possible toPolog?. bandwidth without consuming tlie excessive amount o f Fig. 5 Slave op amp with common mode feedback

In additional al~lplifier,i order to generate stabilized n feedback voltage, two torrent as cOlnlnOnlnode

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feedback iinpleincnted by hvo transistors are used. slionn in. Fig.51.i]15]. First. according to tlic different tlircshold or lransisiors in difkrent come= and the Tollage dehign kquirenients. clioose the DC operating point. Second. clioose transistors ,in nuniinnm length. check if rlie? meet tlic design requirements. Tlird. cliange the bias ciinrnt and check the design requircments. Fonli. keep llie ratio ( / L ). regulate the \\ idtli and lcngtl~ or the transistors Fifth. check if the poncr meets Ilie design requircmenls.

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IV. SIMULATION RESULTS


Simulations show each op amp's DC gain exceed 8OdB i n different camerr and its iinih gain are beyond IOOMHz. The noise rejection perfonnance of tlie voltage regulator is 5hdB in typ corner. 5ldB in ff corner and 59dB in ss corner, Jitter simulations were perfonlied with n VCO rrcquency or IC Hz and an outpnt Crequency of ZJOMHz. For the case of ideal Vregl and Vreg2. the jitter is 4 . 2 7 ~And for the case of nominally ~. quiel sopply. the jitter is 4.i24ps. When a i0O-niv step is supply. the jitter is i:!jccled onto tlie reylalor's 3 . 3 ~ 4.i72ps.

FUTURE WORK
A bandgap gcnentor is needed and the protohpe \ \ i l l be iii layout.
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REFERNECE
[ I I Joseph M. Ingino. Viiicent R. van Kaenel. "A.4-GHz Clock Syslcni for a High-Perronnance s::steni-on-a-Cldp Dcsign" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. . .NO. 11. pp. 1693-1698. X NOVEMBER 2tWl 121 Jan M. Rabacy. Digital Integrated Circuits (photocopy cdilion)_PRENTICE HALL. 1998. 1.31 Bellzad R a m i . Design or Analog CMOS Integrated Circuits. McGRAW-HALL INTERNATIONAL EDITION. 2001 j 141 K. Bult m d G. Geekn. :'A fast-settling CMOS op ainp for SC circuits with 'IO-dB DC gain." IEEE .I ,Sdid-,Yrok! c'imti!.<.vol. 25. pp. 1379-138?+ Dec. I990 151 Paul R. G+ Paul J. Hunt. Stcplien H. Lewis and I. Robcn 5. Mcfer. Analysis and Desigii of Analog Integrated Circuits. JOHN WlLEY gL SONS. INC. 2001

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