1

1. For the following ideal systems, calculate the speedup ratio S. In each case, tc is the access time of the cache memory, tm is the access time of the main store, and h is the hit ratio. a. tm = 70 ns, tc = 10 ns, b. tm = 60 ns, tc = 5 ns, (b. Ans = 120/21 = 5.1.4) 2. For the following ideal system, calculate the hit ratio h required to achieve the stated speedup ratio S. a. tm = 50 ns, tc = 10 ns, S = 2.0 h = 0.9 h = 0.9

8. Cache can be accessed in parallel or serial with main memory. In a parallel access mode both the cache and the main store are accessed simultaneously. If a hit occurs, the access to the main store is aborted. In a serial access, the cache is first examined and, if a miss occurs, the main store is accessed. Assume that the hit-ratio is h and that the ratio of cache memory access time to main store access time is k (k < 1). Derive expressions for the speedup ratio of both a parallel access cache and a serial access cache. If a serial mode cache is used and a 10% penalty in speedup ratio over the corresponding parallel access cache can be tolerated, what value of the hit ratio is necessary to achieve this? Assume that the main store access time is 150 ns and that the cache access time is 30 ns. 9. When a CPU writes to the cache, both the item in the cache and the corresponding item in the memory must be updated. If data is not in the cache, it must be fetched from memory and loaded in the cache. If tl is the time taken to reload the cache on a miss, show that the effective average access time of the memory system is given by: tave = htc + (1 - h)tm + (1 - h)tl. 10. What is cache coherency? 11. What is the meaning of the terms a. b. Temporal locality? Spatial locality?

3. Microprocessors operate in integer multiples of the clock period. The following data gives the clock cycle time of a processor, tcyc, and the access time of the main memory tm. Calculate the effective time required to access the memory. a. tcyc = 20 ns, b. tcyc = 10 ns, c. tcyc = 50 ns, tm = 75 ns tm = 75 ns tm = 110 ns

4. For any value of the hit ratio, speed-up ratio of a cache memory can be calculated using the access time of the cache and main memory. In practice, the speed-up ratio depends on clock cycle time as well as the speed of memory/cache. Assume that a system has the following parameters: Memory access (minimum) System clock Main memory wait states Cache memory wait states 4 clock cycles 64 MHz 8 0

The wait states are the additional cycles over and above cache memory access time required to access main memory. a. What is the speed-up ratio of this system? b. What hit ratio must be achieved for a speed-up ratio of 2.5. 5. For the following systems that use a clocked microprocessor, calculate the effective speedup ratio you would expect to see. Note that tcyc is the system clock time. a. tcyc = 20 ns, b. tcyc = 20 ns, tm = 75 ns, tm = 75 ns, tc = 15 ns tc = 25 ns

12. In principle, cache memory is a simple concept. You keep a copy of frequently accessed data in high-speed RAM. In practice, few elements of a computer are harder to design than cache memory. Discuss the truth of this statement. 13. What is the meaning of the terms "level 1 cache" and "level 2 cache" memories (i.e., L1 and L2 caches)? 14. Why is it harder to design a data cache than an instruction cache?

6. Draw a graph of the speedup ratio of a cache system. The yaxis is S and the x-axis is h (from 0 to 1). Construct three plots on the same x and y axes for the values k = 0.1, k = 0.2, k = 0.4. 7. A computer performs both internal operations and memory accesses. The average time to execute an instruction is tave = Finternal.tcyc + Fmemory . [h.tc + (1 - h)(tc + td)].tcyc
Finternal Fmemory tcyc tc td = fraction of time doing internal operations = fraction of time spent doing memory accesses operations = clock cycle time = cache access time in clock cycles = additional penalty paid when accessing main memory

For the following systems calculate the average cycle time a. Finternal = 20%, tcyc = 20 ns, tc= 1, td= 3, h = 0.95 b. Finternal = 50%, tcyc = 20 ns, tc= 1, td= 3, h = 0.9