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New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
Wei Zhao, Student Member, IEEE, and Yu Cao, Member, IEEE
AbstractA predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Le of as low as 13 nm. The accuracy of PTM predictions is comprehensively veried: The error of Ion is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Le , Vth , mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm. Index TermsMobility degradation, predictive modeling, process variation, saturation velocity, threshold voltage.
Fig. 1. Simple method fails to predict the overall IV characteristics.

I. INTRODUCTION HE relentless scaling of CMOS technology has accelerated in recent years and will arguably continue toward the 10-nm regime [1]. In the nanometer regime, physical factors that previously had little or no impact on circuit performance are now becoming increasingly signicant. Particular examples include process variations, transistor mobility degradation, and power consumption. These new effects pose dramatic challenges to robust circuit design and system integration. To continue the design success and make an impact on leading products, advanced circuit design exploration must begin in parallel with early silicon development. This new design paradigm demands predictive MOSFET models that are reasonably accurate, scalable with main process and design knobs, and capable of correctly capturing emerging physical effects. To predict future technology characteristics, an intuitive approach would simply scale down the geometry and voltage parameters from an existing technology. For instance, based on the current standard MOSFET model, Berkeley Short-Channel IGFET Model 4 (BSIM4) [2], we can shrink the parameters of effective gate length Le , equivalent electrical oxide thick-

Manuscript received May 3, 2006; revised August 15, 2006. This work was supported in part by the MARCO Focus Center for Circuit and System Solution and in part by the Materials, Structures, and Devices Focus Center. The review of this paper was arranged by Editor M. J. Deen. The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: wei.zhao@asu.edu). Color version of Figs. 38 are available at http://www.ieeexplore.ieee.org. Digital Object Identier 10.1109/TED.2006.884077

ness Toxe , threshold voltage Vth0 , drain and source paratactic resistance Rdsw , and supply voltage Vdd to the target values while keeping all the other parameters unchanged. However, as shown in Fig. 1, this approach is too simple to capture the basic MOSFET behavior. In Fig. 1, the IV characteristics of a preliminary 65-nm technology are predicted based on a well-characterized 130-nm technology by scaling Le , Tox , Vth0 , Rdsw , and Vdd . Compared to experimental data, this simple prediction underestimates the overall performance. This observation matches the fact that during technology scaling, process developers will optimize many other aspects of the device beyond sole geometry scaling. An improved predictive method was developed by the Berkeley Predictive Technology Model (BPTM) [3]. Compared to BSIMs, the BPTM includes more physical parameters into the prediction. Their values are empirically tted from published data of early-stage experiments. Although the BPTM provides reasonable models for technology nodes from 180 to 45 nm, its empirical nature constrains the physicality and scalability of predictions. As the model le for each technology node is independently tted, the overall trend of scaling is not smoothened by the BPTM (Fig. 2). Furthermore, intrinsic correlations among physical parameters are not sufciently considered. For instance, the scaling of Vth0 not only requires the change of channel doping Nch but also impacts other physical parameters, such as mobility 0 and saturation velocity Vsat . Insufcient modeling of these correlations limits the accuracy of prediction for process sensitivities. As process variations become increasingly signicant in 65-nm CMOS technology and below, it is critical to include these correlations into future compact models such that robust circuit design can be correctly guided [4].

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TABLE I PRIMARY PARAMETERS OF THE PTM

Fig. 2.

BPTM is not smoothly scalable from 180- to 45-nm nodes.

In this paper, a new generation of PTM is developed to overcome these limitations. First, new physical models are integrated into the predictive methodology to correctly capture the correlations among model parameters, as presented in Section II. These models include Vth0 dependence on Nch , mobility degradation, and velocity overshoot. Second, based on comprehensive studies of published data over various technology generations, i.e., from 250- to 45-nm nodes, the scaling trend of key physical parameters is concluded. By integrating these results into PTM, both nominal and variational transistor performances are predicted, following the traditional trend of scaling. As demonstrated in Section III, smooth and accurate predictions are obtained from 250- to 32-nm nodes, with Le as low as 13 nm. Compared to various published data, the error in prediction of IV characteristics is less than 10%. PTM can also be easily customized by adjusting only ten primary parameters in order to cover a wide range of process uncertainties. Based on the new PTM, the impact of process variations is further investigated for nanoscale CMOS design. Overall, this paper develops a solid predictive base for exploratory circuit design with extremely scaled CMOS. Furthermore, PTM will continue to incorporate physical models for new technology advances, such as strained silicon, high-k dielectrics, and metal gate in order to make a far-reaching impact on future design. II. NEW PREDICTIVE METHODOLOGY A. Parameter Categorization Based on our previous work on the BPTM, it is recognized that the appropriate categorization of transistor-model parameters is crucial for an efcient physical prediction [3], [6]. Although there are typically more than 100 parameters in a compact transistor model to calculate the IV and CV characteristics, only about ten of them are critical in determining the major behavior of a nanoscale transistor. The performance of a transistor is less sensitive to the rest of the secondary parameters. Based on their physical meanings, these rst-order parameters, including technology specications as well as process and physical parameters, are listed in Table I [5], [6]. Such a categorization keeps the physicality of scaling while reducing the complexity of prediction. Furthermore, this categorization is relatively independent of model formats as

Fig. 3. Trend of EOT scaling from 250- to 32-nm nodes.

those key parameters are mostly shared among different transistor models to represent the underlying silicon technology. Accurate modeling and prediction of their values are the key to the development of PTM. In this paper, BSIM4 is used as the model basis, while the predictive methodology is general enough to be applied to other model formats. A detailed approach to predict nominal model parameters is presented in Section II-B. In addition to predicting nominal values, it becomes increasingly important to capture process sensitivities as well. As process variations are vastly exacerbated at future technology nodes, the current deterministic design paradigm needs to be shifted toward a statistical design ow in order to reduce design uncertainties [1], [4]. Thus, physical correlations among main model parameters should be explicitly expressed in compact models for both accurate technology extrapolation and robust design exploration. While such a consideration is absent in the BPTM [2], [3], the new generation of PTM identies those critical correlations, particularly the interactions among Le , Vth , mobility, and saturation velocity. B. Prediction of Model Parameters As presented in Table I, the rst group of parameters is related to the process specications in technology scaling, including Vdd , Toxe , Le , Vth0 , and Rdsw . Their nominal values are determined by literature survey from published industry data, including the International Roadmap for Semiconductors (ITRS) [1]. Based on the collected data, Fig. 3 presents the trend of equivalent oxide thickness (EOT). EOT is steadily scaling down, although the pace may slow down in recent years. The trend of Vdd and Vth scaling is plotted in Fig. 4, where the value of Vth is extracted from the subthreshold IV curves. Due to the concern of subthreshold leakage, Vth almost stays the same in the nanoscale. The fth technology parameter Rdsw

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Fig. 6. Fig. 4. Trend of Vdd and Vth scaling from 250- to 32-nm nodes.

Trend of Nch scaling from 250- to 32-nm nodes.

Fig. 7. Fig. 5. Trend of Rds scaling from 250- to 32-nm nodes.

Trend of Eta0 scaling from 250- to 32-nm nodes.

is extracted by tting the IV curves in the linear region, after low-led mobility 0 is predicted [i.e., (1) and (2)]. The trend of Rdsw is shown in Fig. 5. The reduction of Rdsw becomes more difcult in short-channel devices and results in constant scaling, as shown by the data. These trends, which are supported by experimental data, are then integrated into PTM to predict the nominal values during CMOS technology scaling. Values of technology specications not only dene the basic characteristics of a process but also further determine other important electrical details of a transistor. In particular, channel doping concentration Nch is mainly dened by the threshold voltage. The exact value of Nch is reversed from published data of Vth0 in [12][28] using the Vth model in BSIM [2]. Fig. 6 illustrates the trend of Nch scaling. Based on Nch , the main coefcient K1 for the body effect of Vth is also estimated with analytical models [2]. Furthermore, to model the Vth behavior of short-channel transistors, drain-induced barrier lowering (DIBL) must be accounted for. To the rst order, this effect is captured by Eta0 , which is a model parameter for the DIBL effect. Its value is extracted from published data of the Vth rolloff [12][28]. A clear trend of Eta0 is illustrated in Fig. 7. The amount of channel doping Nch is actually important for both the threshold voltage and the transportation property in a conductive channel, i.e., the effective carrier mobility e

and the saturation velocity Vsat . For example, low eld carrier mobility degrades as Nch increases, and so does the effective carrier mobility; Vsat also depends on Nch and Le due to the phenomenon of velocity overshoot [9]. To account for these effects, the following formulas are adopted in the new PTM [9][11] to estimate Vsat and 0 , respectively: NMOS : 0 = 1150 exp(5.34 1010 PMOS : 0 = 317 exp(1.25 109 Vsat = Vsat0 + 0.13e Nch ) Nch ) (1) (2) (3)

e kT /q Vd /L2 e

Equations (1) and (2) are based on the physical model of mobility [10], [11]; the values of the coefcients are extracted from advanced silicon data [10], [11]. Equation (3) of the velocity overshoot is a simplied solution of the energybalance equation in [9]. These equations describe important dependence on Nch and are compatible with the current BSIM framework. The value of Vsat is extracted from published IV data, particularly the saturation current Ion ; its trend during scaling is plotted in Fig. 8. The effect of velocity overshoot is pronounced as technology scales down to sub-100-nm regime. Fig. 8 also demonstrates excellent model prediction by (3) with the extracted Vsat .

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for 130- to 32-nm technology generations are available. For easy access, a website is established to release the latest models (http://www.eas.asu.edu/~ptm). III. EVALUATION OF PTM A. Verication of IV Characteristics About 20 sets of published IV data from 250- to 45-nm nodes at room temperature are collected to verify the new PTM. Using the methodology previously presented, we are able to generate the corresponding PTM model les. By tuning ten primary parameters, the predicted IV characteristics are then compared to published data for verication. The parameter tuning steps are explained as follows: First, Vdd , Toxe , Le , and Vth0 are directly adjusted to the published values. Then, Nch is reversely calculated from Vth0 using analytical models [2]. Based on Nch , 0 and Vsat can be calculated with (1)(3). Finally, Rdsw is extracted from the linear region of the IV curves. Figs. 9 and 10 illustrate two examples at 45- and 65-nm nodes, respectively. The predicted IV curves are compared to the measured silicon data from [13] and [14]. Excellent agreement between predicted and published data is achieved in both sub- and superthreshold regions. More comprehensive verications are listed in Table II [12][27] [28]. Without any further model optimization, the error of Ion predictions is smaller than 10% for both n-channel MOS (NMOS) and p-channel MOS (PMOS) transistors. Such an excellent matching proves the physicality and scalability of the new PTM. Based on the successful verications, a PTM for 130- to 32-nm technology generations has been generated and released at http://www.eas.asu.edu/~ptm. Fig. 11 illustrates the trend of nominal Ion and Io . Fig. 12 illustrates the trend of nominal CV/I and switch power (CV2 ). Table III further highlights the dd major characteristics of PTM predictions in technology scaling. Note that the threshold voltage almost remains unchanged due to the leakage concern (Fig. 4). With continuous efforts, the PTM will be extended to 22-nm technology node and below. B. Impacts of Process Variations According to the ITRS [1], a similar or larger amount of process variations is expected for future technology nodes. What matters is not only the amount of variations but also the sensitivity to variations. In the nanometer regime, the sensitivity of transistor performance on process variations becomes more signicant and is critical for robust CMOS design. Particular need is observed in the phenomenon of velocity overshoot (3). Fig. 8 illustrates the trend of Vsat over technology generations. When Le is larger than 100 nm, Vsat can be treated as a constant value, e.g., about 80 000 m/s. However, as Le scales below 100 nm, Vsat can no longer be approximated as a constant. Even though mobility e decreases with technology scaling due to higher Nch , Vsat increases because of its inversely quadratic dependence on Le (1) due to velocity overshoot. As a consequence, Ion , which is somewhat proportional to Vsat , is more sensitive to variations of Le , mobility, and Vdd in the nanoscale (3). When the channel length is further reduced (e.g.,

Fig. 8. Trend of Vsat scaling from 250- to 32-nm nodes and verication of equation (3).

Combining these steps together, the ten primary parameters Vdd , Toxe , Le , Vth0 , Rdsw , Nch , Eta0 , K1 , 0 , and Vsat can be extrapolated toward future technology nodes. Furthermore, their values can be adjusted to cover a range of process uncertainties, e.g., from one companys to another ones or from intrinsic process variations. In general, the error caused by considering these primary parameters only can be reduced to 5%, as demonstrated in [6]. This is further veried by comparing the model predictions with published data, as shown in Section III. The remaining model parameters are secondary ones. There are no explicit models to predict their values. To improve the accuracy of predictions, they are further classied into two groups, depending on their importance in the determination of transistor performance. The rst group is not as critical as the primary parameters, but it also has observable impact on the IV characteristics. They are related to the determination of short-channel effects (Dvt0 and Dvt1 are short-channel-effect coefcients whose values are extracted from published data of the Vth rolloff [12][27] [28]), subthreshold behavior (Dsub , Nfactor , Vo , Cdsc , and Cdscd ), mobility (a and b ), and early voltage. During the scaling of CMOS technology, their values may change from one generation to the next but are relatively stable within one generation. In this context, their values are t from experimental data for each technology node and then xed over a range of process conditions. The remaining secondary parameters have little impact on transistor performance. Thus, for the purpose of early prediction, it is reasonable to leave these parameters unchanged from previous generations. Finally, the parameters for CV characteristics are extrapolated based on BSIM models. The new predictive methodology is rst implemented with Verilog-A since the physical models [i.e., (1)(3)] are currently not available in the standard model format. After generating the PTM for each technology node, the Verilog-A models can be mapped to the standard BSIM4 model for nominal performance prediction so that designers can directly use them with available circuit simulators. In addition, the Verilog-A format is also compatible with Simulation Program with Integrated Circuit Emphasis simulation tools, such that circuit designers can directly use them. Presently, PTM model les

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Fig. 9. Verication of PTM with [13].

Fig. 10.

Verication of PTM with [14].

beyond 22-nm node), the importance of velocity overshoot may degrade due to ballistic transportation and the source-injection limit [2]. In that case, the upper bound of velocity will be the thermal velocity [2]. The importance of velocity overshoot in the study of process variations is further illustrated in Fig. 13. Fig. 13 decomposes the variation of Ion into various physical mechanisms at the 45-nm node for the variation of Le . Without considering DIBL and velocity overshoot, Ion is relatively insensitive to Le variations as a result of pronounced velocity saturation in a nanoscale transistor. However, the Vth of a nanoscale transistor changes when there exists a variation of Le , i.e., DIBL. For example, a 20% Le variation will result in approximately 18% higher Ion due to DIBL. An additional amount of 27% Ion variation can be observed if velocity overshoot is included (Fig. 13). Therefore, it is critical to include these physical models in the prediction in order to provide correct guidance to robust design explorations. Aside from Le variation, the random uctuation of the channel doping concentration is another leading source of process variations. When Nch deviates from the target value, not only Vth0 but also K1 (i.e., the body effect), 0 (i.e., mobility), and Vsat will change accordingly. Fig. 14 shows the impact of Nch variation on Ion . Similar to Fig. 13, the sensitivity of Ion on Nch variation increases when additional physical mechanisms are included. Considering the dependence of 0 and Vsat on Nch , 12% Nch variation leads to 15% increment in Ion at the 45-nm node. These physical correlations are not

considered in the previous BPTM, which causes signicant underestimation of performance variability. The overall map of process sensitivities is shown in Fig. 15 across technology generations from 130 to 32 nm. Due to increasing process sensitivities, the variation of Ion becomes larger during technology scaling, even if the normalized process variation remains constant, e.g., 20% and 12% for Le and Nch variations, respectively (Fig. 15). For future technology generations, Le will continue to be the dominant factor that affects performance variation because of its role in velocity overshoot and the DIBL effect. Aside from that of Le variation, the impact of Nch variation also keeps increasing as technology scales. Fig. 15 shows the decomposition of the impact of Le variations during technology scaling. It reveals that velocity overshoot plays a more important role than DIBL for nanoscale MOSFET. Therefore, physical modeling of velocity overshoot is necessary in a variation-aware design. Since PTM can be easily customized by tuning Le , Toxe , Rdsw , Vth0 , Eta0 , Vdd , and other primary parameters, robust circuit design research under different conditions is fully supported. IV. CONCLUSION A new generation of PTM is developed for 130- to 32-nm technology nodes. Compared to the previous BPTM, the new predictive methodology has better physicality and scalability over a wide range of process and design conditions. Both nominal values and process sensitivity are captured in the new PTM

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TABLE II COMPREHENSIVE EVALUATION OF PTM PREDICTIONS

TABLE III SUMMARY OF THE PTM

Fig. 11. PTM nominal prediction of Ion and Io from 250- to 32-nm nodes.

2 Fig. 12. Nominal prediction of CV /I and CVdd from 250- to 32-nm nodes.

Fig. 13. Decomposition of the impact of Le variation (45-nm node).

for robust design research. Excellent predictions have been veried from 250- to 45-nm nodes. The importance of physical correlations among parameters and the impact of process variations have been evaluated. Model les for bulk CMOS with Le as low as 13 nm are available at http://www.eas.asu.edu/~ptm. These predictive model les enable early-stage circuit design

for end-of-the-roadmap technologies. In the future, the PTM will be extended to more advanced technology generations, with appropriate models for nontraditional front-end processes, such as high-k gate dielectrics and strained silicon. Feedbacks from both industrial and academic researchers will be very helpful to improve the accuracy and exibility of the PTM.

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Fig. 14. Decomposition of the impact of Nch variation (45-nm node).

Fig. 15. Impact of Le variation on Ion across technology generations.

ACKNOWLEDGMENT The authors would like to thank the BSIM group at the University of California, Berkeley, for the valuable discussions on this project. R EFERENCES
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Yu Cao (S99M02) received the B.S. degree in physics from Peking University, Beijing, China, in 1996 and the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1999 and 2002, respectively. He was a Summer Intern with Hewlett-Packard Labs, Palo Alto, CA, in 2000, and with IBM Microelectronics Division, East Fishkill, NY, in 2001. After working as a Postdoctoral Researcher at the Berkeley Wireless Research Center, he joined Arizona State University, Tempe, where he is currently an Assistant Professor of electrical engineering. He also serves as a Consultant for several electronic design automation companies. He has published numerous articles and coauthored one book on nano-CMOS physical and circuit design. His research interests include modeling and analysis of nanoscale circuits, design for lowpower and reliable circuit and system integration, modeling and integration of postsilicon technologies, and high-speed signaling techniques. Dr. Cao was a recipient of the 2006 National Science Foundation CAREER Award, the 2006 IBM Faculty Award, the 2004 Best Paper Award at the International Symposium on Quality Electronic Design, and the 2000 Beatrice Winner Award at the International Solid-State Circuits Conference. He currently serves on the technical program committee of numerous design automation and circuit design conferences.

Wei Zhao (S05) received the B.S. degree in electronics engineering from Tsinghua University, Beijing, China, in 2004. He is currently working toward the Ph.D. degree in electrical engineering at the Arizona State University, Tempe. His research interests include the modeling and design of robust circuits using nanoscale silicon.