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Verilog HDL Introduction


Textbook: VerilogHDL A guide to digital design & synthesis Second edition Author: Samir Palnitkar

VLSI System Design

Verilog HDL

HDL???

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The principal feature of a hardware description language is that it contains the capability to describe the function of a piece of hardware independently of the implementation. The great advance with modern HDLs was the recognition that a single language could be used to describe the function of the design and also to describe the implementation. This allows the entire design process to take place in a single language, and thus a single representation of the design.
VLSI System Design Verilog HDL
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Verilog HDL

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The Verilog Hardware Description Language, usually just called Verilog, was designed and first implemented by Phil Moorby at Gateway Design Automation in 1984 and 1985. It was first used beginning in 1985 and was extended substantially through 1987. The implementation was the VerilogXL simulator sold by Gateway. Present version: IEEE 1364-2001 Compliant

VLSI System Design

Verilog HDL

What is Verilog HDL?

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Verilog Hardware Description Language(HDL)?


A high-level computer language can model, represent and simulate digital design
Hardware concurrency Parallel Activity Flow Semantics for Signal Value and Time

Design examples using Verilog HDL


Intel Pentium, AMD K5, K6, Athleon, ARM7, etc Thousands of ASIC designs using Verilog HDL
VLSI System Design Verilog HDL
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Basic Design Methodology of HDLs


Requirements RTL Model Synthesize Gate-level Model ASIC or FPGA Place & Route Timing Model Simulate

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Simulate

Test Bench

Simulate
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VLSI System Design

Verilog HDL

10 Modeling Digital Systems


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Verilog HDL is for writing models of a system Reasons for modeling requirements specification documentation testing using simulation formal verification synthesis Goal most reliable design process, with minimum cost and time avoid design errors!
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Domains and Levels of Modeling


Structural Functional

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high level of abstraction

low level of abstraction

Y-chart due to Gajski & Kahn

Geometric
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Domains and Levels of Modeling


Structural Functional
Algorithm (behavioral)

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Register-Transfer Language
Boolean Equation Differential Equation

Geometric
VLSI System Design Verilog HDL

Y-chart due to Gajski & Kahn


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Domains and Levels of Modeling


Structural
Processor-Memory Switch
Register-Transfer

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Functional

Gate Transistor

Y-chart due to Gajski & Kahn

Geometric
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Domains and Levels of Modeling


Structural Functional

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Polygons Sticks Standard Cells Floor Plan

Geometric
VLSI System Design Verilog HDL

Y-chart due to Gajski & Kahn

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Hierarchy
Verilog allows you to represent the hierarchy of a design. The Verilog structures which build the hierarchy are: modules, ports. A Verilog model is composed of modules. A module is the basic unit of the model, and it may be composed of instances of other modules. A module which is composed of other module instances is called a parent module, and the instances are called child modules.

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Hierarchy contd
A more common way of depicting hierarchical relationships is: We say that a parent instantiates a child module. That is, it creates an instance of it to be a submodel of the parent. Comp_1 System instantiates comp_1, comp_2. comp_2 instantiates sub_3.

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SYSTEM

Comp_2

Sub_3

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Module
A module is defined like this:

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A module can be an element or a collection of lower-level design blocks.

module <module_name> (<module_terminal_list >); . <module internals> Verilog HDL is a case-sensitive . language. All keywords are in endmodule

lowercase
Each module must have a <module_name> which is a identifier for the module, and a <module_termininal_list>, which describes the input and output terminals of the module.

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Module contd
Signifies starting of the module
module test (out , in1,in2); . statement1; statement2; . endmodule

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Semicolon ; signifies termination of a module statement Name assigned to the module


Individual statements within the module

Signifies termination of a module

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Instances

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The process of creating objects from a module template is called instantiation, and objects are called instances. Name assigned to the instantiation Name of the output lead Names of the input leads

nand_gate ic1 (b1,a8,a7,a1);


nand_gate ic2 (b2,c8,c7,c1);

A typical instantiation of a nand gate

nand_gate is the name assigned to the module. The nand_gate can be instantiated by the designer as many times as desired. Each instantiation has to be assigned identifier name (ic1, ic2 .. ). As part of the instantiation declaration, the input and output terminals are to be defined. The convention followed is to stick to the same order as in the module declaration.

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Verilog HDL

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Instances contd
a1 The other way of instantiation is given as nand_gate ic1 (O(b), I8(a8), I7(a7), I1(a1) );

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I1

I8

nand gate module ic1

a8

Each module can be defined only once. They cannot be nested. Any module can be instantiated inside another any number of times.

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Example
// 4-bit Ripple Carry Counter module ripple_carry_counter (q, clk, reset); output [3:0] q; input clk, reset; T_FF tff0 (q[0], clk, reset); T_FF tff1 (q[1], q[0], reset); T_FF tff2 (q[2], q[1], reset); T_FF tff3 (q[3], q[2], reset); endmodule

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// Define the module T_FF. It instantiates a D_FF. module T_FF (q, clk, reset); output q; input clk, reset; wire d; D_FF dff0 (q, d, clk, reset); not n1 (d, q); // not gate is verilog primitive endmodule

// Define the module D_FF module D_FF (q1, d, clk, reset); output q1; input d, clk, reset; reg q1; always @(posedge reset or negedge clk) if (reset) q1 <= 1'b0 ; else q1 <= d; endmodule
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VLSI System Design

Verilog HDL

Levels of modelling
Switch level (Circuit level) Gate level

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Data flow Behavioral level

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Switch level

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This is lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage vdd nodes and the interconnection between them.
Example : // inverter module my_inv(out, in); output out; input in; supply1 vdd ; supply0 gnd; pmos p1(out, pwr, in); nmos n1( out, gnd, in); endmodule VLSI System Design Verilog HDL

in

out

gnd
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Gate level

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This is next level of abstraction provided by Verilog. The module is implemented in terms of logic gates and the interconnections between these gates
and a1 (A, B, C); or and (A, B, C);

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Data flow

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This is the next level of abstraction. At the data flow level, signals are assigned through the data manipulating equations. The design description are more compact than those at the gate level.

assign C = A & B;

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Behavioral level

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Behavioral level constitutes the highest level of design description. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming. The behavioral level should contain atleast a initial or always block

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Verilog HDL

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Lexical conventions
White space:
blank space (\b) tabs (\t) newline (\n)

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White space is ignored by verilog except when it separates tokens

NOTE: Tokens can be comments, delimiters ( , and ; ), numbers, strings,


identifiers and keywords. White space is not ignored in strings.

Comments: One line comment starts with //


Multiple line comment starts with /* and ends with */ Multiple line comments cant be nested.

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Number specifiations
(-)<size>`<base format><number>

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<size> : specify the size of the constant in the number of bits. (optional) 32-bit wide number by default <base format> : single character ` followed by one of the following characters b(binary), d(decimal), o(octal), h(hex) decimal by default

Examples
549 //decimal number `h 8FF //hex number `o765 // octal number 4`b11 // 4-bit binary number 0011 3`b10x // 3-bit binary number with least significant bit unknown 5`d3 // 5-bit decimal number -4`b11 // 4-bit twos complement of 0011 or 1101 this is a string // enclosed in double quotes

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Operators
3 types
Unary operators precede the operand

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Example: a = ~ b; // ~ is a unary operator, b is operand

Binary operators appear b/w two operand


Example: a = b && c ; // && is binary operator, b and c are operands

Ternary operators have two separate operators that separate 3 operators.

Example: a = b ? c : d ; // ? : ternary operators. b, c, d operands.


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Ternary example:
reg y; always @ (a or b or select) if (select) y = a; else y = b; OR y = (select) ? a : b;

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Operators(1/8)
Arithmetic operators
Treats vectors as a whole value If any operand is x, then the results are unknown
Example : ain+ din = unknown

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If results and operands are same size, then carry is lost

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Operators(2/8)
Bitwise operators
Operates on each bit of operand Result is the size of the largest operand Left-extended if sizes are different

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Operators(3/8)
Reduction operators

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Reduces vector to single bit x is considered unknown, but result maybe a known value
Example: &din results in 1`b0

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Operators(4/8)
Relational operators

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Used to compare values Returns a 1 bit scalar value of boolean true (1) / false (0) If any operand is x, then the results are unknown

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Operators(5/8)
Equality operators

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Used to compare values Returns a 1 bit scalar value of boolean true (1) / false (0) If any operand is Z or X, then the results are unknown Case equality and inequality includes x

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Operators(6/8)
Logical operators

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Returns a 1 bit scalar value of boolean true (1) / false (0) If any operand is x, then the results are unknown

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Operators(7/8)
Shift operators
Shifts a vector left or right some number of bits Zero fills Shifted bits are lost

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Operators(8/8)
Miscellaneous operators

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Operators precedence
Operators default precedence +, -, !, ~ (unary) +, - (binary) <<, >> <, >, <=, >= ==, != & ^, ^~ or ~^ | && || ?: (ternary) ( ) can be used to override default
VLSI System Design Verilog HDL Highest priority

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Lowest priority

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Data types(1/6)
4 value logical system in verilog.
ZERO

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ONE

UNKNOWN

HIGH IMPEDANCE
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Data types(2/6)
3 major data types.
Nets
Represents physcial connection between devices

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Registers
Represent abstract data storage elements

Parameters
Run-time constants

Declaration syntax
<data_type> [<MSB>:<LSB>] <list_of_identifier>

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Data types(3/6)
Nets
wire is the most common type

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Data types(4/6)
Register
reg is the most common type

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Data types(5/6)
Vectors

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wire and register can be represents by vectors


wire [7:0]temp1 reg [7:0] temp1

Arrays
<array_name> [<subscript>]
integer temp [7:0] reg [7:0] temp[31:0]

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