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module half_5(a, b, sum, c);

input a, b;
output sum, c;
wire a, b;
wire sum, c;
ADDHXL g17(.A (a), .B (b), .S (sum), .CO (c));
endmodule

module half_2(a, b, sum, c);


input a, b;
output sum, c;
wire a, b;
wire sum, c;
ADDHXL g17(.A (a), .B (b), .S (sum), .CO (c));
endmodule

module mul1(a, b, p);


input [1:0] a;
input [3:0] b;
output [5:0] p;
wire [1:0] a;
wire [3:0] b;
wire [5:0] p;
wire [9:0] w;

full c10(w[2], w[3], w[7], p[2], w[8]);


full_1 c11(w[4], w[5], w[8], p[3], w[9]);
half_5 c12(w[6], w[9], p[4], p[5]);
half_2 c9(w[0], w[1], p[1], w[7]);
AND2XL g49(.A (a[0]), .B (b[0]), .Y (p[0]));
AND2X1 g50(.A (a[0]), .B (b[1]), .Y (w[0]));
AND2X1 g51(.A (a[0]), .B (b[2]), .Y (w[2]));
AND2X1 g52(.A (a[1]), .B (b[1]), .Y (w[3]));
AND2X1 g53(.A (a[0]), .B (b[3]), .Y (w[4]));
AND2X1 g54(.A (a[1]), .B (b[0]), .Y (w[1]));
AND2X1 g55(.A (a[1]), .B (b[2]), .Y (w[5]));
AND2X1 g56(.A (a[1]), .B (b[3]), .Y (w[6]));
endmodule

rc:/> ls
./
designs/
object_types/

dex/

hdl_libraries/

libraries/

messages/

rc:/> cd /designs/
rc:/designs> ls
./

mul1/

rc:/designs> cd /designs/mul1/
rc:/designs/mul1> ls
./
dex_settings/ instances_comb/ instances_seq/
ports_out/
subdesigns/
constants/
timing/

dft/

instances_hier/ nets/

rc:/designs/mul1> report po

physical/

port_busses_out/

port_busses_in/ ports_in/

power/

ambiguous "po": port power power_domain


rc:/designs/mul1> report power
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 10:47:31 AM

Module:

mul1

Technology library:

slow_normal 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Leakage Dynamic Total


Instance Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------mul1

16 294.299 1396.399 1690.698

c11

3 72.708 337.078 409.785

c2

1 29.679 117.705 147.384

c1

1 29.015 159.782 188.797

c10

3 72.319 304.502 376.822

c1

1 29.022 167.070 196.092

c2

1 28.858 88.104 116.962

c9

1 29.099 86.060 115.159

c12

1 29.096 104.956 134.053

rc:/designs/mul1> report timing


Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'mul1'.
: Use 'report timing -lint' for more information.
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 10:52:03 AM

Module:

mul1

Technology library:

slow_normal 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Pin

Type

Fanout Load Slew Delay Arrival


(fF) (ps) (ps) (ps)

-------------------------------------------------------b[2]

in port

g51/B
g51/Y

2 2.2 0 +0
+0

AND2X1

0F

1 1.9 48 +97

97 F

c10/a
c1/a
g17/A
g17/S ADDHXL
c1/sum

+0

97

1 2.3 92 +144

240 F

c2/a
g17/B

+0

g17/CO ADDHXL

240

1 1.1 41 +102

343 F

c2/c
g2/A
g2/Y

+0
OR2XL

343

1 2.3 69 +141

483 F

c10/ca
c11/c
c2/b
g17/B

+0

g17/CO ADDHXL

483

1 1.1 42 +96

579 F

c2/c
g2/A
g2/Y

+0
OR2XL

579

1 2.3 69 +141

720 F

c11/ca
c12/b
g17/B
g17/CO

+0
ADDHXL

720

1 0.0 27 +84

c12/c
p[5]

out port

+0

804 F

-------------------------------------------------------Timing slack : UNCONSTRAINED


Start-point : b[2]
End-point : p[5]

804 F

rc:/designs/mul1> report timing -lint


============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 10:52:24 AM

Module:

mul1

Technology library:

slow_normal 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

------------------------------------------------------------------------------The following primary inputs have no clocked external delays. As a result the
timing paths leading from the ports have no timing constraints derived from
clock waveforms. The'external_delay' command is used to create new external
delays.

/designs/mul1/ports_in/a[0]
/designs/mul1/ports_in/a[1]
/designs/mul1/ports_in/b[0]
... 3 other warnings in this category.
Use the -verbose option for more details.
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

The following primary outputs have no clocked external delays. As a result the
timing paths leading to the ports have no timing constraints derived from clock
waveforms. The'external_delay' command is used to create new external delays.

/designs/mul1/ports_out/p[0]
/designs/mul1/ports_out/p[1]
/designs/mul1/ports_out/p[2]
... 3 other warnings in this category.
Use the -verbose option for more details.
-------------------------------------------------------------------------------

rc:/designs/mul1> report area


============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 10:53:39 AM

Module:

mul1

Technology library:

slow_normal 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Instance Cells Cell Area Net Area Wireload


----------------------------------------------------

mul1

16

99

<none> (D)

c11

25

<none> (D)

c2

11

<none> (D)

c1

11

<none> (D)

c10

25

<none> (D)

c2

11

<none> (D)

c1

11

<none> (D)

c9

11

<none> (D)

c12

11

<none> (D)

(D) = wireload is default in technology library


rc:/designs/mul1> report gates
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 10:54:00 AM

Module:

mul1

Technology library:

slow_normal 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Gate Instances Area

Library

-----------------------------------------

ADDHXL

6 63.504 slow_normal

AND2X1

7 24.696 slow_normal

AND2XL

1 3.528 slow_normal

OR2XL

2 7.056 slow_normal

----------------------------------------total

16 98.784

Type Instances Area Area %


-----------------------------logic

16 98.784 100.0

-----------------------------total

16 98.784 100.0

rc:/designs/mul1> set_attribute library


/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.
lib
Error : Failed to parse attribute string. [TUI-23] [set_attribute]
: Unable to convert the string
'/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt
.lib' to type 'library domain' for the attribute 'library_domain'.
: To see the usage/description for this attribute, type 'set_attribute -h <attr_name> *'.
Failed on set_attribute library
/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.
lib
rc:/designs/mul1> cd ..
rc:/designs> cd ..

rc:/> set_attribute library


/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.
lib
Freeing libraries in memory
(/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_norm
al.lib)

Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]


: Cannot resolve reference to 'OR2XL'.
: To resolve the reference, either load a technology library containing the cell by appending to the
'library' attribute, or read in the hdl file containing the module before performing elaboration. As the
design is incomplete, synthesis results may not correspond to the entire design.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'ADDHXL'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'AND2XL'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'AND2X1'.
Setting attribute of root '/': 'library' =
/home/vlsi07/Database_Cadence/Database/Cadence_digital_labs/Workarea/rclabs/library/slow_highvt.
lib
rc:/> cd /designs/
rc:/designs> ls
./

mul1/

rc:/designs> remove_design /designs/mul1/


invalid command name "remove_design"
rc:/designs> remove /designs/mul1/
ambiguous command name "remove": remove_assigns_without_optimization
remove_cdn_loop_breaker remove_inserted_sync_enable_logic

rc:/designs> remove -design /designs/mul1/


ambiguous command name "remove": remove_assigns_without_optimization
remove_cdn_loop_breaker remove_inserted_sync_enable_logic
rc:/designs> read_hdl mul1.v
rc:/designs> cd ..
rc:/> read_hdl mul1.v
module mul1(a,b,p);
|
Warning : Replacing previously read Verilog description. [VLOGPT-6]
: Replacing Verilog description 'mul1' with Verilog module in file 'mul1.v' on line 1, column 11.
: A Verilog description is replaced when a new description of the same name and same library is
read again.
Verilog descriptions are:
module
macromodule
SystemVerilog adds the following descriptions:
interface
program
package.
module full(a,b,c,sum,ca);
|
Warning : Replacing previously read Verilog description. [VLOGPT-6]
: Replacing Verilog description 'full' with Verilog module in file 'mul1.v' on line 20, column 11.
module half(a,b,sum,c);
|
Warning : Replacing previously read Verilog description. [VLOGPT-6]

: Replacing Verilog description 'half' with Verilog module in file 'mul1.v' on line 34, column 11.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'mul1' in library 'default' with newly read Verilog module 'mul1' in the
same library in file 'mul1.v' on line 1.
: A newly read VHDL entity replaces any previously read Verilog module or VHDL entity in the same
library if its name matches (case-insensitively) the existing module or entity.
For instance:
VHDL 'foo'

replaces VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library

VHDL 'foo' (in any library) replaces Verilog {'FOO' or 'foo' or 'Foo' or ...} in the same library

A newly read Verilog module replaces any previously read Verilog module if its name matches (casesensitively) that module. Further, it replaces any previously read VHDL entity in the same library if its
name matches (case -insensitively) that entity.
For instance:
Verilog 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
Verilog 'foo' replaces Verilog 'foo' only
In addition:
Verilog 'foo' does not replace Verilog 'FOO' and the two remain as distinct modules.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'full' in library 'default' with newly read Verilog module 'full' in the same
library in file 'mul1.v' on line 20.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'half' in library 'default' with newly read Verilog module 'half' in the
same library in file 'mul1.v' on line 34.
rc:/> remove /designs/mul1/
ambiguous command name "remove": remove_assigns_without_optimization
remove_cdn_loop_breaker remove_inserted_sync_enable_logic
rc:/> remove_design /designs/mul1/

invalid command name "remove_design"


rc:/> elaborate
Elaborating top-level block 'mul1' from file 'mul1.v'.
Done elaborating 'mul1'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'OR2XL'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'ADDHXL'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'AND2XL'.
Warning : Black-boxes are represented as unresolved references in the design. [TUI-273]
: Cannot resolve reference to 'AND2X1'.
rc:/> synthesize -to_mapped
Mapping mul1_1 to gates.

Global mapping target info


==========================
Cost Group 'default' target slack: Unconstrained

Global mapping status


=====================
Worst
Total Neg
Operation

Area Slack Worst Path

------------------------------------------------------------------------------global_map

99

0 N/A

Global incremental target info


==============================
Cost Group 'default' target slack: Unconstrained

Global incremental optimization status


======================================
Worst
Total Neg
Operation

Area Slack Worst Path

------------------------------------------------------------------------------global_inc

99

0 N/A

Worst - - DRC Totals - Total Neg


Operation

Max

Area Slack

Max
Trans

Cap

------------------------------------------------------------------------------init_iopt

99

Incremental optimization status


===============================
Worst - - DRC Totals - Total Neg

Max

Max

Operation

Area Slack

Trans

Cap

------------------------------------------------------------------------------init_delay

99

init_drc

99

init_area

99

Incremental optimization status


===============================
Worst - - DRC Totals - Total Neg
Operation

Max

Area Slack

Max
Trans

Cap

------------------------------------------------------------------------------init_delay

99

init_drc

99

init_area

99

Done mapping mul1_1


Mapping mul1 to gates.

Global mapping target info


==========================
Cost Group 'default' target slack: Unconstrained

Global mapping status

=====================
Worst
Total Neg
Operation

Area Slack Worst Path

------------------------------------------------------------------------------global_map

0 N/A

Global incremental target info


==============================
Cost Group 'default' target slack: Unconstrained

Global incremental optimization status


======================================
Worst
Total Neg
Operation

Area Slack Worst Path

------------------------------------------------------------------------------global_inc

0 N/A

Worst - - DRC Totals - Total Neg


Operation

Max

Area Slack

Max
Trans

Cap

------------------------------------------------------------------------------init_iopt

Incremental optimization status


===============================
Worst - - DRC Totals - Total Neg
Operation

Max

Area Slack

Max
Trans

Cap

------------------------------------------------------------------------------init_delay

init_drc

init_area

Incremental optimization status


===============================
Worst - - DRC Totals - Total Neg
Operation

Max

Area Slack

Max
Trans

Cap

------------------------------------------------------------------------------init_delay

init_drc

init_area

Done mapping mul1


Synthesis succeeded.
rc:/> report power
Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [report]
: There is no unique design here.

: Specify a design by using the cd command to change to that design's directory or specify the
design as an argument for the command.
Failed on find_unique_design
rc:/> ls
./
designs/
object_types/

dex/

hdl_libraries/

libraries/

messages/

rc:/> cd /de
ambiguous "/de": designs/ dex/
rc:/> cd /designs/
rc:/designs> ls
./

mul1/

mul1_1/

rc:/designs> cd mul1
rc:/designs/mul1> report power
Warning : Did not find power models for RTL power analysis. [PA-17]
: Design /designs/mul1 has no power models available.
: The RTL power analysis results are more accurate when detailed power models are used. Use
command 'build_rtl_power_models' to build detailed power models.
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:16:33 AM

Module:

mul1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Leakage Dynamic Total


Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------mul1

0.000

0.000

0.000

c10

0.000

0.000

0.000

c1

0.000

0.000

0.000

g17
c2
g17

0
0

0.000
0.000

0.000
0.000

0.000
0.000

0.000

0.000

0.000

g2

0.000

0.000

0.000

c11

0.000

0.000

0.000

c1

0.000

0.000

0.000

g17
c2
g17

0
0

0.000
0.000

0.000
0.000

0.000
0.000

0.000

0.000

0.000

g2

0.000

0.000

0.000

c12

0.000

0.000

0.000

0.000

0.000

0.000

g17
c9
g17

0.000

0.000

0.000

0.000

0.000

0.000

g49

0.000

0.000

0.000

g50

0.000

0.000

0.000

g51

0.000

0.000

0.000

g52

0.000

0.000

0.000

g53

0.000

0.000

0.000

g54

0.000

0.000

0.000

g55

0.000

0.000

0.000

g56

0.000

0.000

0.000

rc:/designs/mul1> cd ..
rc:/designs> mult1_1
invalid command name "mult1_1"
rc:/designs> ls
./

mul1/

mul1_1/

rc:/designs> cd /designs/mul1_1/
rc:/designs/mul1_1> report power
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:17:48 AM

Module:

mul1_1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Leakage Dynamic Total


Instance Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------mul1_1

16 73.975 1375.948 1449.922

c11

3 18.150 331.300 349.450

c2

7.409 115.098 122.507

c1

7.272 156.936 164.207

c10

3 18.144 299.757 317.900

c1

7.293 165.989 173.282

c2

7.283 84.772 92.055

c12

7.321 104.047 111.368

c9

7.317 85.181 92.498

rc:/designs/mul1_1>

rc:/designs/mul1_1> report power


============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:17:48 AM

Module:

mul1_1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Leakage Dynamic Total


Instance Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------mul1_1
c11

16 73.975 1375.948 1449.922


3 18.150 331.300 349.450

c2

7.409 115.098 122.507

c1

7.272 156.936 164.207

c10
c1

3 18.144 299.757 317.900


1

7.293 165.989 173.282

c2

7.283 84.772 92.055

c12

7.321 104.047 111.368

c9

7.317 85.181 92.498

rc:/designs/mul1_1> report timing


Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'mul1_1'.
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:23:44 AM

Module:

mul1_1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Pin

Type

Fanout Load Slew Delay Arrival


(fF) (ps) (ps) (ps)

-------------------------------------------------------b[2]

in port

2 2.2 0 +0

g51/B
g51/Y
c10/a
c1/a

+0
AND2X1TH

0F

1 1.8 56 +122

122 F

g17/A

+0

g17/S ADDHXLTH

122

1 2.3 114 +187

309 F

c1/sum
c2/a
g17/B

+0

309

g17/CO ADDHXLTH

1 1.0 48 +132

441 F

c2/c
g2/A
g2/Y

+0
OR2XLTH

441

1 2.3 84 +184

624 F

c10/ca
c11/c
c2/b
g17/B

+0

624

g17/CO ADDHXLTH

1 1.0 48 +122

746 F

c2/c
g2/A
g2/Y

+0
OR2XLTH

746

1 2.3 84 +184

930 F

c11/ca
c12/b
g17/B
g17/CO

+0
ADDHXLTH

930

1 0.0 32 +108 1039 F

c12/c
p[5]

out port

+0 1039 F

-------------------------------------------------------Timing slack : UNCONSTRAINED

Start-point : b[2]
End-point : p[5]

rc:/designs/mul1_1> report area


============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:24:49 AM

Module:

mul1_1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Instance Cells Cell Area Net Area Wireload


---------------------------------------------------mul1_1

16

99

<none> (D)

c11

25

<none> (D)

c2

11

<none> (D)

c1

11

<none> (D)

c10

25

<none> (D)

c2

11

<none> (D)

c1

11

<none> (D)

c9

11

<none> (D)

c12

11

<none> (D)

(D) = wireload is default in technology library


rc:/designs/mul1_1> report gates
============================================================
Generated by:

Encounter(R) RTL Compiler v09.10-s106_2

Generated on:

Oct 13 2011 11:25:43 AM

Module:

mul1_1

Technology library:

slow_highvt 1.0

Operating conditions: slow (balanced_tree)


Wireload mode:
Area mode:

enclosed
timing library

============================================================

Gate Instances Area

Library

------------------------------------------ADDHXLTH

6 63.504 slow_highvt

AND2X1TH

7 24.696 slow_highvt

AND2XLTH

1 3.528 slow_highvt

OR2XLTH

2 7.056 slow_highvt

------------------------------------------total

16 98.784

Type Instances Area Area %


-----------------------------logic

16 98.784 100.0

-----------------------------total

16 98.784 100.0

rc:/designs/mul1_1>