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input a, b;
output sum, c;
wire a, b;
wire sum, c;
ADDHXL g17(.A (a), .B (b), .S (sum), .CO (c));
endmodule
rc:/> ls
./
designs/
object_types/
dex/
hdl_libraries/
libraries/
messages/
rc:/> cd /designs/
rc:/designs> ls
./
mul1/
rc:/designs> cd /designs/mul1/
rc:/designs/mul1> ls
./
dex_settings/ instances_comb/ instances_seq/
ports_out/
subdesigns/
constants/
timing/
dft/
instances_hier/ nets/
rc:/designs/mul1> report po
physical/
port_busses_out/
port_busses_in/ ports_in/
power/
Generated on:
Module:
mul1
Technology library:
slow_normal 1.0
enclosed
timing library
============================================================
c11
c2
c1
c10
c1
c2
c9
c12
Generated on:
Module:
mul1
Technology library:
slow_normal 1.0
enclosed
timing library
============================================================
Pin
Type
-------------------------------------------------------b[2]
in port
g51/B
g51/Y
2 2.2 0 +0
+0
AND2X1
0F
1 1.9 48 +97
97 F
c10/a
c1/a
g17/A
g17/S ADDHXL
c1/sum
+0
97
1 2.3 92 +144
240 F
c2/a
g17/B
+0
g17/CO ADDHXL
240
1 1.1 41 +102
343 F
c2/c
g2/A
g2/Y
+0
OR2XL
343
1 2.3 69 +141
483 F
c10/ca
c11/c
c2/b
g17/B
+0
g17/CO ADDHXL
483
1 1.1 42 +96
579 F
c2/c
g2/A
g2/Y
+0
OR2XL
579
1 2.3 69 +141
720 F
c11/ca
c12/b
g17/B
g17/CO
+0
ADDHXL
720
1 0.0 27 +84
c12/c
p[5]
out port
+0
804 F
804 F
Generated on:
Module:
mul1
Technology library:
slow_normal 1.0
enclosed
timing library
============================================================
------------------------------------------------------------------------------The following primary inputs have no clocked external delays. As a result the
timing paths leading from the ports have no timing constraints derived from
clock waveforms. The'external_delay' command is used to create new external
delays.
/designs/mul1/ports_in/a[0]
/designs/mul1/ports_in/a[1]
/designs/mul1/ports_in/b[0]
... 3 other warnings in this category.
Use the -verbose option for more details.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
The following primary outputs have no clocked external delays. As a result the
timing paths leading to the ports have no timing constraints derived from clock
waveforms. The'external_delay' command is used to create new external delays.
/designs/mul1/ports_out/p[0]
/designs/mul1/ports_out/p[1]
/designs/mul1/ports_out/p[2]
... 3 other warnings in this category.
Use the -verbose option for more details.
-------------------------------------------------------------------------------
Generated on:
Module:
mul1
Technology library:
slow_normal 1.0
enclosed
timing library
============================================================
mul1
16
99
<none> (D)
c11
25
<none> (D)
c2
11
<none> (D)
c1
11
<none> (D)
c10
25
<none> (D)
c2
11
<none> (D)
c1
11
<none> (D)
c9
11
<none> (D)
c12
11
<none> (D)
Generated on:
Module:
mul1
Technology library:
slow_normal 1.0
enclosed
timing library
============================================================
Library
-----------------------------------------
ADDHXL
6 63.504 slow_normal
AND2X1
7 24.696 slow_normal
AND2XL
1 3.528 slow_normal
OR2XL
2 7.056 slow_normal
----------------------------------------total
16 98.784
16 98.784 100.0
-----------------------------total
16 98.784 100.0
mul1/
: Replacing Verilog description 'half' with Verilog module in file 'mul1.v' on line 34, column 11.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'mul1' in library 'default' with newly read Verilog module 'mul1' in the
same library in file 'mul1.v' on line 1.
: A newly read VHDL entity replaces any previously read Verilog module or VHDL entity in the same
library if its name matches (case-insensitively) the existing module or entity.
For instance:
VHDL 'foo'
VHDL 'foo' (in any library) replaces Verilog {'FOO' or 'foo' or 'Foo' or ...} in the same library
A newly read Verilog module replaces any previously read Verilog module if its name matches (casesensitively) that module. Further, it replaces any previously read VHDL entity in the same library if its
name matches (case -insensitively) that entity.
For instance:
Verilog 'foo' replaces VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
Verilog 'foo' replaces Verilog 'foo' only
In addition:
Verilog 'foo' does not replace Verilog 'FOO' and the two remain as distinct modules.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'full' in library 'default' with newly read Verilog module 'full' in the same
library in file 'mul1.v' on line 20.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
: Replacing Verilog module 'half' in library 'default' with newly read Verilog module 'half' in the
same library in file 'mul1.v' on line 34.
rc:/> remove /designs/mul1/
ambiguous command name "remove": remove_assigns_without_optimization
remove_cdn_loop_breaker remove_inserted_sync_enable_logic
rc:/> remove_design /designs/mul1/
------------------------------------------------------------------------------global_map
99
0 N/A
------------------------------------------------------------------------------global_inc
99
0 N/A
Max
Area Slack
Max
Trans
Cap
------------------------------------------------------------------------------init_iopt
99
Max
Max
Operation
Area Slack
Trans
Cap
------------------------------------------------------------------------------init_delay
99
init_drc
99
init_area
99
Max
Area Slack
Max
Trans
Cap
------------------------------------------------------------------------------init_delay
99
init_drc
99
init_area
99
=====================
Worst
Total Neg
Operation
------------------------------------------------------------------------------global_map
0 N/A
------------------------------------------------------------------------------global_inc
0 N/A
Max
Area Slack
Max
Trans
Cap
------------------------------------------------------------------------------init_iopt
Max
Area Slack
Max
Trans
Cap
------------------------------------------------------------------------------init_delay
init_drc
init_area
Max
Area Slack
Max
Trans
Cap
------------------------------------------------------------------------------init_delay
init_drc
init_area
: Specify a design by using the cd command to change to that design's directory or specify the
design as an argument for the command.
Failed on find_unique_design
rc:/> ls
./
designs/
object_types/
dex/
hdl_libraries/
libraries/
messages/
rc:/> cd /de
ambiguous "/de": designs/ dex/
rc:/> cd /designs/
rc:/designs> ls
./
mul1/
mul1_1/
rc:/designs> cd mul1
rc:/designs/mul1> report power
Warning : Did not find power models for RTL power analysis. [PA-17]
: Design /designs/mul1 has no power models available.
: The RTL power analysis results are more accurate when detailed power models are used. Use
command 'build_rtl_power_models' to build detailed power models.
============================================================
Generated by:
Generated on:
Module:
mul1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
0.000
0.000
0.000
c10
0.000
0.000
0.000
c1
0.000
0.000
0.000
g17
c2
g17
0
0
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
g2
0.000
0.000
0.000
c11
0.000
0.000
0.000
c1
0.000
0.000
0.000
g17
c2
g17
0
0
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
g2
0.000
0.000
0.000
c12
0.000
0.000
0.000
0.000
0.000
0.000
g17
c9
g17
0.000
0.000
0.000
0.000
0.000
0.000
g49
0.000
0.000
0.000
g50
0.000
0.000
0.000
g51
0.000
0.000
0.000
g52
0.000
0.000
0.000
g53
0.000
0.000
0.000
g54
0.000
0.000
0.000
g55
0.000
0.000
0.000
g56
0.000
0.000
0.000
rc:/designs/mul1> cd ..
rc:/designs> mult1_1
invalid command name "mult1_1"
rc:/designs> ls
./
mul1/
mul1_1/
rc:/designs> cd /designs/mul1_1/
rc:/designs/mul1_1> report power
============================================================
Generated by:
Generated on:
Module:
mul1_1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
c11
c2
c1
c10
c1
c2
c12
c9
rc:/designs/mul1_1>
Generated on:
Module:
mul1_1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
c2
c1
c10
c1
c2
c12
c9
Generated on:
Module:
mul1_1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
Pin
Type
-------------------------------------------------------b[2]
in port
2 2.2 0 +0
g51/B
g51/Y
c10/a
c1/a
+0
AND2X1TH
0F
1 1.8 56 +122
122 F
g17/A
+0
g17/S ADDHXLTH
122
309 F
c1/sum
c2/a
g17/B
+0
309
g17/CO ADDHXLTH
1 1.0 48 +132
441 F
c2/c
g2/A
g2/Y
+0
OR2XLTH
441
1 2.3 84 +184
624 F
c10/ca
c11/c
c2/b
g17/B
+0
624
g17/CO ADDHXLTH
1 1.0 48 +122
746 F
c2/c
g2/A
g2/Y
+0
OR2XLTH
746
1 2.3 84 +184
930 F
c11/ca
c12/b
g17/B
g17/CO
+0
ADDHXLTH
930
c12/c
p[5]
out port
+0 1039 F
Start-point : b[2]
End-point : p[5]
Generated on:
Module:
mul1_1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
16
99
<none> (D)
c11
25
<none> (D)
c2
11
<none> (D)
c1
11
<none> (D)
c10
25
<none> (D)
c2
11
<none> (D)
c1
11
<none> (D)
c9
11
<none> (D)
c12
11
<none> (D)
Generated on:
Module:
mul1_1
Technology library:
slow_highvt 1.0
enclosed
timing library
============================================================
Library
------------------------------------------ADDHXLTH
6 63.504 slow_highvt
AND2X1TH
7 24.696 slow_highvt
AND2XLTH
1 3.528 slow_highvt
OR2XLTH
2 7.056 slow_highvt
------------------------------------------total
16 98.784
16 98.784 100.0
-----------------------------total
16 98.784 100.0
rc:/designs/mul1_1>