VLSI Design Lecture 2: Basic Fabrication Steps and Layout

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology

Adapted with modifications from lecture notes prepared by author (from Prentice Hall PTR)

Topics
Basic fabrication steps. Transistor structures. Basic transistor behavior. Latch up.

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Fabrication services
Educational services:
U.S.: MOSIS EC: EuroPractice Taiwan: CIC Japan: VDEC

Foundry = fabrication line for hire.

Foundries are major source of fab capacity today.

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Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si

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Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic, Phosphorus): extra electron (n-type) Group III (Boron): missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si
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+ -

As Si

Si

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p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

N-Diff

P-Diff

cathode
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anode
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Modern VLSI Design 3e: Chapter 2

Fabrication processes
IC built on silicon substrate:
some structures diffused into substrate; other structures built on top of substrate.

Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO2) is insulator.

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Simple cross section

SiO2 metal3 metal2 transistor poly n+ p+ n+ substrate substrate
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metal1

via

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Photolithography
Mask patterns are put on wafer using photo-sensitive material:

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Process steps
First place tubs to provide properly-doped substrate for n-type, p-type transistors:
p-tub substrate n-tub

Pattern polysilicon before diffusion regions:

poly p-tub gate oxide poly n-tub

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Process steps, contd

Add diffusions, performing self-masking:

poly n+ p-tub n+ p+

poly n-tub p+

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Process steps, contd

Start adding metal layers:

metal 1 poly n+ p-tub n+ vias p+

metal 1 poly n-tub p+

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Transistor structure
n-type transistor:

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0.25 micron transistor (Bell Labs)

gate oxide silicide source/drain poly

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Transistor layout
n-type (tubs may vary):

L w

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NMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor
Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Source Gate Drain Even though gate is Polysilicon no longer made of metal SiO2
n+ p n+ bulk Si

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NMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage:
P type body is at low voltage Source b and drain body diodes are OFF - ody No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2 0 n+ p n+ S bulk Si D

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NMOS Operation (contd.)

When the gate is at a high voltage:
Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to - type n Now current can flow through - type silicon from source n through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D

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PMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain

p+ n

p+ bulk Si

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Drain current characteristics

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Drain current
Linear region (Vds < Vgs - Vt):
Id = k (W/L)[(Vgs- Vt)Vds- 0.5 Vds2]

Saturation region (Vds Vgs - Vt):

Id = 0.5k (W/L)(Vgs- Vt) 2

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0.5 m transconductances
From a MOSIS process: n-type:
kn = 73 A/V2 Vtn = 0.7 V

p-type:
kp = 21 A/V2 Vtp = - 0 V .8

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Current through a transistor

Use 0.5 m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions: Vgs = 2V:
Id = 0.5k(W/L)(Vgs V2= 93 A - t)

Vgs = 5V:
Id = 1 mA

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Basic transistor parasitics

Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.

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Basic transistor parasitics, contd

Gate capacitance Cg. Determined by active area. Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.
Cgs = Col W

Gate/bulk overlap capacitance.

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Latch-up
CMOS ICs have parastic silicon-controlled rectifiers (SCRs). When powered up, SCRs can turn on, creating lowresistance path from power to ground. Current can destroy chip. Early CMOS problem. Can be solved with proper circuit/layout structures.

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Parasitic SCR structure

There exist parasitic bipolar transistors (pnp and npn) in a CMOS structure. Additionally, the well and substrate have resistances RW and RS, respectively. Twin tub n tub
Rwell Vwell
A GND Y VDD

p+

n+

n+ p substrate Vsub

p+ n well Vwell

p+

n+ Rwell

Vsub

Rsub

Rsub substrate tap

well tap

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Parasitic SCR

circuit
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- Vbehavior I
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Solution to latch-up
Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

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Tub tie layout

p+ metal (VDD) p tub

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