12th NXP ElectroStatic Discharge And Latch-Up Symposium

Golden Tulip Parkhotel, Doorwerth (NL) April 7 and 8, 2008

nww.nxp.com/it/cto/services/technology-exploration/esd

Introduction
This is the preliminary program of the 12th NXP ESD/LU symposium. This years symposium will be held in Golden Tulip Hotel parkhotel Doorwerth. This booklet contains the full schedule of the symposium. For almost all papers a short abstract is included. The schedule is divided in 30-minute slots. Since we want to encourage interaction with the audience, papers are scheduled to last 20 minutes with additionally 10 minutes for clarification and discussion. There will be an evening program and dinner. This is an excellent opportunity to continue your discussions or extend the informal contacts with your colleagues. If you registered for the symposium, the overnight stay of April 7 has been reserved unless you indicated that you do not want to stay in the hotel. It is possible to reserve extra nights before or after the symposium. CorpI&T/PLT/DL will pay part of the costs of the symposium (conference rooms, drinks, dinner, etc.). Participants with an overnight stay pay 200 Participants without an overnight stay pay 75 Additional nights cost 95 Please settle your bill before leaving the hotel. Location: Golden Tulip Parkhotel Doorwerth Kabeljauwallee 35 6865 BL DOORWERTH (NL) Tel: +31 (0) 317 319 010 Fax: +31 (0) 317 314 546 For more details, please visit http://nww.nxp.com/it/cto/services/technology-exploration/esd Guidelines for presenters 1) The symposium will consist of 30-minute time slots. This time slot includes discussion. Therefore all presenters are requested to schedule a 20-minute presentation. This leaves enough time for questions, either during or after the presentation. 2) A powerpoint template will be sent to you shortly. Please use this template for your presentation! 3) A beamer and laptop will be available. It is preferred that you send your Powerpoint presentation file to Theo Smedes 1 week before the symposium. Alternatively bring a CD, memory stick or your own laptop. A standard overhead projector and flip-overs are also available. 4) We would like to have all presentation sheets available in order to collect them in the proceedings of the symposium. Therefore, if you have not sent the presentations before the symposium, please do so within 1 week after the symposium or give an electronic copy to Theo Smedes during the symposium.

Schedule
Time Monday, 07-04-2008 08:30-09:00 09:00-09:30 09:30-10:00 10:00-10:30 10:30-11:00 11:00-11:30 11:30-12:00 12:00-13:30 13:30-13:45 13:45-14:00 14:00-14:30 14:30-15:00 15:00-15:30 15:30-16:00 16:00-16:30 16:30-17:00 17:00-17:30 17:30-17:45 17:45-18:00 18:00-18:15 18:15-19:15 20:30 Tuesday, 08-04-2008 08:30-09:00 09:00-09:30 09:30-10:00 10:00-10:30 10:30-11:00 11:00-11:30 11:30-11:45 11:45-13:00 13:00-13:30 13:30-14:00 14:00-14:15 14:15-14:45 14:45-15:15 15:15-15:30 15:30-16:00 16:00-16:30 17:00 F1 F2 F3 break G1 G2 G3 break H1 H2 break I1 I2 break J1 J2 EOS On the Relevance of IC ESD Performance to Product Quality On the screening of potential EOS/ESD fails at WT/FT EOS-TME status and EOS project Smedes Christoforou Lefebvre Nijmegen Nijmegen Caen A0 A1 A2 break B1 B2 B3 break C1 C2 C3 C4 break D1 D2 break E1 E2a E2b E2c E3 Qubic Welcome ESD in the QUBiC4 Family, a Very Busy Year 5V-capable ESD protection in QUBiC4plus: back to the basis CMOS Gate oxide protection in CLN65 ESD Protection Strategies for CLN65 and CLN45 I/O Libraries RF IOs status for advanced RFCMOS System level Concepts for effective ESD devices System level ESD protection for HDMI in CMOS14 Development of IEC 61000-4-2 ESD at Chip Level Discussion ABCD ESD review of TJA1042 and TJA1051 Of the grounded gate nmost Tools Working with PERD ESD Verification Methods PLT ESD Checktools Top level circuit simulation as an ESD verification method ESD Tools Roadmap discussion Dinner Smedes Colclaser Maksimovic Nijmegen Albuquerque Zurich Number Title Presenter

Notermans de Jong Barbier

Zurich Nijmegen Caen

Pan Smedes Mohlman Velghe

Hamburg Nijmegen Tempe Nijmegen

Velghe de Raad

Nijmegen Nijmegen

Scheucher Trivedi Fleurimont Zwol Fleurimont

Gratkorn Southampton Nijmegen Nijmegen Nijmegen

CMOS Realizing both ESD- and functional robustness in a CMOS18S D Looijmans Low level HBM and CDM failures in a CMOS090 product Ward Georgia's HTOL re-qualification fails Elsner LU A case study of Latch-Up problems Latch-up risk in negative-bias circuitry Devices ESD simulations of discrete bipolar diodes and transistors Investigation of TLP discharges in RF-MEMS devices Testers New ESD-CDM calibration issues ESD Test Artifacts Closure

Nijmegen Southampton Dresden

Wu Zwol

Nijmegen Nijmegen

Holland de Cock

Hamburg Nijmegen

Polewski Arjona-Gomez

Nijmegen Nijmegen

Abstracts A0. Welcome - Theo Smedes. This presentation will cover some guidelines for the symposium and some highlights of the ESD community. A1. ESD in the QUBiC4 Family, a Very Busy Year - Roy Colclaser, Frederic Barbier There have been a number of significant problems with ESD in the QUBiC4 family in 2007/2008. Some of the problems have been associated with power supply voltages that have been gradually increasing with each new design. We are working on the first QUBiC4plus MEMs project which has +/-20V swings on a process designed for 2.5V DC. We also have an interesting problem associated with the effect of diodes in series to the power supply on the product performance after MM stress. A2. 5V-capable ESD protection in QUBiC4plus: back to the basics - Dejan Maksimovic, Guido Notermans, Roy Colclaser In LeafDice design the HTOL test discovered the reliability problem with the ggNMOST protecting the 5V-tolerant IIC pads. This led to the experiments with 5V-capable devices: ggNMOSTs with NLDDPROT, stacked ggNMOSTs and field-oxide NMOSTs. We present the TLP and DC characterization data of these experimental devices. B1. Gate oxide protection in CLN65 - Guido Notermans, Theo Smedes, eljko Mrarica, Peter de Jong, Ralph Stephan, Hans van Zwol, Dejan Maksimovic Results from electrical (TLP, MM) measurements, extensive failure analysis, and device simulations show that in a 65 nm technology the gate of a MOS transistor is not guaranteed to be protected effectively by the drain junction of another NMOS transistor connected to it, e.g. a grounded-gate NMOST. B2. ESD Protection Strategies for CLN65 and CLN45 I/O Libraries - Peter C. de Jong, Nicolas Guitard In this presentation the protection strategies used in the I/O libraries for CLN65 and CLN45 are compared and differences highlighted. Also some remarkable characterization results of test structures, related to the use of silicide blocking, will be shown. Finally, the library evaluation status and plans will be discussed. B3. RF IOs status for advanced RFCMOS - Eric Thomas, Frederic Barbier NXP is moving to advanced CMOS technologies for the future RF products. Some RF Inputs and Outputs are under development to be able to withstand both the constraints of RF systems and to have the best ESD performances. For advanced CMOS technology, a standard RF IO library for the whole RF design community is now available. Different flavors of RFIOs have been developed taking into account not only RF constraints but also assembly and test compatibility. Moreover spur mitigation and RF isolation techniques have also been considered during this development. This presentation will give an overview of the development of RFIOs in TSMCs CLN65 technology and the perspectives for the coming technology nodes, i.e. CLN45 and CLN32. C1. Concepts for effective ESD devices - Zhihao Pan The improvement of ESD devices is vital for NXP to stay competitive in the market. The aim of the project is to build up a knowledge base and create concepts with simulation and prototypes for effective ESD protection devices. Within the framework of the project a PhD thesis will be written. The main target is to-build calibrated model for ESD simulations-develop concepts for effective ESD protection devices (single diodes, back to back, rail to rail). C2. System level ESD protection for HDMI in CMOS14 - Theo Smedes, Frederic Darthenay, Sebastien Jacquet For HDMI interfaces it was deemed to be a competitive advantage if the IC could withstand 8 kV system level stress without external protections. Therefore a special APIO cell was developed that is intended to pass the worst-case stress, i.e. with direct grounding. The presentation will briefly describe the assumptions, calculations and chosen solution(s).

C3. Development of IEC 61000-4-2 ESD at Chip Level - Ted Mohlman, Alma Anderson This work has been requested by Marketing as a requirement from some of our customers. These customers have indicated that other IC manufacturers (our competitors) are stating that their product meet this specification. The decision was made to develop this test capability locally in the Tempe site for PL-IP products. Development of the equipment, procedure, and data will be presented. Currently, the data collected on the PCA9517A shows that the Tempe bench setup correlates to the Caen EOS/ESD Lab bench setup (Contact discharge: >10kv) when using a Simplified IEC Bench configuration. C4. System level ESD discussion Rudolf Velghe Improving the robustness against system-level ESD for certain classes of products is an aim for several products. In this discussion we want to collect and discuss requirements, ideas, status, etc. D1. ESD review of TJA1042 and TJA1051 - Rudolf Velghe, Hans van Zwol, T.Scheepers, E. Toy In close cooperation with ABL design development groups in San Jose and Nijmegen, ESD protection solutions for 2 CAN transceivers, TJA1042 and TJA105, processed in A-BCD3 process technology have been implemented. This presentation will discuss the ESD review method used and the ESD results, illustrated with some examples. D2. Of the grounded gate nmost - Gijs de Raad, Edgar Olthof During the transfer of ABCD3 from Boeblingen to ICN8, it was found that the TLP-fail current of the 5V grounded gate nmost did not always scale properly with the device width. The underlying problem was that the addition of a delta-Vt implant caused the ggnmost to not always turn on along its full device width. This has initiated further research into what determines the width over which a ggnmost turns on, and how the design can be optimized to ensure the ggnmost turning on over its full device width. E1. Working with PERD Wolfgang Scheucher, Bart Huitsing The ESD results of an I/O Test-IC for a CMOS14 library, designed by an external supplier showing ESD weaknesses starting already at 400VHBM! This presentation will be about: - a systematic way about dealing with more than 7k ESD Design rule violations - split them into workpackages for review groups - rate the violation to get finally priorized lists of execution for the redesign team - comparison of PERD outputs with already detected problems E2a. ESD Verfication Methods Nitesh Trivedi, Michael G. Khazhinsky, Vesselin Vassilev, Harald Gossner, Rosario Consiglio, Enrico Franell, Kelvin Hsueh In this presentation we describe the essential requirements of the ESD EDA verification flow which would be aligned within the IC design community. The proposed verification flow offers systematic approach to check ESD robustness across all IC blocks during conceptual phase, main design phase and final IC verification. E2b. PLT ESD Checktools - Jean Fleurimont ESD verification methodology has to be an integral part of the design flow within Business Units, rather than a singular activity finished before tape-out. Early pre-silicon ESD checking and automation is needed to tackle large designs and improve the manual I/O ring review process. We present two such tools (in prototype status) that provide the user with an accurate measure of layout robustness and also improve ring review process. Optimum & OhmCheck tools will be presented. E2c. Top level circuit simulation as an ESD verification method - Hans van Zwol A recent approach to automate ESD reviews in NXP is to use top-level circuit simulation using simplified device models. An ESD discharge between any pin pair can be simulated and warnings are given if a device is overstressed. The approach has been demonstrated in A-BCD3 on mixed signal HV circuits containing up to 20 k transistors. Typical failures found include incorrect ESD protections and unintended low-ohmic paths through the core. E3. ESD Tools Roadmap - Nitesh Trivedi, Hans van Zwol, Jean Fleurimont Pre-Si verification of ESD robustness is becoming more difficult and time is consuming and error prone. Status of last year ESDChecktools projects i.e. PERD and Pathfinder will be presented.

Introduction of ESDChecktool team and their plans for 2008 will be discussed. This session is intended to be an interactive discussion where we present our current ESD check-tools suite and openly discuss with potential customers what new areas of focus are most needed for their processes and technologies. We hope to gain a better insight into the requirements for different design styles e.g. use of library vs. custom made IO, CMOS vs. non-CMOS, etc throughout all of NXP. This discussion will help in planning our automation roadmap. F1. On the Relevance of IC ESD Performance to Product Quality - Theo Smedes, Yorgos Christoforou Correlations between ESD stress results and return rates are investigated for various product types. It appears that CDM data relates better to product quality than HBM and/or MM data. The paper clearly demonstrates the need for application specific stress standards to cover threads coming from external connections. F2. On the screening of potential EOS/ESD fails at WT/FT Yorgos Christoforou, Mohammed Lemnawar From WT/FT screening experiences the last years, it seems that there is a strong correlation between screening methods and EOS/ESD PPM reduction. In our presentation we will present results experienced with several products from A-BL, we will address the yield correlation to EOS/ESD PPM, we will deepen to the screening methodology for ESD structures, we will make and discuss the separation between EOS and ESD PPM and we will address potential physical mechanisms that are at the origin of the phenomenon. F3. EOS-TME status and EOS project Jean Luc Lefebvre Automotive market with its zero defect requirement push IC suppliers to improve their product robustness. NXP has setup ZD program in order to reach the target. EOS return is one of the main categories. A project called Product Absolute Maximum Rating and OVS test is running through Q&R org and EOS-TME team. This presentation describes the project itself including an overall EOS vision. G1. Realizing both ESD- and functional robustness in a CMOS18S DC-DC converter design Dirk Looijmans, Bart Huitsing DC-DC converters are known for generating significant voltage spikes because of their switching operation. Resulting from their behaviour conflicts can arise between guaranteeing both ESD robustness and good functional performance as well. Measures taken to improve ESD performance can have an effect even in the normal operation mode of the converter, and requirements on the functional characteristics may give extra constraints for the ESD protection. Examples of this and related solutions are presented, resulting from the practical design in CMOS18S of a DC-DC converter as part of an embedded power supply unit in a 5V powered mobile head-set IC. G2. Low level HBM and CDM failures in a CMOS090 product - Derek Ward The qualification of a key Digital TV device - PNX5100 - in CMOS090 demonstrated a very poor ESD performance, passing at only 200V HBM and 200V CDM. The analysis of these failures is described and the root cause, which is related to usage of the Vddco pad type, is discussed. G3. Georgia's HTOL re-qualification fails Dietrich Elsner During Georgia's transfer from Crolles2 to TSMC some re-qualification had to be done, which partly failed to everyone's surprise. Although on the one hand the qualification stress HTOL (High Temperature Operating Life) has nothing to do with ESD/EOS, in the end of the day we think that the rood cause of the fails was some kind of unwanted ESD/EOS. Let me share some pictures from FA. H1. A case study of Latch-Up problems Tianyuan Wu A recent case of Latch-Up problems will be presented and discussed. A product processed in CMOS18 with high resistive substrate will be used as example. Using a combination of stressing and physical analysis it is tried to identify the root cause for the LU mechanism in each problem. After that possible solutions are proposed. Lessons are learned for other designs. H2. Latch-up risk in negative-bias circuitry - Hans van Zwol Various design teams request part of their circuit to operate below substrate, in particular for PMUs and True Ground Audio output. This creates a new type of latch-up risk. We will explain the new

failure mode in detail and show from measurements on C090 test structures and on the full IC how the PNX0151 was designed LU-safe. I1. ESD simulations of discrete bipolar diodes and transistors - Steffen Holland, Hans-Martin Ritter, Olaf Pfennigstorf, Jochen Wynants, Stefan Berglund In the first part the key parameters for ESD robustness of bipolar discrete diodes and transistors are presented. In the second part simulation results are shown for an ESD protection of resistor equipped transistors. These devices fail at 0.5 kV HBM. The aim is to double the ESD robustness to 1kV. The protection has to fulfill a 50 V minimum blocking voltage in both directions and has to be integrated in an existing transistor design. I2. Investigation of TLP discharges in RF-MEMS devices - Wim de Cock, Bart Huijtsing, Marcel van Gils Electro Static Discharge phenomena in RF-MEMS devices are quite different from those in the usual semiconductor devices, since the discharge has to pass a micro-scale air gap in series with a nitride capacitor.Few literature is available on the discharge mechanisms in micro-gaps. Experiments with TLP discharges were made to unveil the physical mechanisms playing a role in these discharges. Experiments include variations in design, various air gaps, voltage/current/pulse slope variations, visual discharge observations, device parameter degradation and microscopic examination. J1. New ESD-CDM calibration issues - Michal Polewski, Arjan van IJzerloo, Victoria Kiriliouk In the past two years CDM-ESD testing took important place in the IC qualification program. All NXP end-customers require robustness of the supplied IC beyond 500V-1000V. The CDM-ESD model is however very sensitive for equipment parasitics and metrology technics resulting in large discrepancies during interpretation of CDM results. In this presentation two aspects of CDM calibration procedure are addressed: 1) Differences in the CDM discharge current peaks due to e.g. change of dielectric foil parameters are observed during qualification stresses but cannot be detected by the calibration procedure of ESDA standard.2) Connection to the zap detector input (ZDI) is required by end-customers during the CDM qualification stresses but it is not covered by Jedec&ESDA calibration procedures. Significant influence on the CDM monitoring results is shown due to the presence of ZDI connection. Case of the damaged shielding in the cable connected to the ZDI showed additional impact on the monitoring results that are relevant for the analysis. These lead to the conclusion that current calibration procedure does not cover various cases that can take place on the tester side and therefore the additional calibration parameters are proposed to be introduced during ESD-CDM verification procedure. Using new discharge current waveform capturing software the comparison of the JEDEC and ESDA (Q100) standards for ESD-CDM testing will be presented. It will be shown that the standard Q100 represents the worst-case CDM test condition (from the peak current point of view) and therefore is recommended for cases when qualification of the device should fulfil both consumer and automotive market requirements. J2. ESD Test Artifacts- Fulgencio Arjona Gomez The effect of ESD-tester issues on HBM test will be discussed on 2 cases. a) Experimental results of the influence of tester parasitic on HBM stress will be discussed.b) The so-called pre-charge problem will be presented.