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  • ECE 442 Solid State Devices & Circuits CMOS Process

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    kanjsame
    20 vues15 pages
    The document describes the basic fabrication process for CMOS integrated circuits. It involves cleaning silicon wafers in clean rooms, depositing and patterning various layers through steps like oxidation, diffusion, ion implantation, and photolithography. Key steps include doping the substrate, defining active device regions, growing field oxide for isolation, patterning the polysilicon gate, and doping the source and drain regions through self-aligned implantation. Metallization is then used to interconnect the transistors, and the chips are diced and packaged. The process relies on precise photolithography and multiple patterned depositions to build up the transistor layers in a self-aligned manner.

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    The document describes the basic fabrication process for CMOS integrated circuits. It involves cleaning silicon wafers in clean rooms, depositing and patterning various layers through steps like oxidation, diffusion, ion implantation, and photolithography. Key steps include doping the substrate, defining active device regions, growing field oxide for isolation, patterning the polysilicon gate, and doping the source and drain regions through self-aligned implantation. Metallization is then used to interconnect the transistors, and the chips are diced and packaged. The process relies on precise photolithography and multiple patterned depositions to build up the transistor layers in a self-aligned manner.

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    20 vues15 pages

    ECE 442 Solid State Devices & Circuits CMOS Process

    Transféré par

    kanjsame
    The document describes the basic fabrication process for CMOS integrated circuits. It involves cleaning silicon wafers in clean rooms, depositing and patterning various layers through steps like oxidation, diffusion, ion implantation, and photolithography. Key steps include doping the substrate, defining active device regions, growing field oxide for isolation, patterning the polysilicon gate, and doping the source and drain regions through self-aligned implantation. Metallization is then used to interconnect the transistors, and the chips are diced and packaged. The process relies on precise photolithography and multiple patterned depositions to build up the transistor layers in a self-aligned manner.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 15

    ECE442 SolidStateDevices&Circuits CMOSProcess

    Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu


    JoseE.SchuttAine ECE442 Spring2007

    Basic Fabrication Process Chart

    Clean Rooms
    Semiconductor processing is performed in ultraclean facilities called clean rooms Sophisticated filtration to remove airbone particulates Workers must wear special uniforms to minimize introduction of contaminants

    JoseE.SchuttAine ECE442 Spring2007

    Clean Room Facility

    JoseE.SchuttAine ECE442 Spring2007

    CMOS Process Steps


    Wafer Preparation
    Crystal orientation, doping, polishing Typical wafers are 400 m to 600 m thick

    Oxidation
    Silicon reacts with oxygen to form silicon dioxide SiO2 Use high temperature (>1000 oC) to speed up process SiO2 is effective mask against impurities

    Diffusion
    Atoms move from low to high concentration region in Si Performed at high temperature to obtain speed When wafer is cooled impurities are frozen in Si Boron, arsenic, phosphorus are common dopants

    JoseE.SchuttAine ECE442 Spring2007

    Process Steps
    Ion Implantation
    Ions are accelerated by electric field Produces more accurate and reproducible profiles than diffusion

    Chemical Vapor Deposition


    Used to deposit various materials such as Si3N4 on Si

    Metallization
    Metal layer deposited via sputtering process

    Photolithography
    Wafer is coated with photoresist Mask selectively exposes some regions to UV light High precision is required

    Dicing & Packaging


    ICs are separated from wafer Die attach and wire bonding
    JoseE.SchuttAine ECE442 Spring2007

    Step 1 n-Well Diffusion

    Diffusion Process
    Regions for diffusion are exposed after oxide is etched Phosphorus diffuses faster than arsenic into substrate
    JoseE.SchuttAine ECE442 Spring2007

    Step 2 Define Active Regions

    Process
    Active regions are where transistors are to be placed Use silicon nitride (Si3N4) to mask oxidation

    JoseE.SchuttAine ECE442 Spring2007

    Step 3 Local Oxidation (LOCOS)

    Process
    Thick field oxide appears in region between transistors Field oxide isolate transistors Allows interconnection layers to be routed to top
    JoseE.SchuttAine ECE442 Spring2007

    Step 4 Gate Formation

    Process
    Most critical step in CMOS process Polysilicon layer is deposited and patterned Fine resolution produces short channel length
    JoseE.SchuttAine ECE442 Spring2007

    Step 5 n+ Diffusion

    Process
    Photoresist protects p-MOSFET region Polysilicon gate acts as barrier for the implant Field oxide prevents formation of n+ from outside active region Polysilicon gate is self-aligned
    JoseE.SchuttAine ECE442 Spring2007

    10

    Step 6 p+ Diffusion

    Process
    Channel length is defined by gate mask alone Polysilicon gate acts as barrier for the implant Gate protects channel region
    JoseE.SchuttAine ECE442 Spring2007

    self alignment

    11

    Step 7 Contact Holes

    Process
    CVD oxide deposited Photomask is used to define contact window opening Etch oxide with wet or dry process
    JoseE.SchuttAine ECE442 Spring2007

    12

    Step 8 Metallization

    Process
    Evaporate or sputter thin layer of aluminum Use masking to pattern interconnection Use CVD oxide for passivation as protective layer
    JoseE.SchuttAine ECE442 Spring2007

    13

    CMOS Layout

    JoseE.SchuttAine ECE442 Spring2007

    14

    CMOS Layout

    JoseE.SchuttAine ECE442 Spring2007

    15

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