PROJECT 2: SIMPLE CALCULATOR

Project Specification: The input to the calculator is an eight bit wide bus DS, a single bit control signal START and a global reset signal RESET. The most significant bit DS(1) of the bus indicates the format of the byte available on DS, i.e. if DS(1) = 1, the byte is an operator and if DS(1) = 0, the byte is an operand. If the current byte is an operator, then the least significant two bits, DS(7) and DS(8), specify the operation to be performed according to the table below. If the current byte is an operand, bits DS(2)and DS(8) specify the value of the operand (DS(2) is the sign bit) as a seven-bit number in twos complement format. DS(1) 0 1 1 1 1 DS(7)-DS(8) --00 01 10 11 Operator --+ * / Note DS(2)-DS(8) is the operand Addition Subtraction Multiplication (Multiplier is a power of 2) Division (Divisor is a power of 2)

Examples: DS(1)-DS(8) 1000 0010 0000 1010 0111 1101 Interpretation Multiplication operator (+10) (-3)

The user enters an operand or an operator by setting the bit values on the dip switches and pressing and releasing the START button. The calculator reads the value into a buffer and decodes it. If it is an operand, the data value is sign-extended and pushed onto a stack. If it is an operator, the top two items on the stack are removed, the operation is performed, and the result is pushed back onto the stack. The following table shows the format for the operation. The stack has a width of 12 bits and a depth of 4. Second from Top A A A A Top B B B B Operator + * / Operation A+B A-B A*B A/B

The arithmetic expression for the calculator is in the reverse Polish notation (RPN). For example, the following expression (in in-fix notation) 3*4 + 6/2 is expressed in RPN as 34*62/+ The use of RPN allows the expression to be evaluated by scanning the expression from left to right and saving values on a pushdown stack. If a value is scanned, that value is 1

pushed onto the top of the stack. If an operator is scanned, the top two items are removed from the stack, the specified operation is performed, and the result is pushed onto the stack. The following table shows how the RPN expression 872/2*-5+ is evaluated. Item Input DS(1) DS(2)-DS(8) DS(7)-DS(8) 8 7 2 3 2 2 1 5 0 Display after Operation 0 8 7 2 3 2 6 2 5 7 Stack after Operation Empty 8 8,7 8,7,2 8,3 8,3,2 8,6 2 2,5 7

RESET 8 7 2 / 2 * 5 +

0 0 0 1 0 1 1 0 1

The calculator should produce the correct result as long as the maximum stack depth of 4 is not exceeded or an arithmetic overflow does not occur. The result is 12 bits wide.

Task: Prepare an algorithmic VHDL model of the calculator. The system inputs are START, RESET, DS, CLK. The output of the system is RESULT. Simulate the following operation sequences (given in in-fix notation). The RPN form for the first expression is given. You will need to translate the second two expressions into RPN notation. Note: {-5} means that you enter a negative number already in correct twos complement format. (21+5*2)/2 16 [21 5 2 *+2 / 16 -] 8*(5-(2+(3*4))) (60*32-41/16)*{-64} Synthesize the code using a logic synthesis tool.

Project Report: Your report must contain a description of the logical design, VHDL source code of the design, testbench code, simulation graphs and synthesis report. The VHDL codes must be commented wherever necessary. Place a printout of your project report in Dr. Songs mailbox by 5:00 pm on November 1, 2004. In addition, email the source code of the design and the corresponding testbench code to rnandi@cecs.pdx.edu by 5:00 pm on November 1, 2004. Do not send any attachments. Paste and format the source code & testbench code on the body of the email with the subject line as ECE x81: Project 2, <last names of the project group members>.