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Pentium 4 and new Celeron processors use Intel's seventh generation architecture. Pentium 4 transfers four data per clock cycle, which is four times its actual clock rate. The datapath between the L2 memory cache and The L1 data cache is 256-bit wide. The L1 instruction cache is now after the decode unit, with a new location.
Pentium 4 and new Celeron processors use Intel's seventh generation architecture. Pentium 4 transfers four data per clock cycle, which is four times its actual clock rate. The datapath betwe…